From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>
Cc: Anup Patel <anup@brainfault.org>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Prabhakar <prabhakar.csengg@gmail.com>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list
Date: Wed, 27 Jul 2022 10:51:53 +0200 [thread overview]
Message-ID: <f449cb56-5d16-1443-895f-cf2119c5dea9@linaro.org> (raw)
In-Reply-To: <20220726180623.1668-4-prabhakar.mahadev-lad.rj@bp.renesas.com>
On 26/07/2022 20:06, Lad Prabhakar wrote:
> The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP
> Single) from Andes. In preparation to add support for RZ/Five SoC add
> the Andes AX45MP core to the list.
>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
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next prev parent reply other threads:[~2022-07-27 8:52 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-26 18:06 [PATCH 0/6] Add support for Renesas RZ/Five SoC Lad Prabhakar
2022-07-26 18:06 ` [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch Lad Prabhakar
2022-07-27 8:50 ` Krzysztof Kozlowski
2022-07-27 8:55 ` Lad, Prabhakar
2022-07-27 8:53 ` Krzysztof Kozlowski
2022-07-27 9:00 ` Lad, Prabhakar
2022-07-27 9:31 ` Krzysztof Kozlowski
2022-07-27 9:48 ` Lad, Prabhakar
2022-08-11 15:26 ` Geert Uytterhoeven
2022-08-11 23:37 ` Lad, Prabhakar
2022-07-27 15:43 ` Rob Herring
2022-07-26 18:06 ` [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2022-07-27 8:51 ` Krzysztof Kozlowski
2022-07-26 18:06 ` [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2022-07-27 8:51 ` Krzysztof Kozlowski [this message]
2022-07-26 18:06 ` [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK Lad Prabhakar
2022-07-27 8:54 ` Krzysztof Kozlowski
2022-07-27 9:05 ` Lad, Prabhakar
2022-07-27 9:27 ` Biju Das
2022-07-27 9:35 ` Lad, Prabhakar
2022-07-27 9:54 ` Krzysztof Kozlowski
2022-07-27 10:06 ` Lad, Prabhakar
2022-07-27 10:09 ` Krzysztof Kozlowski
2022-07-27 11:37 ` Lad, Prabhakar
2022-07-27 11:44 ` Krzysztof Kozlowski
2022-07-27 12:21 ` Biju Das
2022-07-27 12:36 ` Krzysztof Kozlowski
2022-07-27 12:56 ` Biju Das
2022-07-27 13:00 ` Krzysztof Kozlowski
2022-07-27 13:29 ` Conor.Dooley
2022-07-27 15:32 ` Lad, Prabhakar
2022-08-11 15:42 ` Geert Uytterhoeven
2022-08-12 6:23 ` Krzysztof Kozlowski
2022-08-12 9:49 ` Lad, Prabhakar
2022-08-12 15:10 ` Palmer Dabbelt
2022-07-26 18:06 ` [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar
2022-07-26 18:49 ` Conor.Dooley
2022-07-27 8:19 ` Lad, Prabhakar
2022-07-26 18:06 ` [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2022-07-26 18:25 ` Conor.Dooley
2022-07-26 18:53 ` Conor.Dooley
2022-07-27 8:09 ` Lad, Prabhakar
2022-07-27 8:21 ` Conor.Dooley
2022-07-27 8:30 ` Lad, Prabhakar
2022-07-27 8:55 ` Krzysztof Kozlowski
2022-07-27 9:08 ` Lad, Prabhakar
2022-07-26 18:51 ` [PATCH 0/6] Add support " Conor.Dooley
2022-07-27 8:00 ` Lad, Prabhakar
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