From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: "Lad, Prabhakar" <prabhakar.csengg@gmail.com>
Cc: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Anup Patel <anup@brainfault.org>,
Linux-Renesas <linux-renesas-soc@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
LKML <linux-kernel@vger.kernel.org>,
Biju Das <biju.das.jz@bp.renesas.com>
Subject: Re: [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK
Date: Wed, 27 Jul 2022 12:09:09 +0200 [thread overview]
Message-ID: <e31e0c1f-4755-704e-8428-93970877d8f5@linaro.org> (raw)
In-Reply-To: <CA+V-a8u1VW9xaj2KjySyMuegpisLVENO_6uJOpAFZGbKziYLYw@mail.gmail.com>
On 27/07/2022 12:06, Lad, Prabhakar wrote:
> Hi Krzysztof,
>
> On Wed, Jul 27, 2022 at 10:54 AM Krzysztof Kozlowski
> <krzysztof.kozlowski@linaro.org> wrote:
>>
>> On 27/07/2022 11:05, Lad, Prabhakar wrote:
>>> Hi Krzysztof,
>>>
>>> Thank you for the review.
>>>
>>> On Wed, Jul 27, 2022 at 9:54 AM Krzysztof Kozlowski
>>> <krzysztof.kozlowski@linaro.org> wrote:
>>>>
>>>> On 26/07/2022 20:06, Lad Prabhakar wrote:
>>>>> Document Renesas RZ/Five (R9A07G043) SoC and SMARC EVK based on this SoC.
>>>>>
>>>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>>> ---
>>>>> .../devicetree/bindings/riscv/renesas.yaml | 49 +++++++++++++++++++
>>>>> 1 file changed, 49 insertions(+)
>>>>> create mode 100644 Documentation/devicetree/bindings/riscv/renesas.yaml
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/riscv/renesas.yaml b/Documentation/devicetree/bindings/riscv/renesas.yaml
>>>>> new file mode 100644
>>>>> index 000000000000..f72f8aea6a82
>>>>> --- /dev/null
>>>>> +++ b/Documentation/devicetree/bindings/riscv/renesas.yaml
>>>>> @@ -0,0 +1,49 @@
>>>>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>>>>> +%YAML 1.2
>>>>> +---
>>>>> +$id: http://devicetree.org/schemas/riscv/renesas.yaml#
>>>>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> +
>>>>> +title: Renesas RZ/Five Platform Device Tree Bindings
>>>>> +
>>>>> +maintainers:
>>>>> + - Geert Uytterhoeven <geert+renesas@glider.be>
>>>>> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>>> +
>>>>> +# We want to ignore this schema if the board is SMARC EVK based on ARM64 arch
>>>>> +select:
>>>>> + not:
>>>>> + properties:
>>>>> + compatible:
>>>>> + contains:
>>>>> + items:
>>>>
>>>> I think you should rather ignore the RiscV SoCs, not specific board.
>>>>
>>> You mean to ignore ARM/64 SoCs?
>>>
>>> Agreed just the below enum, should do the trick.
>>>
>>> - enum:
>>> - renesas,r9a07g043u11
>>> - renesas,r9a07g043u12
>>> - renesas,r9a07g044c1
>>> - renesas,r9a07g044c2
>>> - renesas,r9a07g044l1
>>> - renesas,r9a07g044l2
>>> - renesas,r9a07g054l1
>>> - renesas,r9a07g054l2
>>>
>>>
>>>>> + - const: renesas,smarc-evk
>>>>> + - enum:
>>>>> + - renesas,r9a07g043u11
>>>>> + - renesas,r9a07g043u12
>>>>> + - renesas,r9a07g044c1
>>>>> + - renesas,r9a07g044c2
>>>>> + - renesas,r9a07g044l1
>>>>> + - renesas,r9a07g044l2
>>>>> + - renesas,r9a07g054l1
>>>>> + - renesas,r9a07g054l2
>>>>> + - enum:
>>>>> + - renesas,r9a07g043
>>>>> + - renesas,r9a07g044
>>>>> + - renesas,r9a07g054
>>>>
>>>> Did you actually test that it works and properly matches?
>>>>
>>> Yes I have run the dtbs_check and dt_binding _check for ARM64 and
>>> RISC-V. Do you see any cases where it can fail?
>>
>>
>> Just remove the renesas,smarc-evk2 from
>> arch/arm64/boot/dts/renesas/r9a07g043u11-smarc.dts. Do you see the
>> error? Not from this schema. The only error you will see is that no
>> matching schema was found.
>>
> I did run the dtbs_check test as per your suggestion (below is the
> log) and didn't see "no matching schema error"
>
So you do not see any errors at all. Then it does not work, does it?
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-07-27 10:09 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-26 18:06 [PATCH 0/6] Add support for Renesas RZ/Five SoC Lad Prabhakar
2022-07-26 18:06 ` [PATCH 1/6] dt-bindings: arm: renesas: Ignore the schema for RISC-V arch Lad Prabhakar
2022-07-27 8:50 ` Krzysztof Kozlowski
2022-07-27 8:55 ` Lad, Prabhakar
2022-07-27 8:53 ` Krzysztof Kozlowski
2022-07-27 9:00 ` Lad, Prabhakar
2022-07-27 9:31 ` Krzysztof Kozlowski
2022-07-27 9:48 ` Lad, Prabhakar
2022-08-11 15:26 ` Geert Uytterhoeven
2022-08-11 23:37 ` Lad, Prabhakar
2022-07-27 15:43 ` Rob Herring
2022-07-26 18:06 ` [PATCH 2/6] dt-bindings: riscv: Sort the CPU core list alphabetically Lad Prabhakar
2022-07-27 8:51 ` Krzysztof Kozlowski
2022-07-26 18:06 ` [PATCH 3/6] dt-bindings: riscv: Add Andes AX45MP core to the list Lad Prabhakar
2022-07-27 8:51 ` Krzysztof Kozlowski
2022-07-26 18:06 ` [PATCH 4/6] dt-bindings: riscv: Add DT binding documentation for Renesas RZ/Five SoC and SMARC EVK Lad Prabhakar
2022-07-27 8:54 ` Krzysztof Kozlowski
2022-07-27 9:05 ` Lad, Prabhakar
2022-07-27 9:27 ` Biju Das
2022-07-27 9:35 ` Lad, Prabhakar
2022-07-27 9:54 ` Krzysztof Kozlowski
2022-07-27 10:06 ` Lad, Prabhakar
2022-07-27 10:09 ` Krzysztof Kozlowski [this message]
2022-07-27 11:37 ` Lad, Prabhakar
2022-07-27 11:44 ` Krzysztof Kozlowski
2022-07-27 12:21 ` Biju Das
2022-07-27 12:36 ` Krzysztof Kozlowski
2022-07-27 12:56 ` Biju Das
2022-07-27 13:00 ` Krzysztof Kozlowski
2022-07-27 13:29 ` Conor.Dooley
2022-07-27 15:32 ` Lad, Prabhakar
2022-08-11 15:42 ` Geert Uytterhoeven
2022-08-12 6:23 ` Krzysztof Kozlowski
2022-08-12 9:49 ` Lad, Prabhakar
2022-08-12 15:10 ` Palmer Dabbelt
2022-07-26 18:06 ` [PATCH 5/6] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Lad Prabhakar
2022-07-26 18:49 ` Conor.Dooley
2022-07-27 8:19 ` Lad, Prabhakar
2022-07-26 18:06 ` [PATCH 6/6] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Lad Prabhakar
2022-07-26 18:25 ` Conor.Dooley
2022-07-26 18:53 ` Conor.Dooley
2022-07-27 8:09 ` Lad, Prabhakar
2022-07-27 8:21 ` Conor.Dooley
2022-07-27 8:30 ` Lad, Prabhakar
2022-07-27 8:55 ` Krzysztof Kozlowski
2022-07-27 9:08 ` Lad, Prabhakar
2022-07-26 18:51 ` [PATCH 0/6] Add support " Conor.Dooley
2022-07-27 8:00 ` Lad, Prabhakar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=e31e0c1f-4755-704e-8428-93970877d8f5@linaro.org \
--to=krzysztof.kozlowski@linaro.org \
--cc=anup@brainfault.org \
--cc=aou@eecs.berkeley.edu \
--cc=biju.das.jz@bp.renesas.com \
--cc=devicetree@vger.kernel.org \
--cc=geert+renesas@glider.be \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=magnus.damm@gmail.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=prabhakar.csengg@gmail.com \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).