From: Anup Patel <anup@brainfault.org>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: Damien Le Moal <Damien.LeMoal@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
Radim K <rkrcmar@redhat.com>, Anup Patel <Anup.Patel@wdc.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Christoph Hellwig <hch@infradead.org>,
Atish Patra <Atish.Patra@wdc.com>,
Alexander Graf <graf@amazon.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Thomas Gleixner <tglx@linutronix.de>,
"linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>
Subject: Re: [PATCH v7 10/21] RISC-V: KVM: Handle MMIO exits for VCPU
Date: Mon, 23 Sep 2019 18:39:43 +0530 [thread overview]
Message-ID: <CAAhSdy1-1yxMnjzppmUBxtSOAuwWaPtNZwW+QH1O7LAnEVP8pg@mail.gmail.com> (raw)
In-Reply-To: <8c44ac8a-3fdc-b9dd-1815-06e86cb73047@redhat.com>
On Mon, Sep 23, 2019 at 4:42 PM Paolo Bonzini <pbonzini@redhat.com> wrote:
>
> On 04/09/19 18:15, Anup Patel wrote:
> > + unsigned long guest_sstatus =
> > + vcpu->arch.guest_context.sstatus | SR_MXR;
> > + unsigned long guest_hstatus =
> > + vcpu->arch.guest_context.hstatus | HSTATUS_SPRV;
> > + unsigned long guest_vsstatus, old_stvec, tmp;
> > +
> > + guest_sstatus = csr_swap(CSR_SSTATUS, guest_sstatus);
> > + old_stvec = csr_swap(CSR_STVEC, (ulong)&__kvm_riscv_unpriv_trap);
> > +
> > + if (read_insn) {
> > + guest_vsstatus = csr_read_set(CSR_VSSTATUS, SR_MXR);
>
> Is this needed? IIUC SSTATUS.MXR encompasses a wider set of permissions:
>
> The HS-level MXR bit makes any executable page readable. {\tt
> vsstatus}.MXR makes readable those pages marked executable at the VS
> translation level, but only if readable at the guest-physical
> translation level.
>
> So it should be enough to set SSTATUS.MXR=1 I think. But you also
> shouldn't set SSTATUS.MXR=1 in the !read_insn case.
I was being overly cautious here. Initially, I thought SSTATUS.MXR
applies only to Stage2 and VSSTATUS.MXR applies only to Stage1.
I agree with you. The HS-mode should only need to set SSTATUS.MXR.
>
> Also, you can drop the irq save/restore (which is already a save/restore
> of SSTATUS) since you already write 0 to SSTATUS.SIE in your csr_swap.
> Perhaps add a BUG_ON(guest_sstatus & SR_SIE) before the csr_swap?
I had already dropped irq save/restore in v7 series and having BUG_ON()
on guest_sstatus here would be better.
>
> > + asm volatile ("\n"
> > + "csrrw %[hstatus], " STR(CSR_HSTATUS) ", %[hstatus]\n"
> > + "li %[tilen], 4\n"
> > + "li %[tscause], 0\n"
> > + "lhu %[val], (%[addr])\n"
> > + "andi %[tmp], %[val], 3\n"
> > + "addi %[tmp], %[tmp], -3\n"
> > + "bne %[tmp], zero, 2f\n"
> > + "lhu %[tmp], 2(%[addr])\n"
> > + "sll %[tmp], %[tmp], 16\n"
> > + "add %[val], %[val], %[tmp]\n"
> > + "2: csrw " STR(CSR_HSTATUS) ", %[hstatus]"
> > + : [hstatus] "+&r"(guest_hstatus), [val] "=&r" (val),
> > + [tmp] "=&r" (tmp), [tilen] "+&r" (tilen),
> > + [tscause] "+&r" (tscause)
> > + : [addr] "r" (addr));
> > + csr_write(CSR_VSSTATUS, guest_vsstatus);
>
> >
> > +#ifndef CONFIG_RISCV_ISA_C
> > + "li %[tilen], 4\n"
> > +#else
> > + "li %[tilen], 2\n"
> > +#endif
>
> Can you use an assembler directive to force using a non-compressed
> format for ld and lw? This would get rid of tilen, which is costing 6
> bytes (if I did the RVC math right) in order to save two. :)
I tried looking for it but could not find any assembler directive
to selectively turn-off instruction compression.
>
> Paolo
>
> > + "li %[tscause], 0\n"
> > +#ifdef CONFIG_64BIT
> > + "ld %[val], (%[addr])\n"
> > +#else
> > + "lw %[val], (%[addr])\n"
> > +#endif
Regards,
Anup
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next prev parent reply other threads:[~2019-09-23 13:10 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-04 16:13 [PATCH v7 00/21] KVM RISC-V Support Anup Patel
2019-09-04 16:13 ` [PATCH v7 01/21] KVM: RISC-V: Add KVM_REG_RISCV for ONE_REG interface Anup Patel
2019-09-19 12:37 ` Paul Walmsley
2019-09-04 16:13 ` [PATCH] RISC-V: Enable KVM for RV64 and RV32 Anup Patel
2019-09-04 16:17 ` Anup Patel
2019-09-04 16:13 ` [PATCH v7 02/21] RISC-V: Add bitmap reprensenting ISA features common across CPUs Anup Patel
2019-09-19 12:56 ` Anup Patel
2019-09-21 10:01 ` Paul Walmsley
2019-09-23 3:39 ` Anup Patel
2019-09-23 15:54 ` Alistair Francis
2019-09-04 16:14 ` [PATCH v7 03/21] RISC-V: Export few kernel symbols Anup Patel
2019-09-19 12:39 ` Paul Walmsley
2019-09-04 16:14 ` [PATCH v7 04/21] RISC-V: Add hypervisor extension related CSR defines Anup Patel
2019-09-04 16:14 ` [PATCH v7 05/21] RISC-V: Add initial skeletal KVM support Anup Patel
2019-09-04 16:14 ` [PATCH v7 06/21] RISC-V: KVM: Implement VCPU create, init and destroy functions Anup Patel
2019-09-23 6:44 ` Alexander Graf
2019-09-23 12:37 ` Anup Patel
2019-09-04 16:14 ` [PATCH v7 07/21] RISC-V: KVM: Implement VCPU interrupts and requests handling Anup Patel
2019-09-04 16:14 ` [PATCH v7 08/21] RISC-V: KVM: Implement KVM_GET_ONE_REG/KVM_SET_ONE_REG ioctls Anup Patel
2019-09-23 3:42 ` Anup Patel
2019-09-04 16:15 ` [PATCH v7 09/21] RISC-V: KVM: Implement VCPU world-switch Anup Patel
2019-09-04 16:15 ` [PATCH v7 10/21] RISC-V: KVM: Handle MMIO exits for VCPU Anup Patel
2019-09-23 6:50 ` Alexander Graf
2019-09-23 11:12 ` Paolo Bonzini
2019-09-23 13:09 ` Anup Patel [this message]
2019-09-23 13:33 ` Paolo Bonzini
2019-09-24 5:07 ` Anup Patel
2019-10-08 22:44 ` Palmer Dabbelt
2019-10-09 4:58 ` Anup Patel
2019-09-04 16:15 ` [PATCH v7 11/21] RISC-V: KVM: Handle WFI " Anup Patel
2019-09-23 6:53 ` Alexander Graf
2019-09-23 12:54 ` Anup Patel
2019-09-04 16:15 ` [PATCH v7 12/21] RISC-V: KVM: Implement VMID allocator Anup Patel
2019-09-04 16:15 ` [PATCH v7 13/21] RISC-V: KVM: Implement stage2 page table programming Anup Patel
2019-09-04 16:15 ` [PATCH v7 14/21] RISC-V: KVM: Implement MMU notifiers Anup Patel
2019-09-04 16:15 ` [PATCH v7 15/21] RISC-V: KVM: Add timer functionality Anup Patel
2019-09-04 16:15 ` [PATCH v7 16/21] RISC-V: KVM: FP lazy save/restore Anup Patel
2019-09-04 16:15 ` [PATCH v7 17/21] RISC-V: KVM: Implement ONE REG interface for FP registers Anup Patel
2019-09-04 16:16 ` [PATCH v7 18/21] RISC-V: KVM: Add SBI v0.1 support Anup Patel
2019-09-05 8:35 ` Andreas Schwab
2019-09-23 7:01 ` Alexander Graf
2019-09-23 12:59 ` Anup Patel
2019-09-04 16:16 ` [PATCH v7 19/21] RISC-V: KVM: Document RISC-V specific parts of KVM API Anup Patel
2019-09-04 16:16 ` [PATCH v7 20/21] RISC-V: Enable VIRTIO drivers in RV64 and RV32 defconfig Anup Patel
2019-09-19 7:54 ` Paul Walmsley
2019-09-04 16:16 ` [PATCH v7 21/21] RISC-V: KVM: Add MAINTAINERS entry Anup Patel
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