From: Atish Patra <Atish.Patra@wdc.com>
To: "hch@lst.de" <hch@lst.de>,
"paul.walmsley@sifive.com" <paul.walmsley@sifive.com>,
"palmer@sifive.com" <palmer@sifive.com>
Cc: "linux-riscv@lists.infradead.org"
<linux-riscv@lists.infradead.org>,
Damien Le Moal <Damien.LeMoal@wdc.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 09/15] riscv: implement remote sfence.i natively for M-mode
Date: Tue, 20 Aug 2019 21:04:57 +0000 [thread overview]
Message-ID: <d3ca4c6174dea85a4a55f2ec62875b226f05b69d.camel@wdc.com> (raw)
In-Reply-To: <20190813154747.24256-10-hch@lst.de>
On Tue, 2019-08-13 at 17:47 +0200, Christoph Hellwig wrote:
> The RISC-V ISA only supports flushing the instruction cache for the
> local
> CPU core. For normal S-mode Linux remote flushing is offloaded to
> machine mode using ecalls, but for M-mode Linux we'll have to do it
> ourselves. Use the same implementation as all the existing open
> source
> SBI implementations by just doing an IPI to all remote cores to
> execute
> th sfence.i instruction on every live core.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> ---
> arch/riscv/mm/cacheflush.c | 31 +++++++++++++++++++++++++++----
> 1 file changed, 27 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> index 9ebcff8ba263..10875ea1065e 100644
> --- a/arch/riscv/mm/cacheflush.c
> +++ b/arch/riscv/mm/cacheflush.c
> @@ -10,10 +10,35 @@
>
> #include <asm/sbi.h>
>
> +#ifdef CONFIG_M_MODE
> +static void ipi_remote_fence_i(void *info)
> +{
> + return local_flush_icache_all();
> +}
> +
> +void flush_icache_all(void)
> +{
> + on_each_cpu(ipi_remote_fence_i, NULL, 1);
> +}
> +
> +static void flush_icache_cpumask(const cpumask_t *mask)
> +{
> + on_each_cpu_mask(mask, ipi_remote_fence_i, NULL, 1);
> +}
> +#else /* CONFIG_M_MODE */
> void flush_icache_all(void)
> {
> sbi_remote_fence_i(NULL);
> }
> +static void flush_icache_cpumask(const cpumask_t *mask)
> +{
> + cpumask_t hmask;
> +
> + cpumask_clear(&hmask);
> + riscv_cpuid_to_hartid_mask(mask, &hmask);
> + sbi_remote_fence_i(hmask.bits);
> +}
> +#endif /* CONFIG_M_MODE */
>
> /*
> * Performs an icache flush for the given MM context. RISC-V has no
> direct
> @@ -28,7 +53,7 @@ void flush_icache_all(void)
> void flush_icache_mm(struct mm_struct *mm, bool local)
> {
> unsigned int cpu;
> - cpumask_t others, hmask, *mask;
> + cpumask_t others, *mask;
>
> preempt_disable();
>
> @@ -47,9 +72,7 @@ void flush_icache_mm(struct mm_struct *mm, bool
> local)
> cpumask_andnot(&others, mm_cpumask(mm), cpumask_of(cpu));
> local |= cpumask_empty(&others);
> if (mm != current->active_mm || !local) {
> - cpumask_clear(&hmask);
> - riscv_cpuid_to_hartid_mask(&others, &hmask);
> - sbi_remote_fence_i(hmask.bits);
> + flush_icache_cpumask(&others);
> } else {
> /*
> * It's assumed that at least one strongly ordered
> operation is
Reviewed-by: Atish Patra <atish.patra@wdc.com>
--
Regards,
Atish
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next prev parent reply other threads:[~2019-08-20 21:05 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-13 15:47 RISC-V nommu support v3 Christoph Hellwig
2019-08-13 15:47 ` [PATCH 01/15] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-08-13 17:44 ` Paul Walmsley
2019-08-14 9:06 ` Marc Zyngier
2019-08-13 15:47 ` [PATCH 02/15] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig
2019-08-13 16:36 ` Paul Walmsley
2019-08-13 16:42 ` Christoph Hellwig
2019-08-13 16:51 ` Paul Walmsley
2019-08-13 19:44 ` Paul Walmsley
2019-08-13 15:47 ` [PATCH 03/15] riscv: refactor the IPI code Christoph Hellwig
2019-08-14 4:41 ` Paul Walmsley
2019-08-19 10:18 ` Christoph Hellwig
2019-09-01 8:03 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 04/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-08-13 15:47 ` [PATCH 05/15] riscv: improve the default power off implementation Christoph Hellwig
2019-08-13 15:47 ` [PATCH 06/15] riscv: provide a flat entry loader Christoph Hellwig
2019-08-13 15:47 ` [PATCH 07/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-08-13 15:47 ` [PATCH 08/15] riscv: provide native clint access for M-mode Christoph Hellwig
2019-08-13 16:29 ` Mark Rutland
2019-08-19 10:16 ` Christoph Hellwig
2019-08-27 23:37 ` Palmer Dabbelt
2019-08-28 6:11 ` Christoph Hellwig
2019-09-03 18:48 ` Palmer Dabbelt
2019-09-04 2:05 ` Alan Kao
2019-08-21 0:24 ` Atish Patra
2019-08-21 0:42 ` hch
2019-08-13 15:47 ` [PATCH 09/15] riscv: implement remote sfence.i natively " Christoph Hellwig
2019-08-20 21:04 ` Atish Patra [this message]
2019-08-13 15:47 ` [PATCH 10/15] riscv: poison SBI calls " Christoph Hellwig
2019-08-20 21:05 ` Atish Patra
2019-08-13 15:47 ` [PATCH 11/15] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig
2019-08-13 15:47 ` [PATCH 12/15] riscv: use the correct interrupt levels " Christoph Hellwig
2019-08-13 15:47 ` [PATCH 13/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-08-14 1:00 ` Alan Kao
2019-08-14 1:07 ` Alan Kao
2019-08-14 4:35 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 14/15] riscv: add nommu support Christoph Hellwig
2019-08-13 15:47 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-08-20 21:07 ` Atish Patra
2019-08-21 4:14 ` Troy Benjegerdes
2019-08-21 7:12 ` Christoph Hellwig
2019-08-21 17:31 ` Atish Patra
2019-08-21 17:54 ` Troy Benjegerdes
2019-08-21 23:02 ` Anup Patel
2019-08-21 23:32 ` Troy Benjegerdes
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