From: Paul Walmsley <paul.walmsley@sifive.com>
To: Christoph Hellwig <hch@lst.de>
Cc: Atish Patra <atish.patra@wdc.com>,
Damien Le Moal <damien.lemoal@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 02/15] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm
Date: Tue, 13 Aug 2019 09:51:56 -0700 (PDT) [thread overview]
Message-ID: <alpine.DEB.2.21.9999.1908130951250.30024@viisi.sifive.com> (raw)
In-Reply-To: <20190813164257.GA10019@lst.de>
On Tue, 13 Aug 2019, Christoph Hellwig wrote:
> On Tue, Aug 13, 2019 at 09:36:23AM -0700, Paul Walmsley wrote:
> > On Tue, 13 Aug 2019, Christoph Hellwig wrote:
> >
> > > Switch to our own constant for the satp register instead of using
> > > the old name from a legacy version of the privileged spec.
> > >
> > > Signed-off-by: Christoph Hellwig <hch@lst.de>
> > > Reviewed-by: Atish Patra <atish.patra@wdc.com>
> >
> > Didn't you want us to replace this with Bin Meng's patch?
> >
> > https://lore.kernel.org/linux-riscv/20190807151316.GB16432@infradead.org/
> >
> > If so, probably best just to drop this one and state a dependency.
>
> Either way is fine with me. But until you have a branch with
> either one applied I'm going to keep resending my patch, as random
> dependencies on uncommitted patches don't work.
If you're going to resend a patch, it's better to resend the other one
that you've explicitly endorsed in favor of your own.
- Paul
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next prev parent reply other threads:[~2019-08-13 16:52 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-13 15:47 RISC-V nommu support v3 Christoph Hellwig
2019-08-13 15:47 ` [PATCH 01/15] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-08-13 17:44 ` Paul Walmsley
2019-08-14 9:06 ` Marc Zyngier
2019-08-13 15:47 ` [PATCH 02/15] riscv: use CSR_SATP instead of the legacy sptbr name in switch_mm Christoph Hellwig
2019-08-13 16:36 ` Paul Walmsley
2019-08-13 16:42 ` Christoph Hellwig
2019-08-13 16:51 ` Paul Walmsley [this message]
2019-08-13 19:44 ` Paul Walmsley
2019-08-13 15:47 ` [PATCH 03/15] riscv: refactor the IPI code Christoph Hellwig
2019-08-14 4:41 ` Paul Walmsley
2019-08-19 10:18 ` Christoph Hellwig
2019-09-01 8:03 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 04/15] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-08-13 15:47 ` [PATCH 05/15] riscv: improve the default power off implementation Christoph Hellwig
2019-08-13 15:47 ` [PATCH 06/15] riscv: provide a flat entry loader Christoph Hellwig
2019-08-13 15:47 ` [PATCH 07/15] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-08-13 15:47 ` [PATCH 08/15] riscv: provide native clint access for M-mode Christoph Hellwig
2019-08-13 16:29 ` Mark Rutland
2019-08-19 10:16 ` Christoph Hellwig
2019-08-27 23:37 ` Palmer Dabbelt
2019-08-28 6:11 ` Christoph Hellwig
2019-09-03 18:48 ` Palmer Dabbelt
2019-09-04 2:05 ` Alan Kao
2019-08-21 0:24 ` Atish Patra
2019-08-21 0:42 ` hch
2019-08-13 15:47 ` [PATCH 09/15] riscv: implement remote sfence.i natively " Christoph Hellwig
2019-08-20 21:04 ` Atish Patra
2019-08-13 15:47 ` [PATCH 10/15] riscv: poison SBI calls " Christoph Hellwig
2019-08-20 21:05 ` Atish Patra
2019-08-13 15:47 ` [PATCH 11/15] riscv: don't allow selecting SBI-based drivers " Christoph Hellwig
2019-08-13 15:47 ` [PATCH 12/15] riscv: use the correct interrupt levels " Christoph Hellwig
2019-08-13 15:47 ` [PATCH 13/15] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-08-14 1:00 ` Alan Kao
2019-08-14 1:07 ` Alan Kao
2019-08-14 4:35 ` Christoph Hellwig
2019-08-13 15:47 ` [PATCH 14/15] riscv: add nommu support Christoph Hellwig
2019-08-13 15:47 ` [PATCH 15/15] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-08-20 21:07 ` Atish Patra
2019-08-21 4:14 ` Troy Benjegerdes
2019-08-21 7:12 ` Christoph Hellwig
2019-08-21 17:31 ` Atish Patra
2019-08-21 17:54 ` Troy Benjegerdes
2019-08-21 23:02 ` Anup Patel
2019-08-21 23:32 ` Troy Benjegerdes
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