From: Boris Brezillon <bbrezillon@kernel.org>
To: <Tudor.Ambarus@microchip.com>
Cc: <broonie@kernel.org>, <Nicolas.Ferre@microchip.com>,
<alexandre.belloni@bootlin.com>,
<Ludovic.Desroches@microchip.com>,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org
Subject: Re: [PATCH 1/9] spi: atmel-quadspi: optimize qspi init
Date: Wed, 30 Jan 2019 18:15:15 +0100 [thread overview]
Message-ID: <20190130181505.4f495d3a@bbrezillon> (raw)
In-Reply-To: <20190130150818.24902-2-tudor.ambarus@microchip.com>
On Wed, 30 Jan 2019 15:08:29 +0000
<Tudor.Ambarus@microchip.com> wrote:
> From: Tudor Ambarus <tudor.ambarus@microchip.com>
>
> Set the QSPI controller in Serial Memory Mode at init and not
> at each exec_op() call.
If you ever want to support regular SPI you'll have to put it back to
atmel_qspi_exec_op(), so I'm not sure this is a good move. Another
approach would be to cache the MR value to avoid doing a write access
on the bus when the value hasn't changed.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---
> drivers/spi/atmel-quadspi.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/spi/atmel-quadspi.c b/drivers/spi/atmel-quadspi.c
> index ddc712410812..f79b17792a11 100644
> --- a/drivers/spi/atmel-quadspi.c
> +++ b/drivers/spi/atmel-quadspi.c
> @@ -238,8 +238,6 @@ static int atmel_qspi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
> icr = QSPI_ICR_INST(op->cmd.opcode);
> ifr = QSPI_IFR_INSTEN;
>
> - qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> -
> mode = find_mode(op);
> if (mode < 0)
> return -ENOTSUPP;
> @@ -381,6 +379,9 @@ static int atmel_qspi_init(struct atmel_qspi *aq)
> /* Reset the QSPI controller */
> qspi_writel(aq, QSPI_CR, QSPI_CR_SWRST);
>
> + /* Set the QSPI controller in Serial Memory Mode */
> + qspi_writel(aq, QSPI_MR, QSPI_MR_SMM);
> +
> /* Enable the QSPI controller */
> qspi_writel(aq, QSPI_CR, QSPI_CR_QSPIEN);
>
next prev parent reply other threads:[~2019-01-30 17:15 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-30 15:08 [PATCH 0/9] spi: atmel-quadspi: introduce sam9x60 qspi contoller Tudor.Ambarus
2019-01-30 15:08 ` [PATCH 1/9] spi: atmel-quadspi: optimize qspi init Tudor.Ambarus
2019-01-30 17:15 ` Boris Brezillon [this message]
2019-01-31 10:42 ` Tudor.Ambarus
2019-01-30 15:08 ` [PATCH 2/9] spi: atmel-quadspi: order header files inclusion alphabetically Tudor.Ambarus
2019-01-30 17:16 ` Boris Brezillon
2019-01-30 15:08 ` [PATCH 3/9] spi: atmel-quadspi: fix naming scheme Tudor.Ambarus
2019-01-30 17:19 ` Boris Brezillon
2019-01-31 10:43 ` Tudor.Ambarus
2019-01-30 15:08 ` [PATCH 4/9] spi: atmel-quadspi: remove unnecessary cast Tudor.Ambarus
2019-01-30 17:20 ` Boris Brezillon
2019-01-30 15:08 ` [PATCH 5/9] spi: atmel-quadspi: return appropriate error code Tudor.Ambarus
2019-01-30 17:21 ` Boris Brezillon
2019-01-30 15:08 ` [PATCH 6/9] spi: atmel-quadspi: switch to SPDX license identifiers Tudor.Ambarus
2019-01-30 17:23 ` Boris Brezillon
2019-01-30 15:08 ` [PATCH 7/9] dt-bindings: spi: atmel-quadspi: update example to new clock binding Tudor.Ambarus
2019-01-30 17:25 ` Boris Brezillon
2019-01-30 15:08 ` [PATCH 8/9] dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60 Tudor.Ambarus
2019-01-30 17:30 ` Boris Brezillon
2019-01-31 10:45 ` Tudor.Ambarus
2019-01-30 15:08 ` [PATCH 9/9] spi: atmel-quadspi: add support for sam9x60 qspi controller Tudor.Ambarus
2019-01-30 17:43 ` Boris Brezillon
2019-01-31 10:46 ` Tudor.Ambarus
2019-01-31 11:55 ` Boris Brezillon
2019-01-31 12:40 ` Tudor.Ambarus
2019-01-31 13:12 ` Boris Brezillon
2019-01-31 12:01 ` Boris Brezillon
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