From: Roman Beranek <me@crly.cz>
To: Maxime Ripard <mripard@kernel.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Frank Oltmanns <frank@oltmanns.dev>,
Icenowy Zheng <icenowy@aosc.io>, Ondrej Jirman <megi@xff.cz>,
devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v4 1/4] clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux
Date: Fri, 5 May 2023 07:21:07 +0200 [thread overview]
Message-ID: <20230505052110.67514-2-me@crly.cz> (raw)
In-Reply-To: <20230505052110.67514-1-me@crly.cz>
TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X),
however MIPI DSI output only seems to work when PLL_MIPI is selected and
thus the choice must be hardcoded in.
Currently, this driver can't propagate rate change from N-K-M clocks
(such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating
in setting of the TCON0 data clock rate, limiting the precision with
which a target pixel clock can be matched.
For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock
can deviate up to 8% off target.
Signed-off-by: Roman Beranek <me@crly.cz>
---
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index 41519185600a..eb36f8f77d55 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -528,11 +528,18 @@ static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
+/*
+ * DSI output seems to work only when PLL_MIPI selected. Set it and prevent
+ * the mux from reparenting.
+ */
+#define SUN50I_A64_TCON0_CLK_REG 0x118
+
static const char * const tcon0_parents[] = { "pll-mipi", "pll-video0-2x" };
static const u8 tcon0_table[] = { 0, 2, };
static SUNXI_CCU_MUX_TABLE_WITH_GATE(tcon0_clk, "tcon0", tcon0_parents,
tcon0_table, 0x118, 24, 3, BIT(31),
- CLK_SET_RATE_PARENT);
+ CLK_SET_RATE_PARENT |
+ CLK_SET_RATE_NO_REPARENT);
static const char * const tcon1_parents[] = { "pll-video0", "pll-video1" };
static const u8 tcon1_table[] = { 0, 2, };
@@ -953,6 +960,11 @@ static int sun50i_a64_ccu_probe(struct platform_device *pdev)
writel(0x515, reg + SUN50I_A64_PLL_MIPI_REG);
+ /* Set PLL MIPI as parent for TCON0 */
+ val = readl(reg + SUN50I_A64_TCON0_CLK_REG);
+ val &= ~GENMASK(26, 24);
+ writel(val | (0 << 24), reg + SUN50I_A64_TCON0_CLK_REG);
+
ret = devm_sunxi_ccu_probe(&pdev->dev, reg, &sun50i_a64_ccu_desc);
if (ret)
return ret;
--
2.32.0 (Apple Git-132)
next prev parent reply other threads:[~2023-05-05 5:34 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-05 5:21 [PATCH v4 0/4] drm: sun4i: set proper TCON0 DCLK rate in DSI mode Roman Beranek
2023-05-05 5:21 ` Roman Beranek [this message]
2023-05-10 14:04 ` [PATCH v4 1/4] clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux Maxime Ripard
2023-05-10 18:43 ` Jernej Škrabec
2023-05-18 21:07 ` Jernej Škrabec
2023-05-05 5:21 ` [PATCH v4 2/4] ARM: dts: sunxi: rename tcon's clock output Roman Beranek
2023-05-10 14:04 ` Maxime Ripard
2023-05-10 18:44 ` Jernej Škrabec
2023-05-18 21:09 ` Jernej Škrabec
2023-05-05 5:21 ` [PATCH v4 3/4] drm: sun4i: rename sun4i_dotclock to sun4i_tcon_dclk Roman Beranek
2023-05-10 14:04 ` (subset) " Maxime Ripard
2023-05-05 5:21 ` [PATCH v4 4/4] drm: sun4i: calculate proper DCLK rate for DSI Roman Beranek
2023-05-10 14:04 ` (subset) " Maxime Ripard
2023-05-08 8:47 ` [PATCH v4 0/4] drm: sun4i: set proper TCON0 DCLK rate in DSI mode Frank Oltmanns
2023-05-09 11:04 ` Roman Beranek
2023-05-10 4:30 ` Frank Oltmanns
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