From: "Jernej Škrabec" <jernej.skrabec@gmail.com>
To: Maxime Ripard <mripard@kernel.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Chen-Yu Tsai <wens@csie.org>,
Samuel Holland <samuel@sholland.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Roman Beranek <me@crly.cz>
Cc: Frank Oltmanns <frank@oltmanns.dev>,
Icenowy Zheng <icenowy@aosc.io>, Ondrej Jirman <megi@xff.cz>,
devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 1/4] clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux
Date: Thu, 18 May 2023 23:07:59 +0200 [thread overview]
Message-ID: <4828357.31r3eYUQgx@jernej-laptop> (raw)
In-Reply-To: <20230505052110.67514-2-me@crly.cz>
Dne petek, 05. maj 2023 ob 07:21:07 CEST je Roman Beranek napisal(a):
> TCON0's source clock can be fed from either PLL_MIPI, or PLL_VIDEO0(2X),
> however MIPI DSI output only seems to work when PLL_MIPI is selected and
> thus the choice must be hardcoded in.
>
> Currently, this driver can't propagate rate change from N-K-M clocks
> (such as PLL_MIPI) upwards. This prevents PLL_VIDEO0 from participating
> in setting of the TCON0 data clock rate, limiting the precision with
> which a target pixel clock can be matched.
>
> For outputs with fixed TCON0 divider, that is DSI and LVDS, the dotclock
> can deviate up to 8% off target.
>
> Signed-off-by: Roman Beranek <me@crly.cz>
Applied, thanks!
Best regards,
Jernej
next prev parent reply other threads:[~2023-05-18 21:08 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-05 5:21 [PATCH v4 0/4] drm: sun4i: set proper TCON0 DCLK rate in DSI mode Roman Beranek
2023-05-05 5:21 ` [PATCH v4 1/4] clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux Roman Beranek
2023-05-10 14:04 ` Maxime Ripard
2023-05-10 18:43 ` Jernej Škrabec
2023-05-18 21:07 ` Jernej Škrabec [this message]
2023-05-05 5:21 ` [PATCH v4 2/4] ARM: dts: sunxi: rename tcon's clock output Roman Beranek
2023-05-10 14:04 ` Maxime Ripard
2023-05-10 18:44 ` Jernej Škrabec
2023-05-18 21:09 ` Jernej Škrabec
2023-05-05 5:21 ` [PATCH v4 3/4] drm: sun4i: rename sun4i_dotclock to sun4i_tcon_dclk Roman Beranek
2023-05-10 14:04 ` (subset) " Maxime Ripard
2023-05-05 5:21 ` [PATCH v4 4/4] drm: sun4i: calculate proper DCLK rate for DSI Roman Beranek
2023-05-10 14:04 ` (subset) " Maxime Ripard
2023-05-08 8:47 ` [PATCH v4 0/4] drm: sun4i: set proper TCON0 DCLK rate in DSI mode Frank Oltmanns
2023-05-09 11:04 ` Roman Beranek
2023-05-10 4:30 ` Frank Oltmanns
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