From: Roman Beranek <me@crly.cz>
To: Maxime Ripard <mripard@kernel.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Samuel Holland <samuel@sholland.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: Frank Oltmanns <frank@oltmanns.dev>,
Icenowy Zheng <icenowy@aosc.io>, Ondrej Jirman <megi@xff.cz>,
devicetree@vger.kernel.org, dri-devel@lists.freedesktop.org,
linux-arm-kernel@lists.infradead.org,
linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v4 4/4] drm: sun4i: calculate proper DCLK rate for DSI
Date: Fri, 5 May 2023 07:21:10 +0200 [thread overview]
Message-ID: <20230505052110.67514-5-me@crly.cz> (raw)
In-Reply-To: <20230505052110.67514-1-me@crly.cz>
In DSI mode, TCON0's data clock is required to run at 1/4 the per-lane
bit rate.
Signed-off-by: Roman Beranek <me@crly.cz>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 36 +++++++++++++++++-------------
1 file changed, 21 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index eec26b1faa4b..b263de7a8237 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -291,18 +291,6 @@ static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode,
return delay;
}
-static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon,
- const struct drm_display_mode *mode)
-{
- /* Configure the dot clock */
- clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
-
- /* Set the resolution */
- regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
- SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
- SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
-}
-
static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon,
const struct drm_connector *connector)
{
@@ -367,10 +355,18 @@ static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon,
u32 block_space, start_delay;
u32 tcon_div;
+ /*
+ * dclk is required to run at 1/4 the DSI per-lane bit rate.
+ */
tcon->dclk_min_div = SUN6I_DSI_TCON_DIV;
tcon->dclk_max_div = SUN6I_DSI_TCON_DIV;
+ clk_set_rate(tcon->dclk, mode->crtc_clock * 1000 * (bpp / lanes)
+ / SUN6I_DSI_TCON_DIV);
- sun4i_tcon0_mode_set_common(tcon, mode);
+ /* Set the resolution */
+ regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+ SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
+ SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
/* Set dithering if needed */
sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
@@ -438,7 +434,12 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
tcon->dclk_min_div = 7;
tcon->dclk_max_div = 7;
- sun4i_tcon0_mode_set_common(tcon, mode);
+ clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
+
+ /* Set the resolution */
+ regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+ SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
+ SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
/* Set dithering if needed */
sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder));
@@ -515,7 +516,12 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
tcon->dclk_min_div = tcon->quirks->dclk_min_div;
tcon->dclk_max_div = 127;
- sun4i_tcon0_mode_set_common(tcon, mode);
+ clk_set_rate(tcon->dclk, mode->crtc_clock * 1000);
+
+ /* Set the resolution */
+ regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG,
+ SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) |
+ SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay));
/* Set dithering if needed */
sun4i_tcon0_mode_set_dithering(tcon, connector);
--
2.32.0 (Apple Git-132)
next prev parent reply other threads:[~2023-05-05 5:21 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-05 5:21 [PATCH v4 0/4] drm: sun4i: set proper TCON0 DCLK rate in DSI mode Roman Beranek
2023-05-05 5:21 ` [PATCH v4 1/4] clk: sunxi-ng: a64: force select PLL_MIPI in TCON0 mux Roman Beranek
2023-05-10 14:04 ` Maxime Ripard
2023-05-10 18:43 ` Jernej Škrabec
2023-05-18 21:07 ` Jernej Škrabec
2023-05-05 5:21 ` [PATCH v4 2/4] ARM: dts: sunxi: rename tcon's clock output Roman Beranek
2023-05-10 14:04 ` Maxime Ripard
2023-05-10 18:44 ` Jernej Škrabec
2023-05-18 21:09 ` Jernej Škrabec
2023-05-05 5:21 ` [PATCH v4 3/4] drm: sun4i: rename sun4i_dotclock to sun4i_tcon_dclk Roman Beranek
2023-05-10 14:04 ` (subset) " Maxime Ripard
2023-05-05 5:21 ` Roman Beranek [this message]
2023-05-10 14:04 ` (subset) [PATCH v4 4/4] drm: sun4i: calculate proper DCLK rate for DSI Maxime Ripard
2023-05-08 8:47 ` [PATCH v4 0/4] drm: sun4i: set proper TCON0 DCLK rate in DSI mode Frank Oltmanns
2023-05-09 11:04 ` Roman Beranek
2023-05-10 4:30 ` Frank Oltmanns
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