linux-sunxi.lists.linux.dev archive mirror
 help / color / mirror / Atom feed
From: Emil Lenngren <emil.lenngren@gmail.com>
To: Pascal Roeleven <dev@pascalroeleven.nl>
Cc: "Roman Beranek" <roman.beranek@prusa3d.cz>,
	"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"Lee Jones" <lee.jones@linaro.org>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Chen-Yu Tsai" <wens@csie.org>,
	linux-pwm@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-sunxi@lists.linux.dev, linux-sunxi@googlegroups.com
Subject: Re: [PATCH 0/6] pwm: sun4i: only wait 2 cycles prior to disabling
Date: Mon, 31 May 2021 22:01:58 +0200	[thread overview]
Message-ID: <CAO1O6sdBX8D13tNKFAUynC2AcOX_Oo7tBEJi1vPPueSSQLfJOg@mail.gmail.com> (raw)
In-Reply-To: <e63e2b31c63bb9e227ed9ec04a8af54e@pascalroeleven.nl>

Den mån 31 maj 2021 kl 21:07 skrev Pascal Roeleven <dev@pascalroeleven.nl>:
>
> On 2021-05-31 06:46, Roman Beranek wrote:
> > As Emil Lenngren has previously shown [1], actually only 1-2 cycles of
> > the prescaler-divided clock are necessary to pass before the PWM turns
> > off, not a full period.
> >
> > To avoid having the PWM re-enabled from another thread while asleep,
> > ctrl_lock spinlock was converted to a mutex so that it can be released
> > only after the clock gate has finally been turned on.
> >
> > [1] https://linux-sunxi.org/PWM_Controller_Register_Guide
> >
> > Roman Beranek (6):
> >   pwm: sun4i: enable clk prior to getting its rate
> >   pwm: sun4i: disable EN bit prior to the delay
> >   pwm: sun4i: replace spinlock with a mutex
> >   pwm: sun4i: simplify calculation of the delay time
> >   pwm: sun4i: shorten the delay to 2 cycles
> >   pwm: sun4i: don't delay if the PWM is already off
> >
> >  drivers/pwm/pwm-sun4i.c | 56 +++++++++++++++++++----------------------
> >  1 file changed, 26 insertions(+), 30 deletions(-)
>
> Hi Roman,
>
> Thanks for your attempt to fix this.
>
> Unfortunately on my A10 device (Topwise A721), the controller still gets
> stuck in an unrecoverable state after disabling and re-enabling the PWM
> when it was already on (set in U-Boot), or when enabling it when it was
> off. In this state, any changes to the period register (using devmem)
> don't seem to have any effect. It seems to be stuck in the state it was
> before disabling. The only thing which still works is enabling and
> disabling.
>
> I can't reproduce this behavior manually so I'm not sure what is causing
> this.
>
> Regarding the amount of cycles of sleep; Using a prescaler of 72000 the
> PWM clock is 3 ms. Although timing tests using devmem seem unreliable
> (too much overhead?), in U-Boot I need to 'sleep' for at least 7 ms
> between the commands to make sure the output doesn't sometimes get stuck
> in the enabled state. So in my case it seems to be at least 3 cycles. I
> am not sure how reliable this method is. However even if I can get it
> stuck in the enabled state using a shorter time, it doesn't cause the
> behavior I mentioned before. I was always able to recover it manually.
> Increasing the number of cycles to sleep therefore also doesn't solve my
> problem. Until we can solve that I cannot confirm nor deny if 2 cycles
> is enough.
>
> Regards,
> Pascal

You could look at the devmem source code, and in C write a script that
writes to pwm register to disable the pwm, insert a usleep, then
disable the gating. This can be done for various sleep values, then
retrying with same sleep value multiple times. Assuming the overhead
is low (you can check the overhead by checking the current timestamp
at the beginning and at the end of the program, take the diff and then
subtract the sleep time), you will get one range where it never works,
one range where it works sometimes, and one range where it always
works. The uncertain range's condition for succeeding will depend on
when in the cycle you run the code.
Assuming we believe 3 cycles are enough on A10 and prescaler is 72000,
the thresholds for these ranges are 0-6 ms, 6-9 ms and 9+ ms.

About "being stuck", I'm not sure exactly what you mean but it's
expected that writes to the period register won't be visible (if you
read it after a write) when the clock gating is disabled. Three full
cycles (with the gating is on) must take place before the change is
visible (i.e. need to wait four cycles to be sure). At least on >=A13.
I documented that here:
https://linux-sunxi.org/PWM_Controller_Register_Guide.

/Emil

  reply	other threads:[~2021-05-31 20:02 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-31  4:46 Roman Beranek
2021-05-31  4:46 ` [PATCH 1/6] pwm: sun4i: enable clk prior to getting its rate Roman Beranek
2021-06-07  8:00   ` Uwe Kleine-König
2021-05-31  4:46 ` [PATCH 2/6] pwm: sun4i: disable EN bit prior to the delay Roman Beranek
2021-06-07  8:07   ` Uwe Kleine-König
2021-05-31  4:46 ` [PATCH 3/6] pwm: sun4i: replace spinlock with a mutex Roman Beranek
2021-05-31  4:46 ` [PATCH 4/6] pwm: sun4i: simplify calculation of the delay time Roman Beranek
2021-05-31  4:46 ` [PATCH 5/6] pwm: sun4i: shorten the delay to 2 cycles Roman Beranek
2021-05-31  4:46 ` [PATCH 6/6] pwm: sun4i: don't delay if the PWM is already off Roman Beranek
2021-06-10 13:41   ` Pascal Roeleven
2021-05-31 19:07 ` [PATCH 0/6] pwm: sun4i: only wait 2 cycles prior to disabling Pascal Roeleven
2021-05-31 20:01   ` Emil Lenngren [this message]
2021-05-31 20:20     ` Pascal Roeleven
2021-06-08 12:28   ` Pascal Roeleven

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=CAO1O6sdBX8D13tNKFAUynC2AcOX_Oo7tBEJi1vPPueSSQLfJOg@mail.gmail.com \
    --to=emil.lenngren@gmail.com \
    --cc=dev@pascalroeleven.nl \
    --cc=lee.jones@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-pwm@vger.kernel.org \
    --cc=linux-sunxi@googlegroups.com \
    --cc=linux-sunxi@lists.linux.dev \
    --cc=mripard@kernel.org \
    --cc=roman.beranek@prusa3d.cz \
    --cc=thierry.reding@gmail.com \
    --cc=u.kleine-koenig@pengutronix.de \
    --cc=wens@csie.org \
    --subject='Re: [PATCH 0/6] pwm: sun4i: only wait 2 cycles prior to disabling' \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).