From: Sumit Gupta <sumitg@nvidia.com>
To: <krzysztof.kozlowski@linaro.org>, <treding@nvidia.com>,
<jonathanh@nvidia.com>, <linux-kernel@vger.kernel.org>,
<linux-tegra@vger.kernel.org>
Cc: <bbasu@nvidia.com>, <talho@nvidia.com>, <sumitg@nvidia.com>,
Johnny Liu <johnliu@nvidia.com>
Subject: [Patch RESEND 2/4] memory: tegra: Add clients used by DRM in Tegra234
Date: Wed, 21 Jun 2023 19:13:58 +0530 [thread overview]
Message-ID: <20230621134400.23070-3-sumitg@nvidia.com> (raw)
In-Reply-To: <20230621134400.23070-1-sumitg@nvidia.com>
Add entries for VIC, NVDEC, NVENC, NVJPG memory controller
clients into the 'tegra_234_mc_clients' table.
Signed-off-by: Johnny Liu <johnliu@nvidia.com>
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
drivers/memory/tegra/tegra234.c | 120 ++++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c
index 3e44efe4541e..bc73be7fe143 100644
--- a/drivers/memory/tegra/tegra234.c
+++ b/drivers/memory/tegra/tegra234.c
@@ -29,6 +29,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0xac,
},
},
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVENCSRD,
+ .name = "nvencsrd",
+ .bpmp_id = TEGRA_ICC_BPMP_NVENC,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVENC,
+ .regs = {
+ .sid = {
+ .override = 0xe0,
+ .security = 0xe4,
+ },
+ },
}, {
.id = TEGRA234_MEMORY_CLIENT_PCIE6AR,
.name = "pcie6ar",
@@ -65,6 +77,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x154,
},
},
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVENCSWR,
+ .name = "nvencswr",
+ .bpmp_id = TEGRA_ICC_BPMP_NVENC,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVENC,
+ .regs = {
+ .sid = {
+ .override = 0x158,
+ .security = 0x15c,
+ },
+ },
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA0RDB,
.name = "dla0rdb",
@@ -357,6 +381,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x33c,
},
},
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_VICSRD,
+ .name = "vicsrd",
+ .bpmp_id = TEGRA_ICC_BPMP_VIC,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_VIC,
+ .regs = {
+ .sid = {
+ .override = 0x360,
+ .security = 0x364,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_VICSWR,
+ .name = "vicswr",
+ .bpmp_id = TEGRA_ICC_BPMP_VIC,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_VIC,
+ .regs = {
+ .sid = {
+ .override = 0x368,
+ .security = 0x36c,
+ },
+ },
}, {
.id = TEGRA234_MEMORY_CLIENT_DLA1RDB1,
.name = "dla0rdb1",
@@ -401,6 +449,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x38c,
},
},
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVDECSRD,
+ .name = "nvdecsrd",
+ .bpmp_id = TEGRA_ICC_BPMP_NVDEC,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVDEC,
+ .regs = {
+ .sid = {
+ .override = 0x3c0,
+ .security = 0x3c4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVDECSWR,
+ .name = "nvdecswr",
+ .bpmp_id = TEGRA_ICC_BPMP_NVDEC,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVDEC,
+ .regs = {
+ .sid = {
+ .override = 0x3c8,
+ .security = 0x3cc,
+ },
+ },
}, {
.id = TEGRA234_MEMORY_CLIENT_APER,
.name = "aper",
@@ -437,6 +509,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x3e4,
},
},
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVJPGSRD,
+ .name = "nvjpgsrd",
+ .bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVJPG,
+ .regs = {
+ .sid = {
+ .override = 0x3f0,
+ .security = 0x3f4,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVJPGSWR,
+ .name = "nvjpgswr",
+ .bpmp_id = TEGRA_ICC_BPMP_NVJPG_0,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVJPG,
+ .regs = {
+ .sid = {
+ .override = 0x3f8,
+ .security = 0x3fc,
+ },
+ },
}, {
.id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR,
.name = "nvdisplayr",
@@ -781,6 +877,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = {
.security = 0x77c,
},
},
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVJPG1SRD,
+ .name = "nvjpg1srd",
+ .bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVJPG1,
+ .regs = {
+ .sid = {
+ .override = 0x918,
+ .security = 0x91c,
+ },
+ },
+ }, {
+ .id = TEGRA234_MEMORY_CLIENT_NVJPG1SWR,
+ .name = "nvjpg1swr",
+ .bpmp_id = TEGRA_ICC_BPMP_NVJPG_1,
+ .type = TEGRA_ICC_NISO,
+ .sid = TEGRA234_SID_NVJPG1,
+ .regs = {
+ .sid = {
+ .override = 0x920,
+ .security = 0x924,
+ },
+ },
}, {
.id = TEGRA_ICC_MC_CPU_CLUSTER0,
.name = "sw_cluster0",
--
2.17.1
next prev parent reply other threads:[~2023-06-21 13:44 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-21 13:43 [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes Sumit Gupta
2023-06-21 13:43 ` [Patch RESEND 1/4] memory: tegra: sort tegra234_mc_clients table as per register offsets Sumit Gupta
2023-07-10 10:08 ` Krzysztof Kozlowski
2023-07-10 16:48 ` Sumit Gupta
2023-07-12 19:40 ` Krzysztof Kozlowski
2023-07-13 15:00 ` Thierry Reding
2023-06-21 13:43 ` Sumit Gupta [this message]
2023-07-13 15:01 ` [Patch RESEND 2/4] memory: tegra: Add clients used by DRM in Tegra234 Thierry Reding
2023-06-21 13:43 ` [Patch RESEND 3/4] memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported Sumit Gupta
2023-07-13 15:02 ` Thierry Reding
2023-06-21 13:44 ` [Patch RESEND 4/4] memory: tegra: make icc_set_bw return zero if BWMGR not supported Sumit Gupta
2023-07-13 15:03 ` Thierry Reding
2023-07-25 18:29 ` Jon Hunter
2023-07-25 20:11 ` Krzysztof Kozlowski
2023-07-14 4:10 ` [Patch RESEND 0/4] Tegra234 Memory Interconnect followup changes Krzysztof Kozlowski
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