From: Guenter Roeck <linux@roeck-us.net>
To: Sam Protsenko <semen.protsenko@linaro.org>
Cc: Wim Van Sebroeck <wim@linux-watchdog.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-samsung-soc@vger.kernel.org
Subject: Re: [PATCH v3 05/12] watchdog: s3c2410: Make reset disable register optional
Date: Wed, 17 Nov 2021 05:35:12 -0800 [thread overview]
Message-ID: <20211117133512.GE2435591@roeck-us.net> (raw)
In-Reply-To: <20211107202943.8859-6-semen.protsenko@linaro.org>
On Sun, Nov 07, 2021 at 10:29:36PM +0200, Sam Protsenko wrote:
> On new Exynos chips (e.g. Exynos850 and Exynos9) the
> AUTOMATIC_WDT_RESET_DISABLE register was removed, and its value can be
> thought of as "always 0x0". Add correspondig quirk bit, so that the
> driver can omit accessing it if it's not present.
>
> This commit doesn't bring any functional change to existing devices, but
> merely provides an infrastructure for upcoming chips support.
>
> Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> ---
> Changes in v3:
> - Aligned arguments with opening parentheses
> - Added R-b tag by Krzysztof Kozlowski
>
> Changes in v2:
> - Used quirks instead of callbacks for all added PMU registers
> - Used BIT() macro
> - Extracted splitting the s3c2410wdt_mask_and_disable_reset() function
> to separate patch
> - Extracted cleanup code to separate patch to minimize changes and
> ease the review and porting
>
> drivers/watchdog/s3c2410_wdt.c | 22 +++++++++++++---------
> 1 file changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 0845c05034a1..2cc4923a98a5 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -59,10 +59,12 @@
> #define QUIRK_HAS_PMU_CONFIG (1 << 0)
> #define QUIRK_HAS_RST_STAT (1 << 1)
> #define QUIRK_HAS_WTCLRINT_REG (1 << 2)
> +#define QUIRK_HAS_PMU_AUTO_DISABLE (1 << 3)
>
> /* These quirks require that we have a PMU register map */
> #define QUIRKS_HAVE_PMUREG (QUIRK_HAS_PMU_CONFIG | \
> - QUIRK_HAS_RST_STAT)
> + QUIRK_HAS_RST_STAT | \
> + QUIRK_HAS_PMU_AUTO_DISABLE)
>
> static bool nowayout = WATCHDOG_NOWAYOUT;
> static int tmr_margin;
> @@ -137,7 +139,7 @@ static const struct s3c2410_wdt_variant drv_data_exynos5250 = {
> .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> .rst_stat_bit = 20,
> .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
> - | QUIRK_HAS_WTCLRINT_REG,
> + | QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_AUTO_DISABLE,
> };
>
> static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
> @@ -147,7 +149,7 @@ static const struct s3c2410_wdt_variant drv_data_exynos5420 = {
> .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> .rst_stat_bit = 9,
> .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
> - | QUIRK_HAS_WTCLRINT_REG,
> + | QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_AUTO_DISABLE,
> };
>
> static const struct s3c2410_wdt_variant drv_data_exynos7 = {
> @@ -157,7 +159,7 @@ static const struct s3c2410_wdt_variant drv_data_exynos7 = {
> .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> .rst_stat_bit = 23, /* A57 WDTRESET */
> .quirks = QUIRK_HAS_PMU_CONFIG | QUIRK_HAS_RST_STAT \
> - | QUIRK_HAS_WTCLRINT_REG,
> + | QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_AUTO_DISABLE,
> };
>
> static const struct of_device_id s3c2410_wdt_match[] = {
> @@ -213,11 +215,13 @@ static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
> if (mask)
> val = mask_val;
>
> - ret = regmap_update_bits(wdt->pmureg,
> - wdt->drv_data->disable_reg,
> - mask_val, val);
> - if (ret < 0)
> - goto error;
> + if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) {
> + ret = regmap_update_bits(wdt->pmureg,
> + wdt->drv_data->disable_reg, mask_val,
> + val);
> + if (ret < 0)
> + goto error;
> + }
>
> ret = regmap_update_bits(wdt->pmureg,
> wdt->drv_data->mask_reset_reg,
> --
> 2.30.2
>
next prev parent reply other threads:[~2021-11-17 13:35 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-07 20:29 [PATCH v3 00/12] watchdog: s3c2410: Add Exynos850 support Sam Protsenko
2021-11-07 20:29 ` [PATCH v3 01/12] dt-bindings: watchdog: Require samsung,syscon-phandle for Exynos7 Sam Protsenko
2021-11-17 13:33 ` Guenter Roeck
2021-11-07 20:29 ` [PATCH v3 02/12] dt-bindings: watchdog: Document Exynos850 watchdog bindings Sam Protsenko
2021-11-08 13:08 ` Krzysztof Kozlowski
2021-11-12 22:43 ` Rob Herring
2021-11-17 13:34 ` Guenter Roeck
2021-11-07 20:29 ` [PATCH v3 03/12] watchdog: s3c2410: Fail probe if can't find valid timeout Sam Protsenko
2021-11-17 13:34 ` Guenter Roeck
2021-11-07 20:29 ` [PATCH v3 04/12] watchdog: s3c2410: Let kernel kick watchdog Sam Protsenko
2021-11-17 13:34 ` Guenter Roeck
2021-11-07 20:29 ` [PATCH v3 05/12] watchdog: s3c2410: Make reset disable register optional Sam Protsenko
2021-11-17 13:35 ` Guenter Roeck [this message]
2021-11-07 20:29 ` [PATCH v3 06/12] watchdog: s3c2410: Extract disable and mask code into separate functions Sam Protsenko
2021-11-17 13:35 ` Guenter Roeck
2021-11-07 20:29 ` [PATCH v3 07/12] watchdog: s3c2410: Implement a way to invert mask reg value Sam Protsenko
2021-11-17 13:35 ` Guenter Roeck
2021-11-07 20:29 ` [PATCH v3 08/12] watchdog: s3c2410: Add support for WDT counter enable register Sam Protsenko
2021-11-17 13:36 ` Guenter Roeck
2021-11-07 20:29 ` [PATCH v3 09/12] watchdog: s3c2410: Cleanup PMU related code Sam Protsenko
2021-11-17 13:36 ` Guenter Roeck
2021-11-07 20:29 ` [PATCH v3 10/12] watchdog: s3c2410: Support separate source clock Sam Protsenko
2021-11-08 13:24 ` Krzysztof Kozlowski
2021-11-17 13:37 ` Guenter Roeck
2021-11-07 20:29 ` [PATCH v3 11/12] watchdog: s3c2410: Remove superfluous err label Sam Protsenko
2021-11-17 13:37 ` Guenter Roeck
2021-11-07 20:29 ` [PATCH v3 12/12] watchdog: s3c2410: Add Exynos850 support Sam Protsenko
2021-11-08 13:25 ` Krzysztof Kozlowski
2021-11-17 13:37 ` Guenter Roeck
2021-11-20 20:29 ` Guenter Roeck
2021-11-21 16:25 ` Sam Protsenko
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211117133512.GE2435591@roeck-us.net \
--to=linux@roeck-us.net \
--cc=devicetree@vger.kernel.org \
--cc=krzysztof.kozlowski@canonical.com \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=linux-watchdog@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=semen.protsenko@linaro.org \
--cc=wim@linux-watchdog.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).