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From: "Luis R. Rodriguez" <lrodriguez@atheros.com>
To: linville@tuxdriver.com
Cc: linux-wireless@vger.kernel.org,
	Vasanthakumar Thiagarajan <vasanth@atheros.com>,
	"Luis R. Rodriguez" <lrodriguez@atheros.com>,
	Felix Fietkau <nbd@openwrt.org>
Subject: [PATCH v3 61/97] ath9k_hw: Abstract the routine which returns interrupt status
Date: Thu, 15 Apr 2010 17:39:06 -0400	[thread overview]
Message-ID: <1271367582-992-62-git-send-email-lrodriguez@atheros.com> (raw)
In-Reply-To: <1271367582-992-1-git-send-email-lrodriguez@atheros.com>

From: Vasanthakumar Thiagarajan <vasanth@atheros.com>

Also move interrupt related code to mac.c

Signed-off-by: Vasanthakumar Thiagarajan <vasanth@atheros.com>
Signed-off-by: Luis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: Felix Fietkau <nbd@openwrt.org>
---
 drivers/net/wireless/ath/ath9k/ar9003_mac.c |    6 +
 drivers/net/wireless/ath/ath9k/hw-ops.h     |    5 +
 drivers/net/wireless/ath/ath9k/hw.c         |  281 --------------------------
 drivers/net/wireless/ath/ath9k/hw.h         |    7 +-
 drivers/net/wireless/ath/ath9k/mac.c        |  290 +++++++++++++++++++++++++++
 drivers/net/wireless/ath/ath9k/mac.h        |    5 +
 drivers/net/wireless/ath/ath9k/reg.h        |    2 +
 7 files changed, 310 insertions(+), 286 deletions(-)

diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
index b229597..15f1b0f 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c
@@ -30,6 +30,11 @@ static void ar9003_hw_get_desc_link(void *ds, u32 **ds_link)
 	*ds_link = &((struct ar9003_txc *) ds)->link;
 }
 
+static bool ar9003_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
+{
+	return true;
+}
+
 void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
 {
 	struct ath_hw_ops *ops = ath9k_hw_ops(hw);
@@ -37,6 +42,7 @@ void ar9003_hw_attach_mac_ops(struct ath_hw *hw)
 	ops->rx_enable = ar9003_hw_rx_enable;
 	ops->set_desc_link = ar9003_hw_set_desc_link;
 	ops->get_desc_link = ar9003_hw_get_desc_link;
+	ops->get_isr = ar9003_hw_get_isr;
 }
 
 void ath9k_hw_set_rx_bufsize(struct ath_hw *ah, u16 buf_size)
diff --git a/drivers/net/wireless/ath/ath9k/hw-ops.h b/drivers/net/wireless/ath/ath9k/hw-ops.h
index 3848c0d..b777fd1 100644
--- a/drivers/net/wireless/ath/ath9k/hw-ops.h
+++ b/drivers/net/wireless/ath/ath9k/hw-ops.h
@@ -52,6 +52,11 @@ static inline bool ath9k_hw_calibrate(struct ath_hw *ah,
 	return ath9k_hw_ops(ah)->calibrate(ah, chan, rxchainmask, longcal);
 }
 
+static inline bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
+{
+	return ath9k_hw_ops(ah)->get_isr(ah, masked);
+}
+
 /* Private hardware call ops */
 
 /* PHY ops */
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 5d6df49..ab3a87b 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1781,287 +1781,6 @@ bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
 }
 EXPORT_SYMBOL(ath9k_hw_setpower);
 
-/**********************/
-/* Interrupt Handling */
-/**********************/
-
-bool ath9k_hw_intrpend(struct ath_hw *ah)
-{
-	u32 host_isr;
-
-	if (AR_SREV_9100(ah))
-		return true;
-
-	host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
-	if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
-		return true;
-
-	host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
-	if ((host_isr & AR_INTR_SYNC_DEFAULT)
-	    && (host_isr != AR_INTR_SPURIOUS))
-		return true;
-
-	return false;
-}
-EXPORT_SYMBOL(ath9k_hw_intrpend);
-
-bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
-{
-	u32 isr = 0;
-	u32 mask2 = 0;
-	struct ath9k_hw_capabilities *pCap = &ah->caps;
-	u32 sync_cause = 0;
-	bool fatal_int = false;
-	struct ath_common *common = ath9k_hw_common(ah);
-
-	if (!AR_SREV_9100(ah)) {
-		if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
-			if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
-			    == AR_RTC_STATUS_ON) {
-				isr = REG_READ(ah, AR_ISR);
-			}
-		}
-
-		sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
-			AR_INTR_SYNC_DEFAULT;
-
-		*masked = 0;
-
-		if (!isr && !sync_cause)
-			return false;
-	} else {
-		*masked = 0;
-		isr = REG_READ(ah, AR_ISR);
-	}
-
-	if (isr) {
-		if (isr & AR_ISR_BCNMISC) {
-			u32 isr2;
-			isr2 = REG_READ(ah, AR_ISR_S2);
-			if (isr2 & AR_ISR_S2_TIM)
-				mask2 |= ATH9K_INT_TIM;
-			if (isr2 & AR_ISR_S2_DTIM)
-				mask2 |= ATH9K_INT_DTIM;
-			if (isr2 & AR_ISR_S2_DTIMSYNC)
-				mask2 |= ATH9K_INT_DTIMSYNC;
-			if (isr2 & (AR_ISR_S2_CABEND))
-				mask2 |= ATH9K_INT_CABEND;
-			if (isr2 & AR_ISR_S2_GTT)
-				mask2 |= ATH9K_INT_GTT;
-			if (isr2 & AR_ISR_S2_CST)
-				mask2 |= ATH9K_INT_CST;
-			if (isr2 & AR_ISR_S2_TSFOOR)
-				mask2 |= ATH9K_INT_TSFOOR;
-		}
-
-		isr = REG_READ(ah, AR_ISR_RAC);
-		if (isr == 0xffffffff) {
-			*masked = 0;
-			return false;
-		}
-
-		*masked = isr & ATH9K_INT_COMMON;
-
-		if (ah->config.rx_intr_mitigation) {
-			if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
-				*masked |= ATH9K_INT_RX;
-		}
-
-		if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
-			*masked |= ATH9K_INT_RX;
-		if (isr &
-		    (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
-		     AR_ISR_TXEOL)) {
-			u32 s0_s, s1_s;
-
-			*masked |= ATH9K_INT_TX;
-
-			s0_s = REG_READ(ah, AR_ISR_S0_S);
-			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
-			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
-
-			s1_s = REG_READ(ah, AR_ISR_S1_S);
-			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
-			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
-		}
-
-		if (isr & AR_ISR_RXORN) {
-			ath_print(common, ATH_DBG_INTERRUPT,
-				  "receive FIFO overrun interrupt\n");
-		}
-
-		if (!AR_SREV_9100(ah)) {
-			if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
-				u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
-				if (isr5 & AR_ISR_S5_TIM_TIMER)
-					*masked |= ATH9K_INT_TIM_TIMER;
-			}
-		}
-
-		*masked |= mask2;
-	}
-
-	if (AR_SREV_9100(ah))
-		return true;
-
-	if (isr & AR_ISR_GENTMR) {
-		u32 s5_s;
-
-		s5_s = REG_READ(ah, AR_ISR_S5_S);
-		if (isr & AR_ISR_GENTMR) {
-			ah->intr_gen_timer_trigger =
-				MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
-
-			ah->intr_gen_timer_thresh =
-				MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
-
-			if (ah->intr_gen_timer_trigger)
-				*masked |= ATH9K_INT_GENTIMER;
-
-		}
-	}
-
-	if (sync_cause) {
-		fatal_int =
-			(sync_cause &
-			 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
-			? true : false;
-
-		if (fatal_int) {
-			if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
-				ath_print(common, ATH_DBG_ANY,
-					  "received PCI FATAL interrupt\n");
-			}
-			if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
-				ath_print(common, ATH_DBG_ANY,
-					  "received PCI PERR interrupt\n");
-			}
-			*masked |= ATH9K_INT_FATAL;
-		}
-		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
-			ath_print(common, ATH_DBG_INTERRUPT,
-				  "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
-			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
-			REG_WRITE(ah, AR_RC, 0);
-			*masked |= ATH9K_INT_FATAL;
-		}
-		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
-			ath_print(common, ATH_DBG_INTERRUPT,
-				  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
-		}
-
-		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
-		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
-	}
-
-	return true;
-}
-EXPORT_SYMBOL(ath9k_hw_getisr);
-
-enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
-{
-	enum ath9k_int omask = ah->imask;
-	u32 mask, mask2;
-	struct ath9k_hw_capabilities *pCap = &ah->caps;
-	struct ath_common *common = ath9k_hw_common(ah);
-
-	ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
-
-	if (omask & ATH9K_INT_GLOBAL) {
-		ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
-		REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
-		(void) REG_READ(ah, AR_IER);
-		if (!AR_SREV_9100(ah)) {
-			REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
-			(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
-
-			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
-			(void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
-		}
-	}
-
-	mask = ints & ATH9K_INT_COMMON;
-	mask2 = 0;
-
-	if (ints & ATH9K_INT_TX) {
-		if (ah->txok_interrupt_mask)
-			mask |= AR_IMR_TXOK;
-		if (ah->txdesc_interrupt_mask)
-			mask |= AR_IMR_TXDESC;
-		if (ah->txerr_interrupt_mask)
-			mask |= AR_IMR_TXERR;
-		if (ah->txeol_interrupt_mask)
-			mask |= AR_IMR_TXEOL;
-	}
-	if (ints & ATH9K_INT_RX) {
-		mask |= AR_IMR_RXERR;
-		if (ah->config.rx_intr_mitigation)
-			mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
-		else
-			mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
-		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
-			mask |= AR_IMR_GENTMR;
-	}
-
-	if (ints & (ATH9K_INT_BMISC)) {
-		mask |= AR_IMR_BCNMISC;
-		if (ints & ATH9K_INT_TIM)
-			mask2 |= AR_IMR_S2_TIM;
-		if (ints & ATH9K_INT_DTIM)
-			mask2 |= AR_IMR_S2_DTIM;
-		if (ints & ATH9K_INT_DTIMSYNC)
-			mask2 |= AR_IMR_S2_DTIMSYNC;
-		if (ints & ATH9K_INT_CABEND)
-			mask2 |= AR_IMR_S2_CABEND;
-		if (ints & ATH9K_INT_TSFOOR)
-			mask2 |= AR_IMR_S2_TSFOOR;
-	}
-
-	if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
-		mask |= AR_IMR_BCNMISC;
-		if (ints & ATH9K_INT_GTT)
-			mask2 |= AR_IMR_S2_GTT;
-		if (ints & ATH9K_INT_CST)
-			mask2 |= AR_IMR_S2_CST;
-	}
-
-	ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
-	REG_WRITE(ah, AR_IMR, mask);
-	ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
-			   AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
-			   AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
-	ah->imrs2_reg |= mask2;
-	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
-
-	if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
-		if (ints & ATH9K_INT_TIM_TIMER)
-			REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
-		else
-			REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
-	}
-
-	if (ints & ATH9K_INT_GLOBAL) {
-		ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
-		REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
-		if (!AR_SREV_9100(ah)) {
-			REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
-				  AR_INTR_MAC_IRQ);
-			REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
-
-
-			REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
-				  AR_INTR_SYNC_DEFAULT);
-			REG_WRITE(ah, AR_INTR_SYNC_MASK,
-				  AR_INTR_SYNC_DEFAULT);
-		}
-		ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
-			  REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
-	}
-
-	return omask;
-}
-EXPORT_SYMBOL(ath9k_hw_set_interrupts);
-
 /*******************/
 /* Beacon Handling */
 /*******************/
diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h
index b27e76b..7a32733 100644
--- a/drivers/net/wireless/ath/ath9k/hw.h
+++ b/drivers/net/wireless/ath/ath9k/hw.h
@@ -227,6 +227,7 @@ struct ath9k_ops_config {
 	u32 enable_ani;
 	int serialize_regmode;
 	bool rx_intr_mitigation;
+	bool tx_intr_mitigation;
 #define SPUR_DISABLE        	0
 #define SPUR_ENABLE_IOCTL   	1
 #define SPUR_ENABLE_EEPROM  	2
@@ -549,6 +550,7 @@ struct ath_hw_ops {
 			  struct ath9k_channel *chan,
 			  u8 rxchainmask,
 			  bool longcal);
+	bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
 };
 
 struct ath_hw {
@@ -810,11 +812,6 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
 
 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
 
-/* Interrupt Handling */
-bool ath9k_hw_intrpend(struct ath_hw *ah);
-bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked);
-enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints);
-
 /* Generic hw timer primitives */
 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
 					  void (*trigger)(void *),
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index a8dab23..4a36ec5 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -31,6 +31,158 @@ static void ar9002_hw_get_desc_link(void *ds, u32 **ds_link)
 	*ds_link = &((struct ath_desc *)ds)->ds_link;
 }
 
+static bool ar9002_hw_get_isr(struct ath_hw *ah, enum ath9k_int *masked)
+{
+	u32 isr = 0;
+	u32 mask2 = 0;
+	struct ath9k_hw_capabilities *pCap = &ah->caps;
+	u32 sync_cause = 0;
+	bool fatal_int = false;
+	struct ath_common *common = ath9k_hw_common(ah);
+
+	if (!AR_SREV_9100(ah)) {
+		if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
+			if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
+			    == AR_RTC_STATUS_ON) {
+				isr = REG_READ(ah, AR_ISR);
+			}
+		}
+
+		sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
+			AR_INTR_SYNC_DEFAULT;
+
+		*masked = 0;
+
+		if (!isr && !sync_cause)
+			return false;
+	} else {
+		*masked = 0;
+		isr = REG_READ(ah, AR_ISR);
+	}
+
+	if (isr) {
+		if (isr & AR_ISR_BCNMISC) {
+			u32 isr2;
+			isr2 = REG_READ(ah, AR_ISR_S2);
+			if (isr2 & AR_ISR_S2_TIM)
+				mask2 |= ATH9K_INT_TIM;
+			if (isr2 & AR_ISR_S2_DTIM)
+				mask2 |= ATH9K_INT_DTIM;
+			if (isr2 & AR_ISR_S2_DTIMSYNC)
+				mask2 |= ATH9K_INT_DTIMSYNC;
+			if (isr2 & (AR_ISR_S2_CABEND))
+				mask2 |= ATH9K_INT_CABEND;
+			if (isr2 & AR_ISR_S2_GTT)
+				mask2 |= ATH9K_INT_GTT;
+			if (isr2 & AR_ISR_S2_CST)
+				mask2 |= ATH9K_INT_CST;
+			if (isr2 & AR_ISR_S2_TSFOOR)
+				mask2 |= ATH9K_INT_TSFOOR;
+		}
+
+		isr = REG_READ(ah, AR_ISR_RAC);
+		if (isr == 0xffffffff) {
+			*masked = 0;
+			return false;
+		}
+
+		*masked = isr & ATH9K_INT_COMMON;
+
+		if (ah->config.rx_intr_mitigation) {
+			if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
+				*masked |= ATH9K_INT_RX;
+		}
+
+		if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
+			*masked |= ATH9K_INT_RX;
+		if (isr &
+		    (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
+		     AR_ISR_TXEOL)) {
+			u32 s0_s, s1_s;
+
+			*masked |= ATH9K_INT_TX;
+
+			s0_s = REG_READ(ah, AR_ISR_S0_S);
+			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
+			ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
+
+			s1_s = REG_READ(ah, AR_ISR_S1_S);
+			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
+			ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
+		}
+
+		if (isr & AR_ISR_RXORN) {
+			ath_print(common, ATH_DBG_INTERRUPT,
+				  "receive FIFO overrun interrupt\n");
+		}
+
+		if (!AR_SREV_9100(ah)) {
+			if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
+				u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
+				if (isr5 & AR_ISR_S5_TIM_TIMER)
+					*masked |= ATH9K_INT_TIM_TIMER;
+			}
+		}
+
+		*masked |= mask2;
+	}
+
+	if (AR_SREV_9100(ah))
+		return true;
+
+	if (isr & AR_ISR_GENTMR) {
+		u32 s5_s;
+
+		s5_s = REG_READ(ah, AR_ISR_S5_S);
+		if (isr & AR_ISR_GENTMR) {
+			ah->intr_gen_timer_trigger =
+				MS(s5_s, AR_ISR_S5_GENTIMER_TRIG);
+
+			ah->intr_gen_timer_thresh =
+				MS(s5_s, AR_ISR_S5_GENTIMER_THRESH);
+
+			if (ah->intr_gen_timer_trigger)
+				*masked |= ATH9K_INT_GENTIMER;
+
+		}
+	}
+
+	if (sync_cause) {
+		fatal_int =
+			(sync_cause &
+			 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
+			? true : false;
+
+		if (fatal_int) {
+			if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
+				ath_print(common, ATH_DBG_ANY,
+					  "received PCI FATAL interrupt\n");
+			}
+			if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
+				ath_print(common, ATH_DBG_ANY,
+					  "received PCI PERR interrupt\n");
+			}
+			*masked |= ATH9K_INT_FATAL;
+		}
+		if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
+			ath_print(common, ATH_DBG_INTERRUPT,
+				  "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
+			REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
+			REG_WRITE(ah, AR_RC, 0);
+			*masked |= ATH9K_INT_FATAL;
+		}
+		if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
+			ath_print(common, ATH_DBG_INTERRUPT,
+				  "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
+		}
+
+		REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
+		(void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
+	}
+
+	return true;
+}
+
 void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
 {
 	struct ath_hw_ops *ops = ath9k_hw_ops(ah);
@@ -38,6 +190,7 @@ void ar9002_hw_attach_mac_ops(struct ath_hw *ah)
 	ops->rx_enable = ar9002_hw_rx_enable;
 	ops->set_desc_link = ar9002_hw_set_desc_link;
 	ops->get_desc_link = ar9002_hw_get_desc_link;
+	ops->get_isr = ar9002_hw_get_isr;
 }
 
 static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
@@ -1089,3 +1242,140 @@ int ath9k_hw_beaconq_setup(struct ath_hw *ah)
 	return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
 }
 EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
+
+bool ath9k_hw_intrpend(struct ath_hw *ah)
+{
+	u32 host_isr;
+
+	if (AR_SREV_9100(ah))
+		return true;
+
+	host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
+	if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
+		return true;
+
+	host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
+	if ((host_isr & AR_INTR_SYNC_DEFAULT)
+	    && (host_isr != AR_INTR_SPURIOUS))
+		return true;
+
+	return false;
+}
+EXPORT_SYMBOL(ath9k_hw_intrpend);
+
+enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
+					      enum ath9k_int ints)
+{
+	enum ath9k_int omask = ah->imask;
+	u32 mask, mask2;
+	struct ath9k_hw_capabilities *pCap = &ah->caps;
+	struct ath_common *common = ath9k_hw_common(ah);
+
+	ath_print(common, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
+
+	if (omask & ATH9K_INT_GLOBAL) {
+		ath_print(common, ATH_DBG_INTERRUPT, "disable IER\n");
+		REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
+		(void) REG_READ(ah, AR_IER);
+		if (!AR_SREV_9100(ah)) {
+			REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
+			(void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
+
+			REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
+			(void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
+		}
+	}
+
+	/* TODO: global int Ref count */
+	mask = ints & ATH9K_INT_COMMON;
+	mask2 = 0;
+
+	if (ints & ATH9K_INT_TX) {
+		if (ah->config.tx_intr_mitigation)
+			mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
+		if (ah->txok_interrupt_mask)
+			mask |= AR_IMR_TXOK;
+		if (ah->txdesc_interrupt_mask)
+			mask |= AR_IMR_TXDESC;
+		if (ah->txerr_interrupt_mask)
+			mask |= AR_IMR_TXERR;
+		if (ah->txeol_interrupt_mask)
+			mask |= AR_IMR_TXEOL;
+	}
+	if (ints & ATH9K_INT_RX) {
+		if (AR_SREV_9300_20_OR_LATER(ah)) {
+			mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
+			if (ah->config.rx_intr_mitigation) {
+				mask &= ~AR_IMR_RXOK_LP;
+				mask |=  AR_IMR_RXMINTR | AR_IMR_RXINTM;
+			} else {
+				mask |= AR_IMR_RXOK_LP;
+			}
+		} else {
+			if (ah->config.rx_intr_mitigation)
+				mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
+			else
+				mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
+		}
+		if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
+			mask |= AR_IMR_GENTMR;
+	}
+
+	if (ints & (ATH9K_INT_BMISC)) {
+		mask |= AR_IMR_BCNMISC;
+		if (ints & ATH9K_INT_TIM)
+			mask2 |= AR_IMR_S2_TIM;
+		if (ints & ATH9K_INT_DTIM)
+			mask2 |= AR_IMR_S2_DTIM;
+		if (ints & ATH9K_INT_DTIMSYNC)
+			mask2 |= AR_IMR_S2_DTIMSYNC;
+		if (ints & ATH9K_INT_CABEND)
+			mask2 |= AR_IMR_S2_CABEND;
+		if (ints & ATH9K_INT_TSFOOR)
+			mask2 |= AR_IMR_S2_TSFOOR;
+	}
+
+	if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
+		mask |= AR_IMR_BCNMISC;
+		if (ints & ATH9K_INT_GTT)
+			mask2 |= AR_IMR_S2_GTT;
+		if (ints & ATH9K_INT_CST)
+			mask2 |= AR_IMR_S2_CST;
+	}
+
+	ath_print(common, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
+	REG_WRITE(ah, AR_IMR, mask);
+	ah->imrs2_reg &= ~(AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC |
+			   AR_IMR_S2_CABEND | AR_IMR_S2_CABTO |
+			   AR_IMR_S2_TSFOOR | AR_IMR_S2_GTT | AR_IMR_S2_CST);
+	ah->imrs2_reg |= mask2;
+	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
+
+	if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
+		if (ints & ATH9K_INT_TIM_TIMER)
+			REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
+		else
+			REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
+	}
+
+	if (ints & ATH9K_INT_GLOBAL) {
+		ath_print(common, ATH_DBG_INTERRUPT, "enable IER\n");
+		REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
+		if (!AR_SREV_9100(ah)) {
+			REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
+				  AR_INTR_MAC_IRQ);
+			REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
+
+
+			REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
+				  AR_INTR_SYNC_DEFAULT);
+			REG_WRITE(ah, AR_INTR_SYNC_MASK,
+				  AR_INTR_SYNC_DEFAULT);
+		}
+		ath_print(common, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
+			  REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
+	}
+
+	return omask;
+}
+EXPORT_SYMBOL(ath9k_hw_set_interrupts);
diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h
index 99f81eb..7c0d754 100644
--- a/drivers/net/wireless/ath/ath9k/mac.h
+++ b/drivers/net/wireless/ath/ath9k/mac.h
@@ -736,6 +736,11 @@ void ath9k_hw_stoppcurecv(struct ath_hw *ah);
 bool ath9k_hw_stopdmarecv(struct ath_hw *ah);
 int ath9k_hw_beaconq_setup(struct ath_hw *ah);
 
+/* Interrupt Handling */
+bool ath9k_hw_intrpend(struct ath_hw *ah);
+enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah,
+				       enum ath9k_int ints);
+
 void ar9002_hw_attach_mac_ops(struct ath_hw *ah);
 
 #endif /* MAC_H */
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 96b2cfe..7f85633 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -253,6 +253,8 @@
 #define AR_IMR               0x00a0
 #define AR_IMR_RXOK          0x00000001
 #define AR_IMR_RXDESC        0x00000002
+#define AR_IMR_RXOK_HP	     0x00000001
+#define AR_IMR_RXOK_LP	     0x00000002
 #define AR_IMR_RXERR         0x00000004
 #define AR_IMR_RXNOPKT       0x00000008
 #define AR_IMR_RXEOL         0x00000010
-- 
1.6.3.3


  parent reply	other threads:[~2010-04-15 21:39 UTC|newest]

Thread overview: 103+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-04-15 21:38 [PATCH v3 00/97] ath9k: add AR9003 support Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 01/97] ath9k_hw: start building an abstraction layer for hardware routines Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 02/97] ath9k_hw: add silicon revision macros for AR9300 Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 03/97] ath9k_hw: add a macro for abstracting generic timer access Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 04/97] ath9k_hw: fix a missing hex prefix for a register mask Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 05/97] ath9k_hw: add simple register abstraction for some AR9300 registers Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 06/97] ath9k_hw: add support for GPIO differences on AR9003 Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 07/97] ath9k_hw: AR9003 does not have AR_RC_AHB skip its setting Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 08/97] ath9k_hw: remove wrapper ath9k_hw_write_regs() Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 09/97] ath9k_hw: Move some RF ops to the private callbacks Luis R. Rodriguez
2010-04-16 19:43   ` John W. Linville
2010-04-16 19:56     ` Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 10/97] ath9k_hw: skip PLL initialization on AR9003 on Power-On-Reset Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 11/97] ath9k_hw: add some comments for ath9k_set_power_network_sleep() Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 12/97] ath9k_hw: add a private callback for PLL control computation Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 13/97] ath9k_hw: Add the PCI IDs for AR9300 and fill up the pci_id_tables Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 14/97] ath9k_hw: Add AR9003 PHY support Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 15/97] ath9k_hw: move init config and default after chip is up Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 16/97] ath9k_hw: add the AR9003 ar9003_hw_macversion_supported() Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 17/97] ath9k_hw: disable ANI for AR9003 Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 18/97] ath9k: disable the MIB interrupt if ANI is disabled Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 19/97] ath9k_hw: Add hw cap flag for EDMA for the AR9003 family Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 20/97] ath9k_hw: Fill few hw cap for edma Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 21/97] ath9k_hw: Add abstraction for rx enable Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 22/97] ath9k_hw: Fill rx_enable() for the AR9003 hardware family Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 23/97] ath9k_hw: Add few routines for rx edma support Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 24/97] ath9k_hw: update the chip tests for AR9003 Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 25/97] ath9k_hw: prevent reset control register zeroing on AR9003 reset Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 26/97] ath9k_hw: Add AR9003 PHY register definitions Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 27/97] ath9k_hw: add common channel select helpers for ar900[23] Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 28/97] ath9k_hw: Set the channel on AR9003 Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 29/97] ath9k_hw: Implement PLL control " Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 30/97] ath9k_hw: Implement spur mitigation " Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 31/97] ath9k_hw: split initvals.h by hardware family Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 32/97] ath9k_hw: add initvals for the AR9003 " Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 33/97] ath9k_hw: add helpers for processing the AR9003 INI Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 34/97] ath9k_hw: Split off ANI control to the PHY ops Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 35/97] ath9k_hw: add all the AR9003 PHY callbacks Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 36/97] ath9k_hw: Define tx control struct for AR9003 Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 37/97] ath9k_hw: Move code which populates ds_data to ath9k_hw Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 38/97] ath9k_hw: Add abstraction to set/get link pointer Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 39/97] ath9k: Use abstraction to get " Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 40/97] ath9k: Use memcpy in ath_clone_txbuf() Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 41/97] ath9k: Remove ATH9K_TX_SW_ABORTED and introduce a bool for this purpose Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 42/97] ath9k: Make bf_desc of ath_buf opaque Luis R. Rodriguez
2010-04-16 22:00   ` Pavel Roskin
2010-04-16 22:09     ` Felix Fietkau
2010-04-19 15:53       ` Pavel Roskin
2010-04-15 21:38 ` [PATCH v3 43/97] ath9k: Add Rx EDMA support Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 44/97] ath9k_hw: Split out the function for reading the noise floor Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 45/97] ath9k_hw: the eep_map is used only for AR9280 PCI card ini fixup Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 46/97] ath9k_hw: add a helper for Power Amplifier calibration for AR9002 Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 47/97] ath9k_hw: add a helper for the OLC tem compensation " Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 48/97] ath9k_hw: rename PA calib for AR9287 Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 49/97] ath9k_hw: shift code for AR9280 OLC temp comp Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 50/97] ath9k_hw: move the AR9280 OLC temp comp to its own helper Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 51/97] ath9k_hw: simplify OLC temp compensation for AR9002 Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 52/97] ath9k_hw: rename the PA calib routines to match their families Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 53/97] ath9k_hw: rename getNoiseFloorThresh() to ath9k_hw_loadnf() Luis R. Rodriguez
2010-04-15 21:38 ` [PATCH v3 54/97] ath9k_hw: move the cal AR9100 calibration settings Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 55/97] ath9k_hw: split calib code by hardware families Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 56/97] ath9k_hw: add the AR9003 ar9003_hw_init_cal callback Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 57/97] ath9k_hw: add the config_pci_powersave AR9003 callback Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 58/97] ath9k_hw: split the generic hardware code by hardware family Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 59/97] ath9k_hw: move the cck channel 14 INI to the AR9002 hw code Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 60/97] ath9k_hw: move TX/RX gain INI stuff to its own hardware family code Luis R. Rodriguez
2010-04-15 21:39 ` Luis R. Rodriguez [this message]
2010-04-15 21:39 ` [PATCH v3 62/97] ath9k_hw: Initialize interrupt mask for AR9003 Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 63/97] ath9k_hw: abstract the AR_PHY_AGC_CONTROL register access Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 64/97] ath9k_hw: abstract loading noisefloor Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 65/97] ath9k_hw: fill in the callbacks for calibration for AR9003 Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 66/97] ath9k_hw: complete AR9003 calibration Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 67/97] ath9k_hw: rename eep_AR9287_ops to eep_ar9287_ops Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 68/97] ath9k_hw: restore mac address reading logic Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 69/97] ath9k_hw: Implement AR9003 eeprom callbacks Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 70/97] ath9k_hw: add OFDM spur mitigation for AR9003 Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 71/97] ath9k_hw: Fill get_isr() " Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 72/97] ath9k_hw: move AR9280 PCI EEPROM fix to eeprom_def.c Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 73/97] ath9k_hw: move the RF claim stuff to AR9002 hardware family Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 74/97] ath9k_hw: Configure Tx interrupt mitigation timer Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 75/97] ath9k_hw: add the AR9300 SREV hw name print Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 76/97] ath9k_hw: add TX/RX gain register initialization for AR9003 Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 77/97] ath9k_hw: Update ath9k_hw_set_dma for AR9300 Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 78/97] ath9k_hw: skip asynch fifo enablement to AR9003 Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 79/97] ath9k_hw: skip WEP aggregation enable code for AR9003 Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 80/97] ath9k: Load SW filtered NF values and start NF cal during full reset " Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 81/97] ath9k_hw: Define abstraction for tx desc access Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 82/97] ath9k_hw: Add function to configure tx status ring buffer Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 83/97] ath9k_hw: move AR9002 mac ops to its own file Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 84/97] ath9k_hw: Fill descriptor abstrations for AR9003 Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 85/97] ath9k: add RXLP and RXHP to debugfs counters Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 86/97] ath9k_hw: enable CRC check of descriptors for AR9003 Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 87/97] ath9k_hw: set cwmin and cwmax to 0 for for AR9003 upon txq reset Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 88/97] ath9k: Setup appropriate tx desc for regular dma and edma Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 89/97] ath9k: Initialize and configure tx status for EDMA Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 90/97] ath9k_hw: Compute pointer checksum over the link descriptor Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 91/97] ath9k: Add Tx EDMA support Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 92/97] mac80211: add LDPC control flag Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 93/97] ath9k_hw: add LDPC support for AR9003 Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 94/97] ath9k: add LDPC support Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 95/97] ath9k: Enable TXOK and TXERR interrupts for TX EDMA Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 96/97] ath9k_hw: Abort rx if hw is not coming out of full sleep in reset Luis R. Rodriguez
2010-04-15 21:39 ` [PATCH v3 97/97] ath9k_hw: add the PCI ID for the first AR9300 device Luis R. Rodriguez

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