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From: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
To: Paul Mackerras <paulus@ozlabs.org>
Cc: mikey@neuling.org, maddy@linux.vnet.ibm.com,
	linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH v2 02/10] KVM: PPC: Book3S HV: Save/restore new PMU registers
Date: Thu, 2 Jul 2020 11:52:37 +0530
Message-ID: <9692404F-A567-479B-BF9B-3624E71639FB@linux.vnet.ibm.com> (raw)
In-Reply-To: <20200701111158.GA694641@thinks.paulus.ozlabs.org>


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> On 01-Jul-2020, at 4:41 PM, Paul Mackerras <paulus@ozlabs.org> wrote:
> 
> On Wed, Jul 01, 2020 at 05:20:54AM -0400, Athira Rajeev wrote:
>> PowerISA v3.1 has added new performance monitoring unit (PMU)
>> special purpose registers (SPRs). They are
>> 
>> Monitor Mode Control Register 3 (MMCR3)
>> Sampled Instruction Event Register A (SIER2)
>> Sampled Instruction Event Register B (SIER3)
>> 
>> Patch addes support to save/restore these new
>> SPRs while entering/exiting guest.
> 
> This mostly looks reasonable, at a quick glance at least, but I am
> puzzled by two of the changes you are making.  See below.
> 
>> diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
>> index 6bf66649..c265800 100644
>> --- a/arch/powerpc/kvm/book3s_hv.c
>> +++ b/arch/powerpc/kvm/book3s_hv.c
>> @@ -1698,7 +1698,8 @@ static int kvmppc_get_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
>> 		*val = get_reg_val(id, vcpu->arch.sdar);
>> 		break;
>> 	case KVM_REG_PPC_SIER:
>> -		*val = get_reg_val(id, vcpu->arch.sier);
>> +		i = id - KVM_REG_PPC_SIER;
>> +		*val = get_reg_val(id, vcpu->arch.sier[i]);
> 
> This is inside a switch (id) statement, so here we know that id is
> KVM_REG_PPC_SIER.  In other words i will always be zero, so what is
> the point of doing the subtraction?
> 
>> 		break;
>> 	case KVM_REG_PPC_IAMR:
>> 		*val = get_reg_val(id, vcpu->arch.iamr);
>> @@ -1919,7 +1920,8 @@ static int kvmppc_set_one_reg_hv(struct kvm_vcpu *vcpu, u64 id,
>> 		vcpu->arch.sdar = set_reg_val(id, *val);
>> 		break;
>> 	case KVM_REG_PPC_SIER:
>> -		vcpu->arch.sier = set_reg_val(id, *val);
>> +		i = id - KVM_REG_PPC_SIER;
>> +		vcpu->arch.sier[i] = set_reg_val(id, *val);
> 
> Same comment here.

Hi Paul,

Thanks for reviewing the patch. Yes, true that currently `id` will be zero since it is only KVM_REG_PPC_SIER. I have kept the subtraction here considering that there will be addition of new registers to switch case. 
ex: case KVM_REG_PPC_SIER..KVM_REG_PPC_SIER3

> 
> I think that new defines for the new registers will need to be added
> to arch/powerpc/include/uapi/asm/kvm.h and
> Documentation/virt/kvm/api.rst, and then new cases will need to be
> added to these switch statements.

Yes, New registers are not yet added to kvm.h 
I will address these comments and include changes for arch/powerpc/include/uapi/asm/kvm.h and Documentation/virt/kvm/api.rst in the
next version.

> 
> By the way, please cc kvm-ppc@vger.kernel.org and kvm@vger.kernel.org
> on KVM patches.

Sure, will include KVM mailing list in the next version

Thanks
Athira 
> 
> Paul.


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  reply index

Thread overview: 41+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-01  9:20 [PATCH v2 00/10] powerpc/perf: Add support for power10 PMU Hardware Athira Rajeev
2020-07-01  9:20 ` [PATCH v2 01/10] powerpc/perf: Add support for ISA3.1 PMU SPRs Athira Rajeev
2020-07-08 11:02   ` Michael Ellerman
2020-07-09  1:53     ` Athira Rajeev
2020-07-13 12:50       ` Michael Ellerman
2020-07-15  6:07         ` Athira Rajeev
2020-07-01  9:20 ` [PATCH v2 02/10] KVM: PPC: Book3S HV: Save/restore new PMU registers Athira Rajeev
2020-07-01 11:11   ` Paul Mackerras
2020-07-02  6:22     ` Athira Rajeev [this message]
2020-07-07  6:13   ` Michael Neuling
2020-07-01  9:20 ` [PATCH v2 03/10] powerpc/xmon: Add PowerISA v3.1 PMU SPRs Athira Rajeev
2020-07-08 11:04   ` Michael Ellerman
2020-07-09  1:57     ` Athira Rajeev
2020-07-01  9:20 ` [PATCH v2 04/10] powerpc/perf: Add power10_feat to dt_cpu_ftrs Athira Rajeev
2020-07-07  6:22   ` Michael Neuling
2020-07-08  2:13     ` Athira Rajeev
2020-07-08 11:15   ` Michael Ellerman
2020-07-09 11:07     ` Athira Rajeev
2020-07-01  9:20 ` [PATCH v2 05/10] powerpc/perf: Update Power PMU cache_events to u64 type Athira Rajeev
2020-07-01  9:20 ` [PATCH v2 06/10] powerpc/perf: power10 Performance Monitoring support Athira Rajeev
2020-07-02  9:06   ` kernel test robot
2020-07-07  6:50   ` Michael Neuling
2020-07-08 10:56     ` Athira Rajeev
2020-07-01  9:20 ` [PATCH v2 07/10] powerpc/perf: support BHRB disable bit and new filtering modes Athira Rajeev
2020-07-07  7:17   ` Michael Neuling
2020-07-08  7:41     ` Athira Rajeev
2020-07-08  7:43     ` Gautham R Shenoy
2020-07-09  2:01       ` Athira Rajeev
2020-07-08 11:42   ` Michael Ellerman
2020-07-09  2:43     ` Athira Rajeev
2020-07-01  9:21 ` [PATCH v2 08/10] powerpc/perf: Add support for outputting extended regs in perf intr_regs Athira Rajeev
2020-07-01  9:21 ` [PATCH v2 09/10] tools/perf: Add perf tools support for extended register capability in powerpc Athira Rajeev
2020-07-08 12:04   ` Michael Ellerman
2020-07-09  3:10     ` Athira Rajeev
2020-07-13 12:47       ` Michael Ellerman
2020-07-13  2:36     ` Athira Rajeev
2020-07-01  9:21 ` [PATCH v2 10/10] powerpc/perf: Add extended regs support for power10 platform Athira Rajeev
2020-07-02  9:40   ` kernel test robot
2020-07-08  1:53     ` Athira Rajeev
2020-07-08 12:04   ` Michael Ellerman
2020-07-09  6:29     ` Athira Rajeev

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