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From: Ashish Mhetre <amhetre@nvidia.com>
To: Dmitry Osipenko <dmitry.osipenko@collabora.com>,
	Dmitry Osipenko <digetx@gmail.com>,
	krzysztof.kozlowski@canonical.com, robh+dt@kernel.org,
	thierry.reding@gmail.com, jonathanh@nvidia.com,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-tegra@vger.kernel.org
Cc: vdumpa@nvidia.com, Snikam@nvidia.com
Subject: Re: [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186 onward
Date: Wed, 30 Mar 2022 16:52:29 +0530	[thread overview]
Message-ID: <06174428-edb1-6478-1b2c-ede83c4bfa87@nvidia.com> (raw)
In-Reply-To: <bf851834-7812-13f1-a382-1f64078ff2a5@collabora.com>



On 3/30/2022 4:06 PM, Dmitry Osipenko wrote:
> External email: Use caution opening links or attachments
> 
> 
> On 3/30/22 13:16, Ashish Mhetre wrote:
>>
>>
>> On 3/30/2022 5:31 AM, Dmitry Osipenko wrote:
>>> External email: Use caution opening links or attachments
>>>
>>>
>>> On 3/22/22 20:34, Ashish Mhetre wrote:
>>>>>> +     switch (status & mc->soc->int_channel_mask) {
>>>>>> +     case BIT(0):
>>>>>> +             *mc_channel = 0;
>>>>>> +             break;
>>>>>> +
>>>>>> +     case BIT(1):
>>>>>> +             *mc_channel = 1;
>>>>>> +             break;
>>>>>> +
>>>>>> +     case BIT(2):
>>>>>> +             *mc_channel = 2;
>>>>>> +             break;
>>>>>> +
>>>>>> +     case BIT(3):
>>>>>> +             *mc_channel = 3;
>>>>>> +             break;
>>>>>> +
>>>>>> +     case BIT(24):
>>>>>> +             *mc_channel = MC_BROADCAST_CHANNEL;
>>>>>> +             break;
>>>>>> +
>>>>>> +     default:
>>>>>> +             pr_err("Unknown interrupt source\n");
>>>>>
>>>>> dev_err_ratelimited("unknown interrupt channel 0x%08x\n", status) and
>>>>> should be moved to the common interrupt handler.
>>>>>
>>>> So return just error from default case and handle error in common
>>>> interrupt handler with this print, right? I'll update this in next
>>>> version.
>>>
>>> Yes, just move out the common print.
>>>
>>> Although, you could parameterize the shift per SoC and then have a
>>> common helper that does "status >> intmask_chan_shift", couldn't you?
>>
>> Do you mean shift to get the channel, like
>> "channel = status >> intmask_chan_shift"?
>> So to get rid of this callback completely and adding a variable in
>> tegra_mc_soc for intmask_chan_shift, right? Or compute shift in this
>> callback and use it in common handler?
> 
> Add variable to tegra_mc_soc.
> 
> The intmask_chan_shift is a misnomer, perhaps something like
> status_reg_chan_shift will be a better name.
> 
Okay, I will do this.

>> If we are to remove this callback then how to handle unknown interrupt
>> channel error?
> 
> Create a common helper function that returns ID of the raised channel or
> errorno if not bits are set.
> 
So something like this:

int status_to_channel(const struct tegra_mc *mc, u32 status,
		      unsigned int *mc_channel)
{
	if ((status & mc->soc->ch_intmask) == 0)
		return -EINVAL;

	*mc_channel = __ffs((status & mc->soc->ch_intmask) >>
			     mc->soc->status_reg_chan_shift);

	return 0;
}

Correct?

>> Also we want to handle interrupts on one channel at a time and then
>> clear it from status register. There can be interrupts on multiple
>> channel. So multiple bits from status will be set. Hence it will be
>> hard to parameterize shift such that it gives appropriate channel.
>> So I think current approach is fine. Please correct me if I am wrong
>> somewhere.
> 
> You may do the following:
> 
> 1. find the first channel bit set in the status reg
> 2. handle that channel
> 3. clear only the handled status bit, don't clear the other bits
> 4. return from interrupt
> 
> If there are other bits set, then interrupt handler will fire again and
> next channel will be handled.

For clearing status bit after handling, we can retrieve channel bit by
something like this:

ch_bit = BIT(*mc_channel) << mc->soc->status_reg_chan_shift;

Correct?

  reply	other threads:[~2022-03-30 11:22 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-16  9:25 [Patch v5 0/4] memory: tegra: Add MC channels and error logging Ashish Mhetre
2022-03-16  9:25 ` [Patch v5 1/4] memory: tegra: Add memory controller channels support Ashish Mhetre
2022-03-19 15:42   ` Dmitry Osipenko
2022-03-22 16:13     ` Ashish Mhetre
2022-03-25  4:50     ` Ashish Mhetre
2022-03-29 23:48       ` Dmitry Osipenko
2022-03-30  5:07         ` Ashish Mhetre
2022-03-20 12:31   ` Krzysztof Kozlowski
2022-03-22 18:04     ` Ashish Mhetre
2022-03-22 18:24       ` Krzysztof Kozlowski
2022-03-16  9:25 ` [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186 onward Ashish Mhetre
2022-03-19 15:50   ` Dmitry Osipenko
2022-03-19 16:19     ` Dmitry Osipenko
2022-03-22 17:51       ` Ashish Mhetre
2022-03-22 16:48     ` Ashish Mhetre
2022-03-19 15:59   ` Dmitry Osipenko
2022-03-22 17:23     ` Ashish Mhetre
2022-03-29 23:51       ` Dmitry Osipenko
2022-03-30  5:02         ` Ashish Mhetre
2022-03-19 16:14   ` Dmitry Osipenko
2022-03-22 17:34     ` Ashish Mhetre
2022-03-30  0:01       ` Dmitry Osipenko
2022-03-30 10:16         ` Ashish Mhetre
2022-03-30 10:36           ` Dmitry Osipenko
2022-03-30 11:22             ` Ashish Mhetre [this message]
2022-03-31 19:49               ` Dmitry Osipenko
2022-03-31 21:55                 ` Ashish Mhetre
2022-03-20 12:53   ` Dmitry Osipenko
2022-03-23  8:36     ` Ashish Mhetre
2022-03-30  0:06   ` Dmitry Osipenko
2022-03-30  9:03     ` Ashish Mhetre
2022-03-30 10:19       ` Dmitry Osipenko
2022-03-30 10:34         ` Ashish Mhetre
2022-03-16  9:25 ` [Patch v5 3/4] dt-bindings: memory: Update reg maxitems for tegra186 Ashish Mhetre
2022-03-19 15:42   ` Dmitry Osipenko
2022-03-20  2:13   ` Rob Herring
2022-03-20 12:42   ` Krzysztof Kozlowski
2022-03-22 18:12     ` Ashish Mhetre
2022-03-22 18:42       ` Krzysztof Kozlowski
2022-03-16  9:25 ` [Patch v5 4/4] arm64: tegra: Add memory controller channels Ashish Mhetre

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