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From: Dmitry Osipenko <digetx@gmail.com>
To: Ashish Mhetre <amhetre@nvidia.com>,
	krzysztof.kozlowski@canonical.com, robh+dt@kernel.org,
	thierry.reding@gmail.com, jonathanh@nvidia.com,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	linux-tegra@vger.kernel.org
Cc: vdumpa@nvidia.com, Snikam@nvidia.com
Subject: Re: [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186 onward
Date: Sat, 19 Mar 2022 18:59:38 +0300	[thread overview]
Message-ID: <168cf065-bc17-1ffc-8cc0-75775c7f3bcb@gmail.com> (raw)
In-Reply-To: <20220316092525.4554-3-amhetre@nvidia.com>

16.03.2022 12:25, Ashish Mhetre пишет:
> diff --git a/include/soc/tegra/mc.h b/include/soc/tegra/mc.h
> index 92f810c55b43..6f115436e344 100644
> --- a/include/soc/tegra/mc.h
> +++ b/include/soc/tegra/mc.h
> @@ -203,6 +203,8 @@ struct tegra_mc_soc {
>  	const struct tegra_smmu_soc *smmu;
>  
>  	u32 intmask;
> +	u32 int_channel_mask;

ch_intmask

> +	bool has_addr_hi_reg;
>  
>  	const struct tegra_mc_reset_ops *reset_ops;
>  	const struct tegra_mc_reset *resets;
> @@ -210,6 +212,8 @@ struct tegra_mc_soc {
>  
>  	const struct tegra_mc_icc_ops *icc_ops;
>  	const struct tegra_mc_ops *ops;
> +
> +	int (*get_int_channel)(const struct tegra_mc *mc, int *mc_channel);

This should be a part of tegra_mc_ops.

  parent reply	other threads:[~2022-03-19 15:59 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-16  9:25 [Patch v5 0/4] memory: tegra: Add MC channels and error logging Ashish Mhetre
2022-03-16  9:25 ` [Patch v5 1/4] memory: tegra: Add memory controller channels support Ashish Mhetre
2022-03-19 15:42   ` Dmitry Osipenko
2022-03-22 16:13     ` Ashish Mhetre
2022-03-25  4:50     ` Ashish Mhetre
2022-03-29 23:48       ` Dmitry Osipenko
2022-03-30  5:07         ` Ashish Mhetre
2022-03-20 12:31   ` Krzysztof Kozlowski
2022-03-22 18:04     ` Ashish Mhetre
2022-03-22 18:24       ` Krzysztof Kozlowski
2022-03-16  9:25 ` [Patch v5 2/4] memory: tegra: Add MC error logging on tegra186 onward Ashish Mhetre
2022-03-19 15:50   ` Dmitry Osipenko
2022-03-19 16:19     ` Dmitry Osipenko
2022-03-22 17:51       ` Ashish Mhetre
2022-03-22 16:48     ` Ashish Mhetre
2022-03-19 15:59   ` Dmitry Osipenko [this message]
2022-03-22 17:23     ` Ashish Mhetre
2022-03-29 23:51       ` Dmitry Osipenko
2022-03-30  5:02         ` Ashish Mhetre
2022-03-19 16:14   ` Dmitry Osipenko
2022-03-22 17:34     ` Ashish Mhetre
2022-03-30  0:01       ` Dmitry Osipenko
2022-03-30 10:16         ` Ashish Mhetre
2022-03-30 10:36           ` Dmitry Osipenko
2022-03-30 11:22             ` Ashish Mhetre
2022-03-31 19:49               ` Dmitry Osipenko
2022-03-31 21:55                 ` Ashish Mhetre
2022-03-20 12:53   ` Dmitry Osipenko
2022-03-23  8:36     ` Ashish Mhetre
2022-03-30  0:06   ` Dmitry Osipenko
2022-03-30  9:03     ` Ashish Mhetre
2022-03-30 10:19       ` Dmitry Osipenko
2022-03-30 10:34         ` Ashish Mhetre
2022-03-16  9:25 ` [Patch v5 3/4] dt-bindings: memory: Update reg maxitems for tegra186 Ashish Mhetre
2022-03-19 15:42   ` Dmitry Osipenko
2022-03-20  2:13   ` Rob Herring
2022-03-20 12:42   ` Krzysztof Kozlowski
2022-03-22 18:12     ` Ashish Mhetre
2022-03-22 18:42       ` Krzysztof Kozlowski
2022-03-16  9:25 ` [Patch v5 4/4] arm64: tegra: Add memory controller channels Ashish Mhetre

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