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From: Paolo Bonzini <pbonzini@redhat.com>
To: Borislav Petkov <bp@alien8.de>, "Luck, Tony" <tony.luck@intel.com>
Cc: Jim Mattson <jmattson@google.com>, Qian Cai <cai@redhat.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-tip-commits@vger.kernel.org" 
	<linux-tip-commits@vger.kernel.org>, x86 <x86@kernel.org>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Subject: Re: [PATCH] x86/mce: Check for hypervisor before enabling additional error logging
Date: Tue, 10 Nov 2020 09:50:43 +0100	[thread overview]
Message-ID: <094c2395-b1b3-d908-657c-9bd4144e40ac@redhat.com> (raw)
In-Reply-To: <20201110063151.GB7290@nazgul.tnic>

On 10/11/20 07:31, Borislav Petkov wrote:
>>   
>> +	if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
>> +		return;
>> +
> Frankly, I'm tired of wagging the dog because the tail can't. If
> qemu/kvm can't emulate a CPU model fully then it should ignore those
> unknown MSR accesses by default, i.e., that "ignore_msrs" functionality
> should be on by default I'd say...
> 
> We certainly can't be sprinkling this check everytime the kernel tries
> to do something as basic as read an MSR.

You don't have to, also because it's wrong.  Fortunately it's much 
simpler than that:

1) ignore_msrs _cannot_ be on by default.  You cannot know in advance 
that for all non-architectural MSRs it's okay for them to read as zero 
and eat writes.  For some non-architectural MSR which never reads as 
zero on real hardware, who knows that there isn't some code using the 
contents of the MSR as a divisor, and causing a division by zero 
exception with ignore_msrs=1?

2) it's not just KVM.  _Any_ hypervisor is bound to have this issue for 
some non-architectural MSRs.  KVM just gets the flak because Linux CI 
environments (for obvious reasons) use it more than they use Hyper-V or 
ESXi or VirtualBox.

3) because of (1) and (2), the solution is very simple.  If the MSR is 
architectural, its absence is a KVM bug and we'll fix it in all stable 
versions.  If the MSR is not architectural (and 17Fh isn't; not only 
it's not mentioned in the SDM, even Google is failing me), never ever 
assume that the CPUID family/model/stepping implies a given MSR is 
there, and just use rdmsr_safe/wrmsr_safe.

So, for this patch,

Nacked-by: Paolo Bonzini <pbonzini@redhat.com>

Paolo


  reply	other threads:[~2020-11-10  8:50 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <fcb21490-84a1-8b99-b494-3a6ac2a0e16a@skynet.be>
     [not found] ` <20201029100655.GA31903@zn.tnic>
     [not found]   ` <20201029151518.GA23990@agluck-desk2.amr.corp.intel.com>
     [not found]     ` <20201029194118.GC31903@zn.tnic>
     [not found]       ` <87ft5wo8zn.fsf@nanos.tec.linutronix.de>
     [not found]         ` <20201030091056.GA6532@zn.tnic>
     [not found]           ` <20201030190400.GA13797@agluck-desk2.amr.corp.intel.com>
2020-10-30 19:08             ` [PATCH] x86/mce: Enable additional error logging on certain Intel CPUs Luck, Tony
2020-11-02 11:12               ` Borislav Petkov
2020-11-02 11:18               ` [tip: ras/core] " tip-bot2 for Tony Luck
2020-11-09 21:55                 ` Qian Cai
2020-11-09 22:09                   ` Luck, Tony
2020-11-09 22:36                     ` Jim Mattson
2020-11-09 22:57                       ` Luck, Tony
2020-11-09 23:24                         ` [PATCH] x86/mce: Check for hypervisor before enabling additional error logging Luck, Tony
2020-11-10  6:31                           ` Borislav Petkov
2020-11-10  8:50                             ` Paolo Bonzini [this message]
2020-11-10  9:56                               ` Borislav Petkov
2020-11-10 10:40                                 ` Paolo Bonzini
2020-11-10 15:50                                   ` Borislav Petkov
2020-11-10 16:08                                     ` Paolo Bonzini
2020-11-10 17:52                                       ` Luck, Tony
2020-11-10 20:37                                         ` Paolo Bonzini
2020-11-11  0:39                                           ` [PATCH v2] x86/mce: Use "safe" MSR functions when " Luck, Tony
2020-11-16 16:44                                             ` [tip: ras/core] " tip-bot2 for Tony Luck
2020-11-09 23:26                         ` [tip: ras/core] x86/mce: Enable additional error logging on certain Intel CPUs Jim Mattson
2020-11-09 23:36                           ` Luck, Tony
2020-11-10  9:10                             ` Paolo Bonzini

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