From: "Luck, Tony" <tony.luck@intel.com>
To: Jim Mattson <jmattson@google.com>
Cc: Qian Cai <cai@redhat.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-tip-commits@vger.kernel.org"
<linux-tip-commits@vger.kernel.org>, Boris Petkov <bp@alien8.de>,
"Borislav Petkov" <bp@suse.de>, x86 <x86@kernel.org>,
Paolo Bonzini <pbonzini@redhat.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Subject: RE: [tip: ras/core] x86/mce: Enable additional error logging on certain Intel CPUs
Date: Mon, 9 Nov 2020 23:36:16 +0000 [thread overview]
Message-ID: <bece344ae6944368bf5a9a60e9145bd4@intel.com> (raw)
In-Reply-To: <CALMp9eS+SYmPP3OzdK0-Bs1wSBJ4MU_POZe3i5fi3Fd+FTshYw@mail.gmail.com>
> I wouldn't expect all hypervisors to necessarily set CPUID.01H:ECX[bit
> 31]. Architecturally, on Intel CPUs, that bit is simply defined as
> "not used." There is no documented contract between Intel and
> hypervisor vendors regarding the use of that bit. (AMD, on the other
> hand, *does* document that bit as "reserved for use by hypervisor to
> indicate guest status.")
Maybe no contract ... but a bunch of places (many of them in Intel
specific code) that check for it. Perhaps I should poke the owners
of the Intel SDM to accept the inevitable.
$ git grep "boot_cpu_has(X86_FEATURE_HYPERVISOR"
arch/x86/events/core.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
arch/x86/events/intel/core.c: if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
arch/x86/events/intel/core.c: int assume = 3 * !boot_cpu_has(X86_FEATURE_HYPERVISOR);
arch/x86/events/intel/cstate.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
arch/x86/events/intel/uncore.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
arch/x86/kernel/apic/apic.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
arch/x86/kernel/cpu/bugs.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
arch/x86/kernel/cpu/bugs.c: else if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
arch/x86/kernel/cpu/bugs.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
arch/x86/kernel/cpu/bugs.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
arch/x86/kernel/cpu/intel.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
arch/x86/kernel/cpu/mshyperv.c: if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
arch/x86/kernel/cpu/vmware.c: * If !boot_cpu_has(X86_FEATURE_HYPERVISOR), vmware_hypercall_mode
arch/x86/kernel/cpu/vmware.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
arch/x86/kernel/jailhouse.c: !boot_cpu_has(X86_FEATURE_HYPERVISOR))
arch/x86/kernel/kvm.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
arch/x86/kernel/paravirt.c: if (!boot_cpu_has(X86_FEATURE_HYPERVISOR))
arch/x86/kernel/tsc.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR) ||
arch/x86/mm/init_64.c: if (!boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
drivers/acpi/processor_idle.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h: return boot_cpu_has(X86_FEATURE_HYPERVISOR);
drivers/gpu/drm/i915/i915_memcpy.c: !boot_cpu_has(X86_FEATURE_HYPERVISOR))
drivers/gpu/drm/radeon/radeon_device.c: return boot_cpu_has(X86_FEATURE_HYPERVISOR);
drivers/visorbus/visorchipset.c: if (boot_cpu_has(X86_FEATURE_HYPERVISOR)) {
-Tony
next prev parent reply other threads:[~2020-11-09 23:36 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <fcb21490-84a1-8b99-b494-3a6ac2a0e16a@skynet.be>
[not found] ` <20201029100655.GA31903@zn.tnic>
[not found] ` <20201029151518.GA23990@agluck-desk2.amr.corp.intel.com>
[not found] ` <20201029194118.GC31903@zn.tnic>
[not found] ` <87ft5wo8zn.fsf@nanos.tec.linutronix.de>
[not found] ` <20201030091056.GA6532@zn.tnic>
[not found] ` <20201030190400.GA13797@agluck-desk2.amr.corp.intel.com>
2020-10-30 19:08 ` [PATCH] x86/mce: Enable additional error logging on certain Intel CPUs Luck, Tony
2020-11-02 11:12 ` Borislav Petkov
2020-11-02 11:18 ` [tip: ras/core] " tip-bot2 for Tony Luck
2020-11-09 21:55 ` Qian Cai
2020-11-09 22:09 ` Luck, Tony
2020-11-09 22:36 ` Jim Mattson
2020-11-09 22:57 ` Luck, Tony
2020-11-09 23:24 ` [PATCH] x86/mce: Check for hypervisor before enabling additional error logging Luck, Tony
2020-11-10 6:31 ` Borislav Petkov
2020-11-10 8:50 ` Paolo Bonzini
2020-11-10 9:56 ` Borislav Petkov
2020-11-10 10:40 ` Paolo Bonzini
2020-11-10 15:50 ` Borislav Petkov
2020-11-10 16:08 ` Paolo Bonzini
2020-11-10 17:52 ` Luck, Tony
2020-11-10 20:37 ` Paolo Bonzini
2020-11-11 0:39 ` [PATCH v2] x86/mce: Use "safe" MSR functions when " Luck, Tony
2020-11-16 16:44 ` [tip: ras/core] " tip-bot2 for Tony Luck
2020-11-09 23:26 ` [tip: ras/core] x86/mce: Enable additional error logging on certain Intel CPUs Jim Mattson
2020-11-09 23:36 ` Luck, Tony [this message]
2020-11-10 9:10 ` Paolo Bonzini
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