[PATCH] thermal: exynos: Handle the misplaced TRIMINFO register

[PATCH] thermal: exynos: Handle the misplaced TRIMINFO register

[Naveen Krishna Chatradhi]

This patch adds code to handle the misplaced TRIMINFO register
incase of Exynos5420.

On Exynos5420 we have a TRIMINFO register being misplaced for
TMU channels 2, 3 and 4

TRIMINFO at 0x1006c000 contains data for TMU channel 3
TRIMINFO at 0x100a0000 contains data for TMU channel 4
TRIMINFO at 0x10068000 contains data for TMU channel 2

The misplaced register address is passed through devicetree and
map it seperately during probe.
Also, adds the documentation under devicetree/bindings/thermal/

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
---

Rebased on http://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master branch. I'm not sure which one is the right tree to rebase.

 .../devicetree/bindings/thermal/exynos-thermal.txt | 48 ++++++++++++++++++++++
 drivers/thermal/exynos_thermal.c                   | 26 +++++++++++-
 2 files changed, 72 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/thermal/exynos-thermal.txt

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
new file mode 100644
index 0000000..1db279e
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -0,0 +1,48 @@
+* Exynos Thermal
+
+Required properties:
+- compatible: should be one of the following.
+    * "samsung,exynos4210-tmu" - for controllers compatible with exynos4210 tmu.
+    * "samsung,exynos5250-tmu" - for controllers compatible with exynos5250 tmu.
+    * "samsung,exynos5420-tmu" - for controllers compatible with exynos5420 tmu.
+
+- reg: physical base address of the controller and length of
+  memory mapped region.
+
+    ** NOTE FOR EXYNOS5420 **
+    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
+
+    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
+    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
+    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
+
+    * In such cases the reg property contains the misplaced register address and
+      range as the second parameter.
+
+- interrupts : interrupt number to the cpu.
+- clocks : Clock number as per common clock framework for the cpu.
+- clock-names : clock name to be used in the driver
+
+Example:
+
+	/* tmu for CPU0 */
+	tmu@10060000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x10060000 0x100>;
+		interrupts = <0 65 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+Example: In case of Exynos5420 TMU channel 3
+
+	/* tmu for CPU3 */
+	tmu@1006c000 {
+		compatible = "samsung,exynos5420-tmu";
+		/* 2nd reg is for the misplaced TRIMINFO register */
+		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+		interrupts = <0 185 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
index cec3f1f..a229314 100644
--- a/drivers/thermal/exynos_thermal.c
+++ b/drivers/thermal/exynos_thermal.c
@@ -38,6 +38,7 @@
 #include <linux/cpufreq.h>
 #include <linux/cpu_cooling.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 
 #include <plat/cpu.h>
 #include <mach/regs-pmu.h>	/* for EXYNOS5_PS_HOLD_CONTROL */
@@ -123,7 +124,7 @@ struct exynos_thermal_zone;
 struct exynos_tmu_data {
 	struct exynos_tmu_platform_data *pdata;
 	struct resource *mem;
-	void __iomem *base;
+	void __iomem *base, *triminfo_base;
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -665,8 +666,14 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 		__raw_writel(EXYNOS_TRIMINFO_RELOAD,
 				data->base + EXYNOS_TMU_TRIMINFO_CON);
 	}
+
 	/* Save trimming info in order to perform calibration */
-	trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
+	if (data->triminfo_base)
+		/* On exynos5420 TRIMINFO is misplaced for some channels */
+		trim_info = readl(data->triminfo_base);
+	else
+		trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
+
 	data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
 
@@ -1016,6 +1023,15 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	/* For Exynos5420 The misplaced TERMINFO register address will be
+	 * passed from device tree node.
+	 *
+	 * We cannot use devm_request_and_ioremap, as the base address
+	 * over laps with the address space of the other TMU channel.
+	 * Check Documentation for details
+	 */
+	data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
+
 	data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
 	if (IS_ERR(data->clk)) {
 		dev_err(&pdev->dev, "Failed to get clock\n");
@@ -1086,6 +1102,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 err_irq:
 	exynos_unregister_thermal(data);
 err_clk:
+	if (data->triminfo_base)
+		iounmap(data->triminfo_base);
+
 	platform_set_drvdata(pdev, NULL);
 	clk_unprepare(data->clk);
 	return ret;
@@ -1100,6 +1119,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
 
 	exynos_unregister_thermal(data);
 
+	if (data->triminfo_base)
+		iounmap(data->triminfo_base);
+
 	clk_unprepare(data->clk);
 
 	platform_set_drvdata(pdev, NULL);
-- 
1.7.12.4

Re: [PATCH] thermal: exynos: Handle the misplaced TRIMINFO register

[amit daniel kachhap]

Hi Naveen,

Can you rebase these patches against
https://git.kernel.org/cgit/linux/kernel/git/evalenti/linux-soc-thermal.git/log/?h=next.
All these patches have been queued for 3.12 merge and contains the new
re-structured TMU driver.

Thanks,
Amit Daniel

On Thu, Aug 1, 2013 at 11:32 AM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> This patch adds code to handle the misplaced TRIMINFO register
> incase of Exynos5420.
>
> On Exynos5420 we have a TRIMINFO register being misplaced for
> TMU channels 2, 3 and 4
>
> TRIMINFO at 0x1006c000 contains data for TMU channel 3
> TRIMINFO at 0x100a0000 contains data for TMU channel 4
> TRIMINFO at 0x10068000 contains data for TMU channel 2
>
> The misplaced register address is passed through devicetree and
> map it seperately during probe.
> Also, adds the documentation under devicetree/bindings/thermal/
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Reviewed-by: Doug Anderson <dianders@chromium.org>
> ---
>
> Rebased on http://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
> master branch. I'm not sure which one is the right tree to rebase.
>
>  .../devicetree/bindings/thermal/exynos-thermal.txt | 48 ++++++++++++++++++++++
>  drivers/thermal/exynos_thermal.c                   | 26 +++++++++++-
>  2 files changed, 72 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> new file mode 100644
> index 0000000..1db279e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -0,0 +1,48 @@
> +* Exynos Thermal
> +
> +Required properties:
> +- compatible: should be one of the following.
> +    * "samsung,exynos4210-tmu" - for controllers compatible with exynos4210 tmu.
> +    * "samsung,exynos5250-tmu" - for controllers compatible with exynos5250 tmu.
> +    * "samsung,exynos5420-tmu" - for controllers compatible with exynos5420 tmu.
> +
> +- reg: physical base address of the controller and length of
> +  memory mapped region.
> +
> +    ** NOTE FOR EXYNOS5420 **
> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
> +
> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
> +
> +    * In such cases the reg property contains the misplaced register address and
> +      range as the second parameter.
> +
> +- interrupts : interrupt number to the cpu.
> +- clocks : Clock number as per common clock framework for the cpu.
> +- clock-names : clock name to be used in the driver
> +
> +Example:
> +
> +       /* tmu for CPU0 */
> +       tmu@10060000 {
> +               compatible = "samsung,exynos5420-tmu";
> +               reg = <0x10060000 0x100>;
> +               interrupts = <0 65 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif";
> +       };
> +
> +Example: In case of Exynos5420 TMU channel 3
> +
> +       /* tmu for CPU3 */
> +       tmu@1006c000 {
> +               compatible = "samsung,exynos5420-tmu";
> +               /* 2nd reg is for the misplaced TRIMINFO register */
> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
> +               interrupts = <0 185 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif";
> +       };
> +
> diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
> index cec3f1f..a229314 100644
> --- a/drivers/thermal/exynos_thermal.c
> +++ b/drivers/thermal/exynos_thermal.c
> @@ -38,6 +38,7 @@
>  #include <linux/cpufreq.h>
>  #include <linux/cpu_cooling.h>
>  #include <linux/of.h>
> +#include <linux/of_address.h>
>
>  #include <plat/cpu.h>
>  #include <mach/regs-pmu.h>     /* for EXYNOS5_PS_HOLD_CONTROL */
> @@ -123,7 +124,7 @@ struct exynos_thermal_zone;
>  struct exynos_tmu_data {
>         struct exynos_tmu_platform_data *pdata;
>         struct resource *mem;
> -       void __iomem *base;
> +       void __iomem *base, *triminfo_base;
>         int irq;
>         enum soc_type soc;
>         struct work_struct irq_work;
> @@ -665,8 +666,14 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>                 __raw_writel(EXYNOS_TRIMINFO_RELOAD,
>                                 data->base + EXYNOS_TMU_TRIMINFO_CON);
>         }
> +
>         /* Save trimming info in order to perform calibration */
> -       trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
> +       if (data->triminfo_base)
> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
> +               trim_info = readl(data->triminfo_base);
> +       else
> +               trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
> +
>         data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
>         data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
>
> @@ -1016,6 +1023,15 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>                 return -ENODEV;
>         }
>
> +       /* For Exynos5420 The misplaced TERMINFO register address will be
> +        * passed from device tree node.
> +        *
> +        * We cannot use devm_request_and_ioremap, as the base address
> +        * over laps with the address space of the other TMU channel.
> +        * Check Documentation for details
> +        */
> +       data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
> +
>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>         if (IS_ERR(data->clk)) {
>                 dev_err(&pdev->dev, "Failed to get clock\n");
> @@ -1086,6 +1102,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>  err_irq:
>         exynos_unregister_thermal(data);
>  err_clk:
> +       if (data->triminfo_base)
> +               iounmap(data->triminfo_base);
> +
>         platform_set_drvdata(pdev, NULL);
>         clk_unprepare(data->clk);
>         return ret;
> @@ -1100,6 +1119,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>
>         exynos_unregister_thermal(data);
>
> +       if (data->triminfo_base)
> +               iounmap(data->triminfo_base);
> +
>         clk_unprepare(data->clk);
>
>         platform_set_drvdata(pdev, NULL);
> --
> 1.7.12.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH] thermal: exynos: Handle the misplaced TRIMINFO register

[Naveen Krishna Ch]

On 1 August 2013 14:02, amit daniel kachhap <amit.daniel@samsung.com> wrote:
> Hi Naveen,
>
> Can you rebase these patches against
> https://git.kernel.org/cgit/linux/kernel/git/evalenti/linux-soc-thermal.git/log/?h=next.
> All these patches have been queued for 3.12 merge and contains the new
> re-structured TMU driver.
Sure, I will re base and submit.
>
> Thanks,
> Amit Daniel
>
> On Thu, Aug 1, 2013 at 11:32 AM, Naveen Krishna Chatradhi
> <ch.naveen@samsung.com> wrote:
>> This patch adds code to handle the misplaced TRIMINFO register
>> incase of Exynos5420.
>>
>> On Exynos5420 we have a TRIMINFO register being misplaced for
>> TMU channels 2, 3 and 4
>>
>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>> TRIMINFO at 0x10068000 contains data for TMU channel 2
>>
>> The misplaced register address is passed through devicetree and
>> map it seperately during probe.
>> Also, adds the documentation under devicetree/bindings/thermal/
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> Reviewed-by: Doug Anderson <dianders@chromium.org>
>> ---
>>
>> Rebased on http://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
>> master branch. I'm not sure which one is the right tree to rebase.
>>
>>  .../devicetree/bindings/thermal/exynos-thermal.txt | 48 ++++++++++++++++++++++
>>  drivers/thermal/exynos_thermal.c                   | 26 +++++++++++-
>>  2 files changed, 72 insertions(+), 2 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>
>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> new file mode 100644
>> index 0000000..1db279e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> @@ -0,0 +1,48 @@
>> +* Exynos Thermal
>> +
>> +Required properties:
>> +- compatible: should be one of the following.
>> +    * "samsung,exynos4210-tmu" - for controllers compatible with exynos4210 tmu.
>> +    * "samsung,exynos5250-tmu" - for controllers compatible with exynos5250 tmu.
>> +    * "samsung,exynos5420-tmu" - for controllers compatible with exynos5420 tmu.
>> +
>> +- reg: physical base address of the controller and length of
>> +  memory mapped region.
>> +
>> +    ** NOTE FOR EXYNOS5420 **
>> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
>> +
>> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
>> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
>> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
>> +
>> +    * In such cases the reg property contains the misplaced register address and
>> +      range as the second parameter.
>> +
>> +- interrupts : interrupt number to the cpu.
>> +- clocks : Clock number as per common clock framework for the cpu.
>> +- clock-names : clock name to be used in the driver
>> +
>> +Example:
>> +
>> +       /* tmu for CPU0 */
>> +       tmu@10060000 {
>> +               compatible = "samsung,exynos5420-tmu";
>> +               reg = <0x10060000 0x100>;
>> +               interrupts = <0 65 0>;
>> +               clocks = <&clock 318>;
>> +               clock-names = "tmu_apbif";
>> +       };
>> +
>> +Example: In case of Exynos5420 TMU channel 3
>> +
>> +       /* tmu for CPU3 */
>> +       tmu@1006c000 {
>> +               compatible = "samsung,exynos5420-tmu";
>> +               /* 2nd reg is for the misplaced TRIMINFO register */
>> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>> +               interrupts = <0 185 0>;
>> +               clocks = <&clock 318>;
>> +               clock-names = "tmu_apbif";
>> +       };
>> +
>> diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
>> index cec3f1f..a229314 100644
>> --- a/drivers/thermal/exynos_thermal.c
>> +++ b/drivers/thermal/exynos_thermal.c
>> @@ -38,6 +38,7 @@
>>  #include <linux/cpufreq.h>
>>  #include <linux/cpu_cooling.h>
>>  #include <linux/of.h>
>> +#include <linux/of_address.h>
>>
>>  #include <plat/cpu.h>
>>  #include <mach/regs-pmu.h>     /* for EXYNOS5_PS_HOLD_CONTROL */
>> @@ -123,7 +124,7 @@ struct exynos_thermal_zone;
>>  struct exynos_tmu_data {
>>         struct exynos_tmu_platform_data *pdata;
>>         struct resource *mem;
>> -       void __iomem *base;
>> +       void __iomem *base, *triminfo_base;
>>         int irq;
>>         enum soc_type soc;
>>         struct work_struct irq_work;
>> @@ -665,8 +666,14 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>>                 __raw_writel(EXYNOS_TRIMINFO_RELOAD,
>>                                 data->base + EXYNOS_TMU_TRIMINFO_CON);
>>         }
>> +
>>         /* Save trimming info in order to perform calibration */
>> -       trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
>> +       if (data->triminfo_base)
>> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
>> +               trim_info = readl(data->triminfo_base);
>> +       else
>> +               trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
>> +
>>         data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
>>         data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
>>
>> @@ -1016,6 +1023,15 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>                 return -ENODEV;
>>         }
>>
>> +       /* For Exynos5420 The misplaced TERMINFO register address will be
>> +        * passed from device tree node.
>> +        *
>> +        * We cannot use devm_request_and_ioremap, as the base address
>> +        * over laps with the address space of the other TMU channel.
>> +        * Check Documentation for details
>> +        */
>> +       data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
>> +
>>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>>         if (IS_ERR(data->clk)) {
>>                 dev_err(&pdev->dev, "Failed to get clock\n");
>> @@ -1086,6 +1102,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>  err_irq:
>>         exynos_unregister_thermal(data);
>>  err_clk:
>> +       if (data->triminfo_base)
>> +               iounmap(data->triminfo_base);
>> +
>>         platform_set_drvdata(pdev, NULL);
>>         clk_unprepare(data->clk);
>>         return ret;
>> @@ -1100,6 +1119,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>>
>>         exynos_unregister_thermal(data);
>>
>> +       if (data->triminfo_base)
>> +               iounmap(data->triminfo_base);
>> +
>>         clk_unprepare(data->clk);
>>
>>         platform_set_drvdata(pdev, NULL);
>> --
>> 1.7.12.4
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Shine bright,
(: Nav :)

[PATCH v2] thermal: exynos: Handle the misplaced TRIMINFO register

[Naveen Krishna Chatradhi]

This patch adds code to handle the misplaced TRIMINFO register
incase of Exynos5420.

On Exynos5420 we have a TRIMINFO register being misplaced for
TMU channels 2, 3 and 4

TRIMINFO at 0x1006c000 contains data for TMU channel 3
TRIMINFO at 0x100a0000 contains data for TMU channel 4
TRIMINFO at 0x10068000 contains data for TMU channel 2

The misplaced register address is passed through devicetree and
map it seperately during probe.
Also, adds the documentation under devicetree/bindings/thermal/

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
---
Changes since v1:
Rebased on http://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git

 .../devicetree/bindings/thermal/exynos-thermal.txt |   48 ++++++++++++++++++++
 drivers/thermal/exynos_thermal.c                   |   26 ++++++++++-
 2 files changed, 72 insertions(+), 2 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/thermal/exynos-thermal.txt

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
new file mode 100644
index 0000000..1db279e
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -0,0 +1,48 @@
+* Exynos Thermal
+
+Required properties:
+- compatible: should be one of the following.
+    * "samsung,exynos4210-tmu" - for controllers compatible with exynos4210 tmu.
+    * "samsung,exynos5250-tmu" - for controllers compatible with exynos5250 tmu.
+    * "samsung,exynos5420-tmu" - for controllers compatible with exynos5420 tmu.
+
+- reg: physical base address of the controller and length of
+  memory mapped region.
+
+    ** NOTE FOR EXYNOS5420 **
+    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
+
+    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
+    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
+    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
+
+    * In such cases the reg property contains the misplaced register address and
+      range as the second parameter.
+
+- interrupts : interrupt number to the cpu.
+- clocks : Clock number as per common clock framework for the cpu.
+- clock-names : clock name to be used in the driver
+
+Example:
+
+	/* tmu for CPU0 */
+	tmu@10060000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x10060000 0x100>;
+		interrupts = <0 65 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+Example: In case of Exynos5420 TMU channel 3
+
+	/* tmu for CPU3 */
+	tmu@1006c000 {
+		compatible = "samsung,exynos5420-tmu";
+		/* 2nd reg is for the misplaced TRIMINFO register */
+		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+		interrupts = <0 185 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
index d20ce9e..1ad9005 100644
--- a/drivers/thermal/exynos_thermal.c
+++ b/drivers/thermal/exynos_thermal.c
@@ -38,6 +38,7 @@
 #include <linux/cpufreq.h>
 #include <linux/cpu_cooling.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 
 /* Exynos generic registers */
 #define EXYNOS_TMU_REG_TRIMINFO		0x0
@@ -120,7 +121,7 @@
 struct exynos_tmu_data {
 	struct exynos_tmu_platform_data *pdata;
 	struct resource *mem;
-	void __iomem *base;
+	void __iomem *base, *triminfo_base;
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -593,8 +594,14 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 		__raw_writel(EXYNOS_TRIMINFO_RELOAD,
 				data->base + EXYNOS_TMU_TRIMINFO_CON);
 	}
+
 	/* Save trimming info in order to perform calibration */
-	trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
+	if (data->triminfo_base)
+		/* On exynos5420 TRIMINFO is misplaced for some channels */
+		trim_info = readl(data->triminfo_base);
+	else
+		trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
+
 	data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
 
@@ -941,6 +948,15 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	/* For Exynos5420 The misplaced TERMINFO register address will be
+	 * passed from device tree node.
+	 *
+	 * We cannot use devm_request_and_ioremap, as the base address
+	 * over laps with the address space of the other TMU channel.
+	 * Check Documentation for details
+	 */
+	data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
+
 	data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
 	if (IS_ERR(data->clk)) {
 		dev_err(&pdev->dev, "Failed to get clock\n");
@@ -1001,6 +1017,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 
 	return 0;
 err_clk:
+	if (data->triminfo_base)
+		iounmap(data->triminfo_base);
+
 	platform_set_drvdata(pdev, NULL);
 	clk_unprepare(data->clk);
 	return ret;
@@ -1014,6 +1033,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
 
 	exynos_unregister_thermal();
 
+	if (data->triminfo_base)
+		iounmap(data->triminfo_base);
+
 	clk_unprepare(data->clk);
 
 	platform_set_drvdata(pdev, NULL);
-- 
1.7.9.5

Re: [PATCH v2] thermal: exynos: Handle the misplaced TRIMINFO register

[amit daniel kachhap]

Hi Naveen,

On Thu, Aug 1, 2013 at 4:06 PM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> This patch adds code to handle the misplaced TRIMINFO register
> incase of Exynos5420.
>
> On Exynos5420 we have a TRIMINFO register being misplaced for
> TMU channels 2, 3 and 4
>
> TRIMINFO at 0x1006c000 contains data for TMU channel 3
> TRIMINFO at 0x100a0000 contains data for TMU channel 4
> TRIMINFO at 0x10068000 contains data for TMU channel 2
>
> The misplaced register address is passed through devicetree and
> map it seperately during probe.
> Also, adds the documentation under devicetree/bindings/thermal/
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Reviewed-by: Doug Anderson <dianders@chromium.org>
> ---
> Changes since v1:
> Rebased on http://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git
Is it rebased against next branch?
>
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   48 ++++++++++++++++++++
>  drivers/thermal/exynos_thermal.c                   |   26 ++++++++++-
In the new directory structure this file is renamed as
drivers/thermal/samsung/exynos_tmu.c.

Thanks,
Amit Daniel
>  2 files changed, 72 insertions(+), 2 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> new file mode 100644
> index 0000000..1db279e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -0,0 +1,48 @@
> +* Exynos Thermal
> +
> +Required properties:
> +- compatible: should be one of the following.
> +    * "samsung,exynos4210-tmu" - for controllers compatible with exynos4210 tmu.
> +    * "samsung,exynos5250-tmu" - for controllers compatible with exynos5250 tmu.
> +    * "samsung,exynos5420-tmu" - for controllers compatible with exynos5420 tmu.
> +
> +- reg: physical base address of the controller and length of
> +  memory mapped region.
> +
> +    ** NOTE FOR EXYNOS5420 **
> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
> +
> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
> +
> +    * In such cases the reg property contains the misplaced register address and
> +      range as the second parameter.
> +
> +- interrupts : interrupt number to the cpu.
> +- clocks : Clock number as per common clock framework for the cpu.
> +- clock-names : clock name to be used in the driver
> +
> +Example:
> +
> +       /* tmu for CPU0 */
> +       tmu@10060000 {
> +               compatible = "samsung,exynos5420-tmu";
> +               reg = <0x10060000 0x100>;
> +               interrupts = <0 65 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif";
> +       };
> +
> +Example: In case of Exynos5420 TMU channel 3
> +
> +       /* tmu for CPU3 */
> +       tmu@1006c000 {
> +               compatible = "samsung,exynos5420-tmu";
> +               /* 2nd reg is for the misplaced TRIMINFO register */
> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
> +               interrupts = <0 185 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif";
> +       };
> +
> diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
> index d20ce9e..1ad9005 100644
> --- a/drivers/thermal/exynos_thermal.c
> +++ b/drivers/thermal/exynos_thermal.c
> @@ -38,6 +38,7 @@
>  #include <linux/cpufreq.h>
>  #include <linux/cpu_cooling.h>
>  #include <linux/of.h>
> +#include <linux/of_address.h>
>
>  /* Exynos generic registers */
>  #define EXYNOS_TMU_REG_TRIMINFO                0x0
> @@ -120,7 +121,7 @@
>  struct exynos_tmu_data {
>         struct exynos_tmu_platform_data *pdata;
>         struct resource *mem;
> -       void __iomem *base;
> +       void __iomem *base, *triminfo_base;
>         int irq;
>         enum soc_type soc;
>         struct work_struct irq_work;
> @@ -593,8 +594,14 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>                 __raw_writel(EXYNOS_TRIMINFO_RELOAD,
>                                 data->base + EXYNOS_TMU_TRIMINFO_CON);
>         }
> +
>         /* Save trimming info in order to perform calibration */
> -       trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
> +       if (data->triminfo_base)
> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
> +               trim_info = readl(data->triminfo_base);
> +       else
> +               trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
> +
>         data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
>         data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
>
> @@ -941,6 +948,15 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>                 return ret;
>         }
>
> +       /* For Exynos5420 The misplaced TERMINFO register address will be
> +        * passed from device tree node.
> +        *
> +        * We cannot use devm_request_and_ioremap, as the base address
> +        * over laps with the address space of the other TMU channel.
> +        * Check Documentation for details
> +        */
> +       data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
> +
>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>         if (IS_ERR(data->clk)) {
>                 dev_err(&pdev->dev, "Failed to get clock\n");
> @@ -1001,6 +1017,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>
>         return 0;
>  err_clk:
> +       if (data->triminfo_base)
> +               iounmap(data->triminfo_base);
> +
>         platform_set_drvdata(pdev, NULL);
>         clk_unprepare(data->clk);
>         return ret;
> @@ -1014,6 +1033,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>
>         exynos_unregister_thermal();
>
> +       if (data->triminfo_base)
> +               iounmap(data->triminfo_base);
> +
>         clk_unprepare(data->clk);
>
>         platform_set_drvdata(pdev, NULL);
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v2] thermal: exynos: Handle the misplaced TRIMINFO register

[Naveen Krishna Ch]

On 7 August 2013 12:06, amit daniel kachhap <amit.daniel@samsung.com> wrote:
> Hi Naveen,
>
> On Thu, Aug 1, 2013 at 4:06 PM, Naveen Krishna Chatradhi
> <ch.naveen@samsung.com> wrote:
>> This patch adds code to handle the misplaced TRIMINFO register
>> incase of Exynos5420.
>>
>> On Exynos5420 we have a TRIMINFO register being misplaced for
>> TMU channels 2, 3 and 4
>>
>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>> TRIMINFO at 0x10068000 contains data for TMU channel 2
>>
>> The misplaced register address is passed through devicetree and
>> map it seperately during probe.
>> Also, adds the documentation under devicetree/bindings/thermal/
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> Reviewed-by: Doug Anderson <dianders@chromium.org>
>> ---
>> Changes since v1:
>> Rebased on http://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux-soc-thermal.git
> Is it rebased against next branch?

Sorry, i re based it on to master.
>>
>>  .../devicetree/bindings/thermal/exynos-thermal.txt |   48 ++++++++++++++++++++
>>  drivers/thermal/exynos_thermal.c                   |   26 ++++++++++-
> In the new directory structure this file is renamed as
> drivers/thermal/samsung/exynos_tmu.c.
Yea, just checked it. Will re-base and submit.
>
> Thanks,
> Amit Daniel
>>  2 files changed, 72 insertions(+), 2 deletions(-)
>>  create mode 100644 Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>
>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> new file mode 100644
>> index 0000000..1db279e
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> @@ -0,0 +1,48 @@
>> +* Exynos Thermal
>> +
>> +Required properties:
>> +- compatible: should be one of the following.
>> +    * "samsung,exynos4210-tmu" - for controllers compatible with exynos4210 tmu.
>> +    * "samsung,exynos5250-tmu" - for controllers compatible with exynos5250 tmu.
>> +    * "samsung,exynos5420-tmu" - for controllers compatible with exynos5420 tmu.
>> +
>> +- reg: physical base address of the controller and length of
>> +  memory mapped region.
>> +
>> +    ** NOTE FOR EXYNOS5420 **
>> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
>> +
>> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
>> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
>> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
>> +
>> +    * In such cases the reg property contains the misplaced register address and
>> +      range as the second parameter.
>> +
>> +- interrupts : interrupt number to the cpu.
>> +- clocks : Clock number as per common clock framework for the cpu.
>> +- clock-names : clock name to be used in the driver
>> +
>> +Example:
>> +
>> +       /* tmu for CPU0 */
>> +       tmu@10060000 {
>> +               compatible = "samsung,exynos5420-tmu";
>> +               reg = <0x10060000 0x100>;
>> +               interrupts = <0 65 0>;
>> +               clocks = <&clock 318>;
>> +               clock-names = "tmu_apbif";
>> +       };
>> +
>> +Example: In case of Exynos5420 TMU channel 3
>> +
>> +       /* tmu for CPU3 */
>> +       tmu@1006c000 {
>> +               compatible = "samsung,exynos5420-tmu";
>> +               /* 2nd reg is for the misplaced TRIMINFO register */
>> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>> +               interrupts = <0 185 0>;
>> +               clocks = <&clock 318>;
>> +               clock-names = "tmu_apbif";
>> +       };
>> +
>> diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
>> index d20ce9e..1ad9005 100644
>> --- a/drivers/thermal/exynos_thermal.c
>> +++ b/drivers/thermal/exynos_thermal.c
>> @@ -38,6 +38,7 @@
>>  #include <linux/cpufreq.h>
>>  #include <linux/cpu_cooling.h>
>>  #include <linux/of.h>
>> +#include <linux/of_address.h>
>>
>>  /* Exynos generic registers */
>>  #define EXYNOS_TMU_REG_TRIMINFO                0x0
>> @@ -120,7 +121,7 @@
>>  struct exynos_tmu_data {
>>         struct exynos_tmu_platform_data *pdata;
>>         struct resource *mem;
>> -       void __iomem *base;
>> +       void __iomem *base, *triminfo_base;
>>         int irq;
>>         enum soc_type soc;
>>         struct work_struct irq_work;
>> @@ -593,8 +594,14 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>>                 __raw_writel(EXYNOS_TRIMINFO_RELOAD,
>>                                 data->base + EXYNOS_TMU_TRIMINFO_CON);
>>         }
>> +
>>         /* Save trimming info in order to perform calibration */
>> -       trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
>> +       if (data->triminfo_base)
>> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
>> +               trim_info = readl(data->triminfo_base);
>> +       else
>> +               trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO);
>> +
>>         data->temp_error1 = trim_info & EXYNOS_TMU_TRIM_TEMP_MASK;
>>         data->temp_error2 = ((trim_info >> 8) & EXYNOS_TMU_TRIM_TEMP_MASK);
>>
>> @@ -941,6 +948,15 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>                 return ret;
>>         }
>>
>> +       /* For Exynos5420 The misplaced TERMINFO register address will be
>> +        * passed from device tree node.
>> +        *
>> +        * We cannot use devm_request_and_ioremap, as the base address
>> +        * over laps with the address space of the other TMU channel.
>> +        * Check Documentation for details
>> +        */
>> +       data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
>> +
>>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>>         if (IS_ERR(data->clk)) {
>>                 dev_err(&pdev->dev, "Failed to get clock\n");
>> @@ -1001,6 +1017,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>
>>         return 0;
>>  err_clk:
>> +       if (data->triminfo_base)
>> +               iounmap(data->triminfo_base);
>> +
>>         platform_set_drvdata(pdev, NULL);
>>         clk_unprepare(data->clk);
>>         return ret;
>> @@ -1014,6 +1033,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>>
>>         exynos_unregister_thermal();
>>
>> +       if (data->triminfo_base)
>> +               iounmap(data->triminfo_base);
>> +
>>         clk_unprepare(data->clk);
>>
>>         platform_set_drvdata(pdev, NULL);
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Shine bright,
(: Nav :)

[PATCH 0/3] thermal: samsung: Add TMU for Exynos5420

[Naveen Krishna Chatradhi]

The below patchset adds the TMU support for Exynos5420
1. correct the fall interrupt en, status bit fields
  Fixes an existing bug in the register field access
2. Add TMU support for Exynos5420 SoCs
  Adds support for Exynos5420. (These changes were tested on a different
  kernel version)
3. Handle the misplaced TRIMINFO register
  Discussion was going on at https://lkml.org/lkml/2013/8/7/59
  Handles the misplaced register on Exynos5420 Only

Naveen Krishna Chatradhi (3):
  thermal: samsung: correct the fall interrupt en, status bit fields
  thermal: samsung: Add TMU support for Exynos5420 SoCs
  thermal: exynos: Handle the misplaced TRIMINFO register

 .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++
 drivers/thermal/samsung/exynos_tmu.c               |   38 ++++++--
 drivers/thermal/samsung/exynos_tmu.h               |    3 +
 drivers/thermal/samsung/exynos_tmu_data.c          |   92 ++++++++++++++++++++
 drivers/thermal/samsung/exynos_tmu_data.h          |   10 ++-
 5 files changed, 158 insertions(+), 6 deletions(-)

-- 
1.7.9.5

[PATCH 1/3] thermal: samsung: correct the fall interrupt en, status bit fields

[Naveen Krishna Chatradhi]

The FALL interrupt related en, status bits are available at an offset of
16 on INTEN, INTSTAT registers and at an offset of
12 on INTCLEAR register.

This patch corrects the same for exyns5250 and exynos5440

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 drivers/thermal/samsung/exynos_tmu.c      |    2 +-
 drivers/thermal/samsung/exynos_tmu.h      |    2 ++
 drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
 drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
 4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index ec01dfe..d201ed8 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -265,7 +265,7 @@ skip_calib_data:
 				data->base + reg->threshold_th1);
 
 		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
-			(reg->inten_fall_mask << reg->inten_fall_shift),
+			(reg->inten_fall_mask << reg->intclr_fall_shift),
 				data->base + reg->tmu_intclear);
 
 		/* if last threshold limit is also present */
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index b364c9e..7c6c34a 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -134,6 +134,7 @@ enum soc_type {
  * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
  * @tmu_intstat: Register containing the interrupt status values.
  * @tmu_intclear: Register for clearing the raised interrupt status.
+ * @intclr_fall_shift: shift bits for interrupt clear fall 0
  * @emul_con: TMU emulation controller register.
  * @emul_temp_shift: shift bits of emulation temperature.
  * @emul_time_shift: shift bits of emulation time.
@@ -204,6 +205,7 @@ struct exynos_tmu_registers {
 	u32	tmu_intstat;
 
 	u32	tmu_intclear;
+	u32	intclr_fall_shift;
 
 	u32	emul_con;
 	u32	emul_temp_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 9002499..23fea23 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
 	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 	.emul_con = EXYNOS_EMUL_CON,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index dc7feb5..8788a87 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -69,9 +69,10 @@
 #define EXYNOS_TMU_RISE_INT_MASK	0x111
 #define EXYNOS_TMU_RISE_INT_SHIFT	0
 #define EXYNOS_TMU_FALL_INT_MASK	0x111
-#define EXYNOS_TMU_FALL_INT_SHIFT	12
+#define EXYNOS_TMU_FALL_INT_SHIFT	16
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
+#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
-- 
1.7.9.5

[PATCH 2/3] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Chatradhi]

This patch adds the neccessary register changes and arch information
to support Exynos5420 SoCs
Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 drivers/thermal/samsung/exynos_tmu.c      |    4 ++
 drivers/thermal/samsung/exynos_tmu.h      |    1 +
 drivers/thermal/samsung/exynos_tmu_data.c |   90 +++++++++++++++++++++++++++++
 drivers/thermal/samsung/exynos_tmu_data.h |    7 +++
 4 files changed, 102 insertions(+)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index d201ed8..bfdfbd6 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -499,6 +499,10 @@ static const struct of_device_id exynos_tmu_match[] = {
 		.compatible = "samsung,exynos5440-tmu",
 		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
 	},
+	{
+		.compatible = "samsung,exynos5420-tmu",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 7c6c34a..d88a536 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -43,6 +43,7 @@ enum soc_type {
 	SOC_ARCH_EXYNOS4210 = 1,
 	SOC_ARCH_EXYNOS,
 	SOC_ARCH_EXYNOS5440,
+	SOC_ARCH_EXYNOS5420,
 };
 
 /**
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 23fea23..5adbb36 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -177,6 +177,96 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+static const struct exynos_tmu_registers exynos5420_tmu_registers = {
+	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+	.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+	.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+	.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+	.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+	.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+	.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+	.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+	.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+	.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+	.tmu_status = EXYNOS_TMU_REG_STATUS,
+	.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
+	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
+	.tmu_inten = EXYNOS_TMU_REG_INTEN,
+	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
+	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+	/* INTEN_RISE3 Not availble in exynos5420 */
+	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
+	.emul_con = EXYNOS_EMUL_CON,
+	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+	.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define EXYNOS5420_TMU_DATA \
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.type = SOC_ARCH_EXYNOS5420, \
+	.registers = &exynos5420_tmu_registers, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME)
+
+struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
+	.tmu_data = {
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+	},
+	.tmu_count = 5,
+};
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index 8788a87..3ce94cd 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -153,4 +153,11 @@ extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
 #define EXYNOS5440_TMU_DRV_DATA (NULL)
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
+#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
+#else
+#define EXYNOS5420_TMU_DRV_DATA (NULL)
+#endif
+
 #endif /*_EXYNOS_TMU_DATA_H*/
-- 
1.7.9.5

[PATCH 3/3] thermal: exynos: Handle the misplaced TRIMINFO register

[Naveen Krishna Chatradhi]

This patch adds code to handle the misplaced TRIMINFO register
incase of Exynos5420.

On Exynos5420 we have a TRIMINFO register being misplaced for
TMU channels 2, 3 and 4

TRIMINFO at 0x1006c000 contains data for TMU channel 3
TRIMINFO at 0x100a0000 contains data for TMU channel 4
TRIMINFO at 0x10068000 contains data for TMU channel 2

The misplaced register address is passed through devicetree and
map it seperately during probe.
Also, adds the documentation under devicetree/bindings/thermal/

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++++++++++
 drivers/thermal/samsung/exynos_tmu.c               |   32 +++++++++++++++++---
 2 files changed, 49 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 284f530..e818473 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -7,12 +7,21 @@
 	       "samsung,exynos4210-tmu"
 	       "samsung,exynos5250-tmu"
 	       "samsung,exynos5440-tmu"
+	       "samsung,exynos5420-tmu"
 - interrupt-parent : The phandle for the interrupt controller
 - reg : Address range of the thermal registers. For soc's which has multiple
 	instances of TMU and some registers are shared across all TMU's like
 	interrupt related then 2 set of register has to supplied. First set
 	belongs	to each instance of TMU and second set belongs to common TMU
 	registers.
+
+ ** NOTE FOR EXYNOS5420 **
+    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
+
+    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
+    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
+    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
+
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
@@ -43,6 +52,18 @@ Example 2):
 		clock-names = "tmu_apbif";
 	};
 
+Example 3): In case of Exynos5420 TMU channel 3
+
+	/* tmu for CPU3 */
+	tmu@1006c000 {
+		compatible = "samsung,exynos5420-tmu";
+		/* 2nd reg is for the misplaced TRIMINFO register */
+		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+		interrupts = <0 185 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
 Note: For multi-instance tmu each instance should have an alias correctly
 numbered in "aliases" node.
 
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index bfdfbd6..f95844e 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -42,6 +42,7 @@
  * @pdata: pointer to the tmu platform/configuration data
  * @base: base address of the single instance of the TMU controller.
  * @base_common: base address of the common registers of the TMU controller.
+ * @triminfo_base: misplaced register base for TRIMINFO on Exynos5420 only
  * @irq: irq number of the TMU controller.
  * @soc: id of the SOC type.
  * @irq_work: pointer to the irq work structure.
@@ -57,6 +58,7 @@ struct exynos_tmu_data {
 	struct exynos_tmu_platform_data *pdata;
 	void __iomem *base;
 	void __iomem *base_common;
+	void __iomem *triminfo_base;		/* Needed only Exynos5420 */
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -186,7 +188,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
 		}
 	} else {
-		trim_info = readl(data->base + reg->triminfo_data);
+		/* On exynos5420 TRIMINFO is misplaced for some channels */
+		if (data->triminfo_base)
+			trim_info = readl(data->triminfo_base +
+						reg->triminfo_data);
+		else
+			trim_info = readl(data->base + reg->triminfo_data);
 	}
 	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
@@ -586,8 +593,17 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 	 * Check if the TMU shares some registers and then try to map the
 	 * memory of common registers.
 	 */
-	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
+	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) {
+		/* For Exynos5420 The misplaced TERMINFO register address will
+		 * be passed from device tree node.
+		 *
+		 * We cannot use devm_request_and_ioremap, as the base address
+		 * over laps with the address space of the other TMU channel.
+		 * Check Documentation for details
+		 */
+		data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
 		return 0;
+	}
 
 	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
 		dev_err(&pdev->dev, "failed to get Resource 1\n");
@@ -632,12 +648,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 	data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
 	if (IS_ERR(data->clk)) {
 		dev_err(&pdev->dev, "Failed to get clock\n");
-		return  PTR_ERR(data->clk);
+		ret = PTR_ERR(data->clk);
+		goto err_triminfo_base;
 	}
 
 	ret = clk_prepare(data->clk);
 	if (ret)
-		return ret;
+		goto err_triminfo_base;
 
 	if (pdata->type == SOC_ARCH_EXYNOS ||
 		pdata->type == SOC_ARCH_EXYNOS4210 ||
@@ -707,9 +724,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 	}
 
 	return 0;
+
 err_clk:
 	clk_unprepare(data->clk);
 	return ret;
+err_triminfo_base:
+	if (data->triminfo_base)
+		iounmap(data->triminfo_base);
 }
 
 static int exynos_tmu_remove(struct platform_device *pdev)
@@ -720,6 +741,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
 
 	exynos_unregister_thermal(data->reg_conf);
 
+	if (data->triminfo_base)
+		iounmap(data->triminfo_base);
+
 	clk_unprepare(data->clk);
 
 	if (!IS_ERR(data->regulator))
-- 
1.7.9.5

Re: [PATCH 1/3] thermal: samsung: correct the fall interrupt en, status bit fields

[amit daniel kachhap]

On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> The FALL interrupt related en, status bits are available at an offset of
> 16 on INTEN, INTSTAT registers and at an offset of
> 12 on INTCLEAR register.
>
> This patch corrects the same for exyns5250 and exynos5440
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
The changes looks fine.
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>

Thanks,
Amit
> ---
>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
>  drivers/thermal/samsung/exynos_tmu.h      |    2 ++
>  drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
>  drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
>  4 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index ec01dfe..d201ed8 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -265,7 +265,7 @@ skip_calib_data:
>                                 data->base + reg->threshold_th1);
>
>                 writel((reg->inten_rise_mask << reg->inten_rise_shift) |
> -                       (reg->inten_fall_mask << reg->inten_fall_shift),
> +                       (reg->inten_fall_mask << reg->intclr_fall_shift),
>                                 data->base + reg->tmu_intclear);
>
>                 /* if last threshold limit is also present */
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index b364c9e..7c6c34a 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -134,6 +134,7 @@ enum soc_type {
>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
>   * @tmu_intstat: Register containing the interrupt status values.
>   * @tmu_intclear: Register for clearing the raised interrupt status.
> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
>   * @emul_con: TMU emulation controller register.
>   * @emul_temp_shift: shift bits of emulation temperature.
>   * @emul_time_shift: shift bits of emulation time.
> @@ -204,6 +205,7 @@ struct exynos_tmu_registers {
>         u32     tmu_intstat;
>
>         u32     tmu_intclear;
> +       u32     intclr_fall_shift;
>
>         u32     emul_con;
>         u32     emul_temp_shift;
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 9002499..23fea23 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
>         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +       .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>         .emul_con = EXYNOS_EMUL_CON,
>         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> @@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
>         .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
>         .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
> +       .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>         .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
>         .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
>         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> index dc7feb5..8788a87 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> @@ -69,9 +69,10 @@
>  #define EXYNOS_TMU_RISE_INT_MASK       0x111
>  #define EXYNOS_TMU_RISE_INT_SHIFT      0
>  #define EXYNOS_TMU_FALL_INT_MASK       0x111
> -#define EXYNOS_TMU_FALL_INT_SHIFT      12
> +#define EXYNOS_TMU_FALL_INT_SHIFT      16
>  #define EXYNOS_TMU_CLEAR_RISE_INT      0x111
>  #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 12)
> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT        12
>  #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
>  #define EXYNOS_TMU_TRIP_MODE_MASK      0x7
>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> The FALL interrupt related en, status bits are available at an offset of
> 16 on INTEN, INTSTAT registers and at an offset of
> 12 on INTCLEAR register.
>
> This patch corrects the same for exyns5250 and exynos5440
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
>  drivers/thermal/samsung/exynos_tmu.h      |    2 ++
>  drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
>  drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
>  4 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index ec01dfe..d201ed8 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -265,7 +265,7 @@ skip_calib_data:
>                                 data->base + reg->threshold_th1);
>
>                 writel((reg->inten_rise_mask << reg->inten_rise_shift) |
> -                       (reg->inten_fall_mask << reg->inten_fall_shift),
> +                       (reg->inten_fall_mask << reg->intclr_fall_shift),
>                                 data->base + reg->tmu_intclear);
>
>                 /* if last threshold limit is also present */
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index b364c9e..7c6c34a 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -134,6 +134,7 @@ enum soc_type {
>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
>   * @tmu_intstat: Register containing the interrupt status values.
>   * @tmu_intclear: Register for clearing the raised interrupt status.
> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
>   * @emul_con: TMU emulation controller register.
>   * @emul_temp_shift: shift bits of emulation temperature.
>   * @emul_time_shift: shift bits of emulation time.
> @@ -204,6 +205,7 @@ struct exynos_tmu_registers {
>         u32     tmu_intstat;
>
>         u32     tmu_intclear;
> +       u32     intclr_fall_shift;
>
>         u32     emul_con;
>         u32     emul_temp_shift;
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 9002499..23fea23 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
>         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +       .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>         .emul_con = EXYNOS_EMUL_CON,
>         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> @@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
>         .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
>         .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
> +       .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>         .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
>         .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
>         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> index dc7feb5..8788a87 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> @@ -69,9 +69,10 @@
>  #define EXYNOS_TMU_RISE_INT_MASK       0x111
>  #define EXYNOS_TMU_RISE_INT_SHIFT      0
>  #define EXYNOS_TMU_FALL_INT_MASK       0x111
> -#define EXYNOS_TMU_FALL_INT_SHIFT      12
> +#define EXYNOS_TMU_FALL_INT_SHIFT      16
>  #define EXYNOS_TMU_CLEAR_RISE_INT      0x111
>  #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 12)
> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT        12
>  #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
>  #define EXYNOS_TMU_TRIP_MODE_MASK      0x7
>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 2/3] thermal: samsung: Add TMU support for Exynos5420 SoCs

[amit daniel kachhap]

On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> This patch adds the neccessary register changes and arch information
> to support Exynos5420 SoCs
> Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>

Thanks,
Amit
> ---
>  drivers/thermal/samsung/exynos_tmu.c      |    4 ++
>  drivers/thermal/samsung/exynos_tmu.h      |    1 +
>  drivers/thermal/samsung/exynos_tmu_data.c |   90 +++++++++++++++++++++++++++++
>  drivers/thermal/samsung/exynos_tmu_data.h |    7 +++
>  4 files changed, 102 insertions(+)
>
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index d201ed8..bfdfbd6 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -499,6 +499,10 @@ static const struct of_device_id exynos_tmu_match[] = {
>                 .compatible = "samsung,exynos5440-tmu",
>                 .data = (void *)EXYNOS5440_TMU_DRV_DATA,
>         },
> +       {
> +               .compatible = "samsung,exynos5420-tmu",
> +               .data = (void *)EXYNOS5420_TMU_DRV_DATA,
> +       },
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, exynos_tmu_match);
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 7c6c34a..d88a536 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -43,6 +43,7 @@ enum soc_type {
>         SOC_ARCH_EXYNOS4210 = 1,
>         SOC_ARCH_EXYNOS,
>         SOC_ARCH_EXYNOS5440,
> +       SOC_ARCH_EXYNOS5420,
>  };
>
>  /**
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 23fea23..5adbb36 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -177,6 +177,96 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
>  };
>  #endif
>
> +#if defined(CONFIG_SOC_EXYNOS5420)
> +static const struct exynos_tmu_registers exynos5420_tmu_registers = {
> +       .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
> +       .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
> +       .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
> +       .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
> +       .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
> +       .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
> +       .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
> +       .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
> +       .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
> +       .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
> +       .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
> +       .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
> +       .tmu_status = EXYNOS_TMU_REG_STATUS,
> +       .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
> +       .threshold_th0 = EXYNOS_THD_TEMP_RISE,
> +       .threshold_th1 = EXYNOS_THD_TEMP_FALL,
> +       .tmu_inten = EXYNOS_TMU_REG_INTEN,
> +       .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> +       .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> +       .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
> +       .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
> +       .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
> +       .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
> +       .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
> +       /* INTEN_RISE3 Not availble in exynos5420 */
> +       .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
> +       .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
> +       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
> +       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +       .intclr_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
> +       .emul_con = EXYNOS_EMUL_CON,
> +       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> +       .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> +       .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
> +};
> +
> +#define EXYNOS5420_TMU_DATA \
> +       .threshold_falling = 10, \
> +       .trigger_levels[0] = 85, \
> +       .trigger_levels[1] = 103, \
> +       .trigger_levels[2] = 110, \
> +       .trigger_levels[3] = 120, \
> +       .trigger_enable[0] = true, \
> +       .trigger_enable[1] = true, \
> +       .trigger_enable[2] = true, \
> +       .trigger_enable[3] = false, \
> +       .trigger_type[0] = THROTTLE_ACTIVE, \
> +       .trigger_type[1] = THROTTLE_ACTIVE, \
> +       .trigger_type[2] = SW_TRIP, \
> +       .trigger_type[3] = HW_TRIP, \
> +       .max_trigger_level = 4, \
> +       .gain = 8, \
> +       .reference_voltage = 16, \
> +       .noise_cancel_mode = 4, \
> +       .cal_type = TYPE_ONE_POINT_TRIMMING, \
> +       .efuse_value = 55, \
> +       .min_efuse_value = 40, \
> +       .max_efuse_value = 100, \
> +       .first_point_trim = 25, \
> +       .second_point_trim = 85, \
> +       .default_temp_offset = 50, \
> +       .freq_tab[0] = { \
> +               .freq_clip_max = 800 * 1000, \
> +               .temp_level = 85, \
> +       }, \
> +       .freq_tab[1] = { \
> +               .freq_clip_max = 200 * 1000, \
> +               .temp_level = 103, \
> +       }, \
> +       .freq_tab_count = 2, \
> +       .type = SOC_ARCH_EXYNOS5420, \
> +       .registers = &exynos5420_tmu_registers, \
> +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +                       TMU_SUPPORT_EMUL_TIME)
> +
> +struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
> +       .tmu_data = {
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA },
> +       },
> +       .tmu_count = 5,
> +};
> +#endif
> +
>  #if defined(CONFIG_SOC_EXYNOS5440)
>  static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> index 8788a87..3ce94cd 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> @@ -153,4 +153,11 @@ extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
>  #define EXYNOS5440_TMU_DRV_DATA (NULL)
>  #endif
>
> +#if defined(CONFIG_SOC_EXYNOS5420)
> +extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
> +#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
> +#else
> +#define EXYNOS5420_TMU_DRV_DATA (NULL)
> +#endif
> +
>  #endif /*_EXYNOS_TMU_DATA_H*/
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 3/3] thermal: exynos: Handle the misplaced TRIMINFO register

[amit daniel kachhap]

Hi Naveen

On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> This patch adds code to handle the misplaced TRIMINFO register
> incase of Exynos5420.
>
> On Exynos5420 we have a TRIMINFO register being misplaced for
> TMU channels 2, 3 and 4
>
> TRIMINFO at 0x1006c000 contains data for TMU channel 3
> TRIMINFO at 0x100a0000 contains data for TMU channel 4
> TRIMINFO at 0x10068000 contains data for TMU channel 2
>
> The misplaced register address is passed through devicetree and
> map it seperately during probe.
> Also, adds the documentation under devicetree/bindings/thermal/
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++++++++++
>  drivers/thermal/samsung/exynos_tmu.c               |   32 +++++++++++++++++---
>  2 files changed, 49 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 284f530..e818473 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -7,12 +7,21 @@
>                "samsung,exynos4210-tmu"
>                "samsung,exynos5250-tmu"
>                "samsung,exynos5440-tmu"
> +              "samsung,exynos5420-tmu"
>  - interrupt-parent : The phandle for the interrupt controller
>  - reg : Address range of the thermal registers. For soc's which has multiple
>         instances of TMU and some registers are shared across all TMU's like
>         interrupt related then 2 set of register has to supplied. First set
>         belongs to each instance of TMU and second set belongs to common TMU
>         registers.
> +
> + ** NOTE FOR EXYNOS5420 **
> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
> +
> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
> +
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> @@ -43,6 +52,18 @@ Example 2):
>                 clock-names = "tmu_apbif";
>         };
>
> +Example 3): In case of Exynos5420 TMU channel 3
> +
> +       /* tmu for CPU3 */
> +       tmu@1006c000 {
> +               compatible = "samsung,exynos5420-tmu";
> +               /* 2nd reg is for the misplaced TRIMINFO register */
> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
> +               interrupts = <0 185 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif";
> +       };
> +
>  Note: For multi-instance tmu each instance should have an alias correctly
>  numbered in "aliases" node.
>
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index bfdfbd6..f95844e 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -42,6 +42,7 @@
>   * @pdata: pointer to the tmu platform/configuration data
>   * @base: base address of the single instance of the TMU controller.
>   * @base_common: base address of the common registers of the TMU controller.
> + * @triminfo_base: misplaced register base for TRIMINFO on Exynos5420 only

Instead of creating this new field you can re-use base_common for
accessing the second set of register for misplaced triminfo address.
Also you can rename this variable as base_second.

>   * @irq: irq number of the TMU controller.
>   * @soc: id of the SOC type.
>   * @irq_work: pointer to the irq work structure.
> @@ -57,6 +58,7 @@ struct exynos_tmu_data {
>         struct exynos_tmu_platform_data *pdata;
>         void __iomem *base;
>         void __iomem *base_common;
> +       void __iomem *triminfo_base;            /* Needed only Exynos5420 */
>         int irq;
>         enum soc_type soc;
>         struct work_struct irq_work;
> @@ -186,7 +188,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>                 }
>         } else {
> -               trim_info = readl(data->base + reg->triminfo_data);
> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
> +               if (data->triminfo_base)
> +                       trim_info = readl(data->triminfo_base +
> +                                               reg->triminfo_data);
> +               else
> +                       trim_info = readl(data->base + reg->triminfo_data);
>         }
>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
> @@ -586,8 +593,17 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>          * Check if the TMU shares some registers and then try to map the
>          * memory of common registers.
>          */
> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
> +       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) {
> +               /* For Exynos5420 The misplaced TERMINFO register address will
> +                * be passed from device tree node.
> +                *
> +                * We cannot use devm_request_and_ioremap, as the base address
> +                * over laps with the address space of the other TMU channel.
> +                * Check Documentation for details
> +                */
> +               data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
>                 return 0;
> +       }
In the below code, remove the request resource API for common_base and
use simple of_iomap API.

Thanks,
Amit Daniel
>
>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
>                 dev_err(&pdev->dev, "failed to get Resource 1\n");
> @@ -632,12 +648,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>         if (IS_ERR(data->clk)) {
>                 dev_err(&pdev->dev, "Failed to get clock\n");
> -               return  PTR_ERR(data->clk);
> +               ret = PTR_ERR(data->clk);
> +               goto err_triminfo_base;
>         }
>
>         ret = clk_prepare(data->clk);
>         if (ret)
> -               return ret;
> +               goto err_triminfo_base;
>
>         if (pdata->type == SOC_ARCH_EXYNOS ||
>                 pdata->type == SOC_ARCH_EXYNOS4210 ||
> @@ -707,9 +724,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>         }
>
>         return 0;
> +
>  err_clk:
>         clk_unprepare(data->clk);
>         return ret;
> +err_triminfo_base:
> +       if (data->triminfo_base)
> +               iounmap(data->triminfo_base);
>  }
>
>  static int exynos_tmu_remove(struct platform_device *pdev)
> @@ -720,6 +741,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>
>         exynos_unregister_thermal(data->reg_conf);
>
> +       if (data->triminfo_base)
> +               iounmap(data->triminfo_base);
> +
>         clk_unprepare(data->clk);
>
>         if (!IS_ERR(data->regulator))
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 3/3] thermal: exynos: Handle the misplaced TRIMINFO register

[Naveen Krishna Ch]

On 28 August 2013 11:33, amit daniel kachhap <amit.daniel@samsung.com> wrote:
> Hi Naveen
>
> On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
> <ch.naveen@samsung.com> wrote:
>> This patch adds code to handle the misplaced TRIMINFO register
>> incase of Exynos5420.
>>
>> On Exynos5420 we have a TRIMINFO register being misplaced for
>> TMU channels 2, 3 and 4
>>
>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>> TRIMINFO at 0x10068000 contains data for TMU channel 2
>>
>> The misplaced register address is passed through devicetree and
>> map it seperately during probe.
>> Also, adds the documentation under devicetree/bindings/thermal/
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> ---
>>  .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++++++++++
>>  drivers/thermal/samsung/exynos_tmu.c               |   32 +++++++++++++++++---
>>  2 files changed, 49 insertions(+), 4 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> index 284f530..e818473 100644
>> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> @@ -7,12 +7,21 @@
>>                "samsung,exynos4210-tmu"
>>                "samsung,exynos5250-tmu"
>>                "samsung,exynos5440-tmu"
>> +              "samsung,exynos5420-tmu"
>>  - interrupt-parent : The phandle for the interrupt controller
>>  - reg : Address range of the thermal registers. For soc's which has multiple
>>         instances of TMU and some registers are shared across all TMU's like
>>         interrupt related then 2 set of register has to supplied. First set
>>         belongs to each instance of TMU and second set belongs to common TMU
>>         registers.
>> +
>> + ** NOTE FOR EXYNOS5420 **
>> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
>> +
>> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
>> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
>> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
>> +
>>  - interrupts : Should contain interrupt for thermal system
>>  - clocks : The main clock for TMU device
>>  - clock-names : Thermal system clock name
>> @@ -43,6 +52,18 @@ Example 2):
>>                 clock-names = "tmu_apbif";
>>         };
>>
>> +Example 3): In case of Exynos5420 TMU channel 3
>> +
>> +       /* tmu for CPU3 */
>> +       tmu@1006c000 {
>> +               compatible = "samsung,exynos5420-tmu";
>> +               /* 2nd reg is for the misplaced TRIMINFO register */
>> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>> +               interrupts = <0 185 0>;
>> +               clocks = <&clock 318>;
>> +               clock-names = "tmu_apbif";
>> +       };
>> +
>>  Note: For multi-instance tmu each instance should have an alias correctly
>>  numbered in "aliases" node.
>>
>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>> index bfdfbd6..f95844e 100644
>> --- a/drivers/thermal/samsung/exynos_tmu.c
>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>> @@ -42,6 +42,7 @@
>>   * @pdata: pointer to the tmu platform/configuration data
>>   * @base: base address of the single instance of the TMU controller.
>>   * @base_common: base address of the common registers of the TMU controller.
>> + * @triminfo_base: misplaced register base for TRIMINFO on Exynos5420 only
>
> Instead of creating this new field you can re-use base_common for
> accessing the second set of register for misplaced triminfo address.
> Also you can rename this variable as base_second.

The purpose and the meaning of the fields are entirely different.
The triminfo is a hardware bug present only in Exynos5420
and the common registers are available only on Exynos5440 i guess.

IMHO, reusing is not a nice idea.
I'm willing to modify the code if there is a better idea.
>
>>   * @irq: irq number of the TMU controller.
>>   * @soc: id of the SOC type.
>>   * @irq_work: pointer to the irq work structure.
>> @@ -57,6 +58,7 @@ struct exynos_tmu_data {
>>         struct exynos_tmu_platform_data *pdata;
>>         void __iomem *base;
>>         void __iomem *base_common;
>> +       void __iomem *triminfo_base;            /* Needed only Exynos5420 */
>>         int irq;
>>         enum soc_type soc;
>>         struct work_struct irq_work;
>> @@ -186,7 +188,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>>                 }
>>         } else {
>> -               trim_info = readl(data->base + reg->triminfo_data);
>> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
>> +               if (data->triminfo_base)
>> +                       trim_info = readl(data->triminfo_base +
>> +                                               reg->triminfo_data);
>> +               else
>> +                       trim_info = readl(data->base + reg->triminfo_data);
>>         }
>>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
>> @@ -586,8 +593,17 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>>          * Check if the TMU shares some registers and then try to map the
>>          * memory of common registers.
>>          */
>> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
>> +       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) {
>> +               /* For Exynos5420 The misplaced TERMINFO register address will
>> +                * be passed from device tree node.
>> +                *
>> +                * We cannot use devm_request_and_ioremap, as the base address
>> +                * over laps with the address space of the other TMU channel.
>> +                * Check Documentation for details
>> +                */
>> +               data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
>>                 return 0;
>> +       }
> In the below code, remove the request resource API for common_base and
> use simple of_iomap API.

That will be a separate fix patch. Will submit separately,
This patchset is to add exynos5420 support

Is the res_size for the common registers fixed ?

>
> Thanks,
> Amit Daniel
>>
>>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
>>                 dev_err(&pdev->dev, "failed to get Resource 1\n");
>> @@ -632,12 +648,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>>         if (IS_ERR(data->clk)) {
>>                 dev_err(&pdev->dev, "Failed to get clock\n");
>> -               return  PTR_ERR(data->clk);
>> +               ret = PTR_ERR(data->clk);
>> +               goto err_triminfo_base;
>>         }
>>
>>         ret = clk_prepare(data->clk);
>>         if (ret)
>> -               return ret;
>> +               goto err_triminfo_base;
>>
>>         if (pdata->type == SOC_ARCH_EXYNOS ||
>>                 pdata->type == SOC_ARCH_EXYNOS4210 ||
>> @@ -707,9 +724,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>         }
>>
>>         return 0;
>> +
>>  err_clk:
>>         clk_unprepare(data->clk);
>>         return ret;
>> +err_triminfo_base:
>> +       if (data->triminfo_base)
>> +               iounmap(data->triminfo_base);
>>  }
>>
>>  static int exynos_tmu_remove(struct platform_device *pdev)
>> @@ -720,6 +741,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>>
>>         exynos_unregister_thermal(data->reg_conf);
>>
>> +       if (data->triminfo_base)
>> +               iounmap(data->triminfo_base);
>> +
>>         clk_unprepare(data->clk);
>>
>>         if (!IS_ERR(data->regulator))
>> --
>> 1.7.9.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>> Please read the FAQ at  http://www.tux.org/lkml/



-- 
Shine bright,
(: Nav :)

Re: [PATCH 3/3] thermal: exynos: Handle the misplaced TRIMINFO register

[amit daniel kachhap]

Hi Naveen,

On Wed, Aug 28, 2013 at 11:49 AM, Naveen Krishna Ch
<naveenkrishna.ch@gmail.com> wrote:
> On 28 August 2013 11:33, amit daniel kachhap <amit.daniel@samsung.com> wrote:
>> Hi Naveen
>>
>> On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
>> <ch.naveen@samsung.com> wrote:
>>> This patch adds code to handle the misplaced TRIMINFO register
>>> incase of Exynos5420.
>>>
>>> On Exynos5420 we have a TRIMINFO register being misplaced for
>>> TMU channels 2, 3 and 4
>>>
>>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>>> TRIMINFO at 0x10068000 contains data for TMU channel 2
>>>
>>> The misplaced register address is passed through devicetree and
>>> map it seperately during probe.
>>> Also, adds the documentation under devicetree/bindings/thermal/
>>>
>>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>>> ---
>>>  .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++++++++++
>>>  drivers/thermal/samsung/exynos_tmu.c               |   32 +++++++++++++++++---
>>>  2 files changed, 49 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>> index 284f530..e818473 100644
>>> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>> @@ -7,12 +7,21 @@
>>>                "samsung,exynos4210-tmu"
>>>                "samsung,exynos5250-tmu"
>>>                "samsung,exynos5440-tmu"
>>> +              "samsung,exynos5420-tmu"
>>>  - interrupt-parent : The phandle for the interrupt controller
>>>  - reg : Address range of the thermal registers. For soc's which has multiple
>>>         instances of TMU and some registers are shared across all TMU's like
>>>         interrupt related then 2 set of register has to supplied. First set
>>>         belongs to each instance of TMU and second set belongs to common TMU
>>>         registers.
>>> +
>>> + ** NOTE FOR EXYNOS5420 **
>>> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
>>> +
>>> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
>>> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
>>> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
>>> +
>>>  - interrupts : Should contain interrupt for thermal system
>>>  - clocks : The main clock for TMU device
>>>  - clock-names : Thermal system clock name
>>> @@ -43,6 +52,18 @@ Example 2):
>>>                 clock-names = "tmu_apbif";
>>>         };
>>>
>>> +Example 3): In case of Exynos5420 TMU channel 3
>>> +
>>> +       /* tmu for CPU3 */
>>> +       tmu@1006c000 {
>>> +               compatible = "samsung,exynos5420-tmu";
>>> +               /* 2nd reg is for the misplaced TRIMINFO register */
>>> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>>> +               interrupts = <0 185 0>;
>>> +               clocks = <&clock 318>;
>>> +               clock-names = "tmu_apbif";
>>> +       };
>>> +
>>>  Note: For multi-instance tmu each instance should have an alias correctly
>>>  numbered in "aliases" node.
>>>
>>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>>> index bfdfbd6..f95844e 100644
>>> --- a/drivers/thermal/samsung/exynos_tmu.c
>>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>>> @@ -42,6 +42,7 @@
>>>   * @pdata: pointer to the tmu platform/configuration data
>>>   * @base: base address of the single instance of the TMU controller.
>>>   * @base_common: base address of the common registers of the TMU controller.
>>> + * @triminfo_base: misplaced register base for TRIMINFO on Exynos5420 only
>>
>> Instead of creating this new field you can re-use base_common for
>> accessing the second set of register for misplaced triminfo address.
>> Also you can rename this variable as base_second.
>
> The purpose and the meaning of the fields are entirely different.
> The triminfo is a hardware bug present only in Exynos5420
My point is that for a bug a new field does not seem good as driver is
common across many Socs. Even In case of 5440 the common base can be
generalized and considered as second base address and documentation
can be updated accordingly. Also change the flag SHARED_MEMORY to
ADDRESS_TWO.
> and the common registers are available only on Exynos5440 i guess.
>
> IMHO, reusing is not a nice idea.
> I'm willing to modify the code if there is a better idea.
>>
>>>   * @irq: irq number of the TMU controller.
>>>   * @soc: id of the SOC type.
>>>   * @irq_work: pointer to the irq work structure.
>>> @@ -57,6 +58,7 @@ struct exynos_tmu_data {
>>>         struct exynos_tmu_platform_data *pdata;
>>>         void __iomem *base;
>>>         void __iomem *base_common;
>>> +       void __iomem *triminfo_base;            /* Needed only Exynos5420 */
>>>         int irq;
>>>         enum soc_type soc;
>>>         struct work_struct irq_work;
>>> @@ -186,7 +188,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>>>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>>>                 }
>>>         } else {
>>> -               trim_info = readl(data->base + reg->triminfo_data);
>>> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
>>> +               if (data->triminfo_base)
>>> +                       trim_info = readl(data->triminfo_base +
>>> +                                               reg->triminfo_data);
>>> +               else
>>> +                       trim_info = readl(data->base + reg->triminfo_data);
>>>         }
>>>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>>>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
>>> @@ -586,8 +593,17 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>>>          * Check if the TMU shares some registers and then try to map the
>>>          * memory of common registers.
>>>          */
>>> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
>>> +       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) {
>>> +               /* For Exynos5420 The misplaced TERMINFO register address will
>>> +                * be passed from device tree node.
>>> +                *
>>> +                * We cannot use devm_request_and_ioremap, as the base address
>>> +                * over laps with the address space of the other TMU channel.
>>> +                * Check Documentation for details
>>> +                */
>>> +               data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
>>>                 return 0;
>>> +       }
>> In the below code, remove the request resource API for common_base and
>> use simple of_iomap API.
>
> That will be a separate fix patch. Will submit separately,
> This patchset is to add exynos5420 support

Sorry for my earlier comment. Actually my suggested change is not
needed as the APIs used don't bind resources. Just enable the
SHARED_MEMORY flag and it should be fine.


>
> Is the res_size for the common registers fixed ?
Yes in 5440 it is same.

Thanks,
Amit Daniel

>
>>
>> Thanks,
>> Amit Daniel
>>>
>>>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
>>>                 dev_err(&pdev->dev, "failed to get Resource 1\n");
>>> @@ -632,12 +648,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>>>         if (IS_ERR(data->clk)) {
>>>                 dev_err(&pdev->dev, "Failed to get clock\n");
>>> -               return  PTR_ERR(data->clk);
>>> +               ret = PTR_ERR(data->clk);
>>> +               goto err_triminfo_base;
>>>         }
>>>
>>>         ret = clk_prepare(data->clk);
>>>         if (ret)
>>> -               return ret;
>>> +               goto err_triminfo_base;
>>>
>>>         if (pdata->type == SOC_ARCH_EXYNOS ||
>>>                 pdata->type == SOC_ARCH_EXYNOS4210 ||
>>> @@ -707,9 +724,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>         }
>>>
>>>         return 0;
>>> +
>>>  err_clk:
>>>         clk_unprepare(data->clk);
>>>         return ret;
>>> +err_triminfo_base:
>>> +       if (data->triminfo_base)
>>> +               iounmap(data->triminfo_base);
>>>  }
>>>
>>>  static int exynos_tmu_remove(struct platform_device *pdev)
>>> @@ -720,6 +741,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>>>
>>>         exynos_unregister_thermal(data->reg_conf);
>>>
>>> +       if (data->triminfo_base)
>>> +               iounmap(data->triminfo_base);
>>> +
>>>         clk_unprepare(data->clk);
>>>
>>>         if (!IS_ERR(data->regulator))
>>> --
>>> 1.7.9.5
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>> Please read the FAQ at  http://www.tux.org/lkml/
>
>
>
> --
> Shine bright,
> (: Nav :)
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

On Wed, Aug 28, 2013 at 11:49 AM, Naveen Krishna Ch
<naveenkrishna.ch@gmail.com> wrote:
> On 28 August 2013 11:33, amit daniel kachhap <amit.daniel@samsung.com> wrote:
>> Hi Naveen
>>
>> On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
>> <ch.naveen@samsung.com> wrote:
>>> This patch adds code to handle the misplaced TRIMINFO register
>>> incase of Exynos5420.
>>>
>>> On Exynos5420 we have a TRIMINFO register being misplaced for
>>> TMU channels 2, 3 and 4
>>>
>>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>>> TRIMINFO at 0x10068000 contains data for TMU channel 2
>>>
>>> The misplaced register address is passed through devicetree and
>>> map it seperately during probe.
>>> Also, adds the documentation under devicetree/bindings/thermal/
>>>
>>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>>> ---
>>>  .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++++++++++
>>>  drivers/thermal/samsung/exynos_tmu.c               |   32 +++++++++++++++++---
>>>  2 files changed, 49 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>> index 284f530..e818473 100644
>>> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>> @@ -7,12 +7,21 @@
>>>                "samsung,exynos4210-tmu"
>>>                "samsung,exynos5250-tmu"
>>>                "samsung,exynos5440-tmu"
>>> +              "samsung,exynos5420-tmu"
>>>  - interrupt-parent : The phandle for the interrupt controller
>>>  - reg : Address range of the thermal registers. For soc's which has multiple
>>>         instances of TMU and some registers are shared across all TMU's like
>>>         interrupt related then 2 set of register has to supplied. First set
>>>         belongs to each instance of TMU and second set belongs to common TMU
>>>         registers.
>>> +
>>> + ** NOTE FOR EXYNOS5420 **
>>> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
>>> +
>>> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
>>> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
>>> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
>>> +
>>>  - interrupts : Should contain interrupt for thermal system
>>>  - clocks : The main clock for TMU device
>>>  - clock-names : Thermal system clock name
>>> @@ -43,6 +52,18 @@ Example 2):
>>>                 clock-names = "tmu_apbif";
>>>         };
>>>
>>> +Example 3): In case of Exynos5420 TMU channel 3
>>> +
>>> +       /* tmu for CPU3 */
>>> +       tmu@1006c000 {
>>> +               compatible = "samsung,exynos5420-tmu";
>>> +               /* 2nd reg is for the misplaced TRIMINFO register */
>>> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>>> +               interrupts = <0 185 0>;
>>> +               clocks = <&clock 318>;
>>> +               clock-names = "tmu_apbif";
>>> +       };
>>> +
>>>  Note: For multi-instance tmu each instance should have an alias correctly
>>>  numbered in "aliases" node.
>>>
>>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>>> index bfdfbd6..f95844e 100644
>>> --- a/drivers/thermal/samsung/exynos_tmu.c
>>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>>> @@ -42,6 +42,7 @@
>>>   * @pdata: pointer to the tmu platform/configuration data
>>>   * @base: base address of the single instance of the TMU controller.
>>>   * @base_common: base address of the common registers of the TMU controller.
>>> + * @triminfo_base: misplaced register base for TRIMINFO on Exynos5420 only
>>
>> Instead of creating this new field you can re-use base_common for
>> accessing the second set of register for misplaced triminfo address.
>> Also you can rename this variable as base_second.
>
> The purpose and the meaning of the fields are entirely different.
> The triminfo is a hardware bug present only in Exynos5420
> and the common registers are available only on Exynos5440 i guess.
>
> IMHO, reusing is not a nice idea.
> I'm willing to modify the code if there is a better idea.
>>
>>>   * @irq: irq number of the TMU controller.
>>>   * @soc: id of the SOC type.
>>>   * @irq_work: pointer to the irq work structure.
>>> @@ -57,6 +58,7 @@ struct exynos_tmu_data {
>>>         struct exynos_tmu_platform_data *pdata;
>>>         void __iomem *base;
>>>         void __iomem *base_common;
>>> +       void __iomem *triminfo_base;            /* Needed only Exynos5420 */
>>>         int irq;
>>>         enum soc_type soc;
>>>         struct work_struct irq_work;
>>> @@ -186,7 +188,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>>>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>>>                 }
>>>         } else {
>>> -               trim_info = readl(data->base + reg->triminfo_data);
>>> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
>>> +               if (data->triminfo_base)
>>> +                       trim_info = readl(data->triminfo_base +
>>> +                                               reg->triminfo_data);
>>> +               else
>>> +                       trim_info = readl(data->base + reg->triminfo_data);
>>>         }
>>>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>>>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
>>> @@ -586,8 +593,17 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>>>          * Check if the TMU shares some registers and then try to map the
>>>          * memory of common registers.
>>>          */
>>> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
>>> +       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) {
>>> +               /* For Exynos5420 The misplaced TERMINFO register address will
>>> +                * be passed from device tree node.
>>> +                *
>>> +                * We cannot use devm_request_and_ioremap, as the base address
>>> +                * over laps with the address space of the other TMU channel.
>>> +                * Check Documentation for details
>>> +                */
>>> +               data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
>>>                 return 0;
>>> +       }
>> In the below code, remove the request resource API for common_base and
>> use simple of_iomap API.
>
> That will be a separate fix patch. Will submit separately,
> This patchset is to add exynos5420 support
>
> Is the res_size for the common registers fixed ?
>
>>
>> Thanks,
>> Amit Daniel
>>>
>>>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
>>>                 dev_err(&pdev->dev, "failed to get Resource 1\n");
>>> @@ -632,12 +648,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>>>         if (IS_ERR(data->clk)) {
>>>                 dev_err(&pdev->dev, "Failed to get clock\n");
>>> -               return  PTR_ERR(data->clk);
>>> +               ret = PTR_ERR(data->clk);
>>> +               goto err_triminfo_base;
>>>         }
>>>
>>>         ret = clk_prepare(data->clk);
>>>         if (ret)
>>> -               return ret;
>>> +               goto err_triminfo_base;
>>>
>>>         if (pdata->type == SOC_ARCH_EXYNOS ||
>>>                 pdata->type == SOC_ARCH_EXYNOS4210 ||
>>> @@ -707,9 +724,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>         }
>>>
>>>         return 0;
>>> +
>>>  err_clk:
>>>         clk_unprepare(data->clk);
>>>         return ret;
>>> +err_triminfo_base:
>>> +       if (data->triminfo_base)
>>> +               iounmap(data->triminfo_base);
>>>  }
>>>
>>>  static int exynos_tmu_remove(struct platform_device *pdev)
>>> @@ -720,6 +741,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>>>
>>>         exynos_unregister_thermal(data->reg_conf);
>>>
>>> +       if (data->triminfo_base)
>>> +               iounmap(data->triminfo_base);
>>> +
>>>         clk_unprepare(data->clk);
>>>
>>>         if (!IS_ERR(data->regulator))
>>> --
>>> 1.7.9.5
>>>
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>> Please read the FAQ at  http://www.tux.org/lkml/
>
>
>
> --
> Shine bright,
> (: Nav :)
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 3/3] thermal: exynos: Handle the misplaced TRIMINFO register

[Naveen Krishna Ch]

On 28 August 2013 14:13, amit daniel kachhap <amit.daniel@samsung.com> wrote:
> Hi Naveen,
>
> On Wed, Aug 28, 2013 at 11:49 AM, Naveen Krishna Ch
> <naveenkrishna.ch@gmail.com> wrote:
>> On 28 August 2013 11:33, amit daniel kachhap <amit.daniel@samsung.com> wrote:
>>> Hi Naveen
>>>
>>> On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
>>> <ch.naveen@samsung.com> wrote:
>>>> This patch adds code to handle the misplaced TRIMINFO register
>>>> incase of Exynos5420.
>>>>
>>>> On Exynos5420 we have a TRIMINFO register being misplaced for
>>>> TMU channels 2, 3 and 4
>>>>
>>>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>>>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>>>> TRIMINFO at 0x10068000 contains data for TMU channel 2
>>>>
>>>> The misplaced register address is passed through devicetree and
>>>> map it seperately during probe.
>>>> Also, adds the documentation under devicetree/bindings/thermal/
>>>>
>>>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>>>> ---
>>>>  .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++++++++++
>>>>  drivers/thermal/samsung/exynos_tmu.c               |   32 +++++++++++++++++---
>>>>  2 files changed, 49 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>> index 284f530..e818473 100644
>>>> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>> @@ -7,12 +7,21 @@
>>>>                "samsung,exynos4210-tmu"
>>>>                "samsung,exynos5250-tmu"
>>>>                "samsung,exynos5440-tmu"
>>>> +              "samsung,exynos5420-tmu"
>>>>  - interrupt-parent : The phandle for the interrupt controller
>>>>  - reg : Address range of the thermal registers. For soc's which has multiple
>>>>         instances of TMU and some registers are shared across all TMU's like
>>>>         interrupt related then 2 set of register has to supplied. First set
>>>>         belongs to each instance of TMU and second set belongs to common TMU
>>>>         registers.
>>>> +
>>>> + ** NOTE FOR EXYNOS5420 **
>>>> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
>>>> +
>>>> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
>>>> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
>>>> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
>>>> +
>>>>  - interrupts : Should contain interrupt for thermal system
>>>>  - clocks : The main clock for TMU device
>>>>  - clock-names : Thermal system clock name
>>>> @@ -43,6 +52,18 @@ Example 2):
>>>>                 clock-names = "tmu_apbif";
>>>>         };
>>>>
>>>> +Example 3): In case of Exynos5420 TMU channel 3
>>>> +
>>>> +       /* tmu for CPU3 */
>>>> +       tmu@1006c000 {
>>>> +               compatible = "samsung,exynos5420-tmu";
>>>> +               /* 2nd reg is for the misplaced TRIMINFO register */
>>>> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>>>> +               interrupts = <0 185 0>;
>>>> +               clocks = <&clock 318>;
>>>> +               clock-names = "tmu_apbif";
>>>> +       };
>>>> +
>>>>  Note: For multi-instance tmu each instance should have an alias correctly
>>>>  numbered in "aliases" node.
>>>>
>>>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>>>> index bfdfbd6..f95844e 100644
>>>> --- a/drivers/thermal/samsung/exynos_tmu.c
>>>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>>>> @@ -42,6 +42,7 @@
>>>>   * @pdata: pointer to the tmu platform/configuration data
>>>>   * @base: base address of the single instance of the TMU controller.
>>>>   * @base_common: base address of the common registers of the TMU controller.
>>>> + * @triminfo_base: misplaced register base for TRIMINFO on Exynos5420 only
>>>
>>> Instead of creating this new field you can re-use base_common for
>>> accessing the second set of register for misplaced triminfo address.
>>> Also you can rename this variable as base_second.
>>
>> The purpose and the meaning of the fields are entirely different.
>> The triminfo is a hardware bug present only in Exynos5420
> My point is that for a bug a new field does not seem good as driver is
> common across many Socs. Even In case of 5440 the common base can be
> generalized and considered as second base address and documentation
> can be updated accordingly. Also change the flag SHARED_MEMORY to
> ADDRESS_TWO.

Why ADDRESS_TWO, are we expecting ADDRESS_THREE as well.

>> and the common registers are available only on Exynos5440 i guess.
>>
>> IMHO, reusing is not a nice idea.
>> I'm willing to modify the code if there is a better idea.
>>>
>>>>   * @irq: irq number of the TMU controller.
>>>>   * @soc: id of the SOC type.
>>>>   * @irq_work: pointer to the irq work structure.
>>>> @@ -57,6 +58,7 @@ struct exynos_tmu_data {
>>>>         struct exynos_tmu_platform_data *pdata;
>>>>         void __iomem *base;
>>>>         void __iomem *base_common;
>>>> +       void __iomem *triminfo_base;            /* Needed only Exynos5420 */
>>>>         int irq;
>>>>         enum soc_type soc;
>>>>         struct work_struct irq_work;
>>>> @@ -186,7 +188,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>>>>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>>>>                 }
>>>>         } else {
>>>> -               trim_info = readl(data->base + reg->triminfo_data);
>>>> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
>>>> +               if (data->triminfo_base)
>>>> +                       trim_info = readl(data->triminfo_base +
>>>> +                                               reg->triminfo_data);
>>>> +               else
>>>> +                       trim_info = readl(data->base + reg->triminfo_data);
>>>>         }
>>>>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>>>>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
>>>> @@ -586,8 +593,17 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>>>>          * Check if the TMU shares some registers and then try to map the
>>>>          * memory of common registers.
>>>>          */
>>>> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
>>>> +       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) {
>>>> +               /* For Exynos5420 The misplaced TERMINFO register address will
>>>> +                * be passed from device tree node.
>>>> +                *
>>>> +                * We cannot use devm_request_and_ioremap, as the base address
>>>> +                * over laps with the address space of the other TMU channel.
>>>> +                * Check Documentation for details
>>>> +                */
>>>> +               data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
>>>>                 return 0;
>>>> +       }
>>> In the below code, remove the request resource API for common_base and
>>> use simple of_iomap API.
>>
>> That will be a separate fix patch. Will submit separately,
>> This patchset is to add exynos5420 support
>
> Sorry for my earlier comment. Actually my suggested change is not
> needed as the APIs used don't bind resources. Just enable the
> SHARED_MEMORY flag and it should be fine.
>
>
>>
>> Is the res_size for the common registers fixed ?
> Yes in 5440 it is same.
>
> Thanks,
> Amit Daniel
>
>>
>>>
>>> Thanks,
>>> Amit Daniel
>>>>
>>>>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
>>>>                 dev_err(&pdev->dev, "failed to get Resource 1\n");
>>>> @@ -632,12 +648,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>>>>         if (IS_ERR(data->clk)) {
>>>>                 dev_err(&pdev->dev, "Failed to get clock\n");
>>>> -               return  PTR_ERR(data->clk);
>>>> +               ret = PTR_ERR(data->clk);
>>>> +               goto err_triminfo_base;
>>>>         }
>>>>
>>>>         ret = clk_prepare(data->clk);
>>>>         if (ret)
>>>> -               return ret;
>>>> +               goto err_triminfo_base;
>>>>
>>>>         if (pdata->type == SOC_ARCH_EXYNOS ||
>>>>                 pdata->type == SOC_ARCH_EXYNOS4210 ||
>>>> @@ -707,9 +724,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>>         }
>>>>
>>>>         return 0;
>>>> +
>>>>  err_clk:
>>>>         clk_unprepare(data->clk);
>>>>         return ret;
>>>> +err_triminfo_base:
>>>> +       if (data->triminfo_base)
>>>> +               iounmap(data->triminfo_base);
>>>>  }
>>>>
>>>>  static int exynos_tmu_remove(struct platform_device *pdev)
>>>> @@ -720,6 +741,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>>>>
>>>>         exynos_unregister_thermal(data->reg_conf);
>>>>
>>>> +       if (data->triminfo_base)
>>>> +               iounmap(data->triminfo_base);
>>>> +
>>>>         clk_unprepare(data->clk);
>>>>
>>>>         if (!IS_ERR(data->regulator))
>>>> --
>>>> 1.7.9.5
>>>>
>>>> --
>>>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>>>> the body of a message to majordomo@vger.kernel.org
>>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>> Please read the FAQ at  http://www.tux.org/lkml/
>>
>>
>>
>> --
>> Shine bright,
>> (: Nav :)
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
> On Wed, Aug 28, 2013 at 11:49 AM, Naveen Krishna Ch
> <naveenkrishna.ch@gmail.com> wrote:
>> On 28 August 2013 11:33, amit daniel kachhap <amit.daniel@samsung.com> wrote:
>>> Hi Naveen
>>>
>>> On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
>>> <ch.naveen@samsung.com> wrote:
>>>> This patch adds code to handle the misplaced TRIMINFO register
>>>> incase of Exynos5420.
>>>>
>>>> On Exynos5420 we have a TRIMINFO register being misplaced for
>>>> TMU channels 2, 3 and 4
>>>>
>>>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>>>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>>>> TRIMINFO at 0x10068000 contains data for TMU channel 2
>>>>
>>>> The misplaced register address is passed through devicetree and
>>>> map it seperately during probe.
>>>> Also, adds the documentation under devicetree/bindings/thermal/
>>>>
>>>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>>>> ---
>>>>  .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++++++++++
>>>>  drivers/thermal/samsung/exynos_tmu.c               |   32 +++++++++++++++++---
>>>>  2 files changed, 49 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>> index 284f530..e818473 100644
>>>> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>> @@ -7,12 +7,21 @@
>>>>                "samsung,exynos4210-tmu"
>>>>                "samsung,exynos5250-tmu"
>>>>                "samsung,exynos5440-tmu"
>>>> +              "samsung,exynos5420-tmu"
>>>>  - interrupt-parent : The phandle for the interrupt controller
>>>>  - reg : Address range of the thermal registers. For soc's which has multiple
>>>>         instances of TMU and some registers are shared across all TMU's like
>>>>         interrupt related then 2 set of register has to supplied. First set
>>>>         belongs to each instance of TMU and second set belongs to common TMU
>>>>         registers.
>>>> +
>>>> + ** NOTE FOR EXYNOS5420 **
>>>> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
>>>> +
>>>> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
>>>> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
>>>> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
>>>> +
>>>>  - interrupts : Should contain interrupt for thermal system
>>>>  - clocks : The main clock for TMU device
>>>>  - clock-names : Thermal system clock name
>>>> @@ -43,6 +52,18 @@ Example 2):
>>>>                 clock-names = "tmu_apbif";
>>>>         };
>>>>
>>>> +Example 3): In case of Exynos5420 TMU channel 3
>>>> +
>>>> +       /* tmu for CPU3 */
>>>> +       tmu@1006c000 {
>>>> +               compatible = "samsung,exynos5420-tmu";
>>>> +               /* 2nd reg is for the misplaced TRIMINFO register */
>>>> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>>>> +               interrupts = <0 185 0>;
>>>> +               clocks = <&clock 318>;
>>>> +               clock-names = "tmu_apbif";
>>>> +       };
>>>> +
>>>>  Note: For multi-instance tmu each instance should have an alias correctly
>>>>  numbered in "aliases" node.
>>>>
>>>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>>>> index bfdfbd6..f95844e 100644
>>>> --- a/drivers/thermal/samsung/exynos_tmu.c
>>>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>>>> @@ -42,6 +42,7 @@
>>>>   * @pdata: pointer to the tmu platform/configuration data
>>>>   * @base: base address of the single instance of the TMU controller.
>>>>   * @base_common: base address of the common registers of the TMU controller.
>>>> + * @triminfo_base: misplaced register base for TRIMINFO on Exynos5420 only
>>>
>>> Instead of creating this new field you can re-use base_common for
>>> accessing the second set of register for misplaced triminfo address.
>>> Also you can rename this variable as base_second.
>>
>> The purpose and the meaning of the fields are entirely different.
>> The triminfo is a hardware bug present only in Exynos5420
>> and the common registers are available only on Exynos5440 i guess.
>>
>> IMHO, reusing is not a nice idea.
>> I'm willing to modify the code if there is a better idea.
>>>
>>>>   * @irq: irq number of the TMU controller.
>>>>   * @soc: id of the SOC type.
>>>>   * @irq_work: pointer to the irq work structure.
>>>> @@ -57,6 +58,7 @@ struct exynos_tmu_data {
>>>>         struct exynos_tmu_platform_data *pdata;
>>>>         void __iomem *base;
>>>>         void __iomem *base_common;
>>>> +       void __iomem *triminfo_base;            /* Needed only Exynos5420 */
>>>>         int irq;
>>>>         enum soc_type soc;
>>>>         struct work_struct irq_work;
>>>> @@ -186,7 +188,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>>>>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>>>>                 }
>>>>         } else {
>>>> -               trim_info = readl(data->base + reg->triminfo_data);
>>>> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
>>>> +               if (data->triminfo_base)
>>>> +                       trim_info = readl(data->triminfo_base +
>>>> +                                               reg->triminfo_data);
>>>> +               else
>>>> +                       trim_info = readl(data->base + reg->triminfo_data);
>>>>         }
>>>>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>>>>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
>>>> @@ -586,8 +593,17 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>>>>          * Check if the TMU shares some registers and then try to map the
>>>>          * memory of common registers.
>>>>          */
>>>> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
>>>> +       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) {
>>>> +               /* For Exynos5420 The misplaced TERMINFO register address will
>>>> +                * be passed from device tree node.
>>>> +                *
>>>> +                * We cannot use devm_request_and_ioremap, as the base address
>>>> +                * over laps with the address space of the other TMU channel.
>>>> +                * Check Documentation for details
>>>> +                */
>>>> +               data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
>>>>                 return 0;
>>>> +       }
>>> In the below code, remove the request resource API for common_base and
>>> use simple of_iomap API.
>>
>> That will be a separate fix patch. Will submit separately,
>> This patchset is to add exynos5420 support
>>
>> Is the res_size for the common registers fixed ?
>>
>>>
>>> Thanks,
>>> Amit Daniel
>>>>
>>>>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
>>>>                 dev_err(&pdev->dev, "failed to get Resource 1\n");
>>>> @@ -632,12 +648,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>>>>         if (IS_ERR(data->clk)) {
>>>>                 dev_err(&pdev->dev, "Failed to get clock\n");
>>>> -               return  PTR_ERR(data->clk);
>>>> +               ret = PTR_ERR(data->clk);
>>>> +               goto err_triminfo_base;
>>>>         }
>>>>
>>>>         ret = clk_prepare(data->clk);
>>>>         if (ret)
>>>> -               return ret;
>>>> +               goto err_triminfo_base;
>>>>
>>>>         if (pdata->type == SOC_ARCH_EXYNOS ||
>>>>                 pdata->type == SOC_ARCH_EXYNOS4210 ||
>>>> @@ -707,9 +724,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>>         }
>>>>
>>>>         return 0;
>>>> +
>>>>  err_clk:
>>>>         clk_unprepare(data->clk);
>>>>         return ret;
>>>> +err_triminfo_base:
>>>> +       if (data->triminfo_base)
>>>> +               iounmap(data->triminfo_base);
>>>>  }
>>>>
>>>>  static int exynos_tmu_remove(struct platform_device *pdev)
>>>> @@ -720,6 +741,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>>>>
>>>>         exynos_unregister_thermal(data->reg_conf);
>>>>
>>>> +       if (data->triminfo_base)
>>>> +               iounmap(data->triminfo_base);
>>>> +
>>>>         clk_unprepare(data->clk);
>>>>
>>>>         if (!IS_ERR(data->regulator))
>>>> --
>>>> 1.7.9.5
>>>>
>>>> --
>>>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>>>> the body of a message to majordomo@vger.kernel.org
>>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>> Please read the FAQ at  http://www.tux.org/lkml/
>>
>>
>>
>> --
>> Shine bright,
>> (: Nav :)
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html



-- 
Shine bright,
(: Nav :)

Re: [PATCH 3/3] thermal: exynos: Handle the misplaced TRIMINFO register

[amit daniel kachhap]

On Wed, Aug 28, 2013 at 2:27 PM, Naveen Krishna Ch
<naveenkrishna.ch@gmail.com> wrote:
> On 28 August 2013 14:13, amit daniel kachhap <amit.daniel@samsung.com> wrote:
>> Hi Naveen,
>>
>> On Wed, Aug 28, 2013 at 11:49 AM, Naveen Krishna Ch
>> <naveenkrishna.ch@gmail.com> wrote:
>>> On 28 August 2013 11:33, amit daniel kachhap <amit.daniel@samsung.com> wrote:
>>>> Hi Naveen
>>>>
>>>> On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
>>>> <ch.naveen@samsung.com> wrote:
>>>>> This patch adds code to handle the misplaced TRIMINFO register
>>>>> incase of Exynos5420.
>>>>>
>>>>> On Exynos5420 we have a TRIMINFO register being misplaced for
>>>>> TMU channels 2, 3 and 4
>>>>>
>>>>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>>>>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>>>>> TRIMINFO at 0x10068000 contains data for TMU channel 2
>>>>>
>>>>> The misplaced register address is passed through devicetree and
>>>>> map it seperately during probe.
>>>>> Also, adds the documentation under devicetree/bindings/thermal/
>>>>>
>>>>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>>>>> ---
>>>>>  .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++++++++++
>>>>>  drivers/thermal/samsung/exynos_tmu.c               |   32 +++++++++++++++++---
>>>>>  2 files changed, 49 insertions(+), 4 deletions(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>>> index 284f530..e818473 100644
>>>>> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>>> @@ -7,12 +7,21 @@
>>>>>                "samsung,exynos4210-tmu"
>>>>>                "samsung,exynos5250-tmu"
>>>>>                "samsung,exynos5440-tmu"
>>>>> +              "samsung,exynos5420-tmu"
>>>>>  - interrupt-parent : The phandle for the interrupt controller
>>>>>  - reg : Address range of the thermal registers. For soc's which has multiple
>>>>>         instances of TMU and some registers are shared across all TMU's like
>>>>>         interrupt related then 2 set of register has to supplied. First set
>>>>>         belongs to each instance of TMU and second set belongs to common TMU
>>>>>         registers.
>>>>> +
>>>>> + ** NOTE FOR EXYNOS5420 **
>>>>> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
>>>>> +
>>>>> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
>>>>> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
>>>>> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
>>>>> +
>>>>>  - interrupts : Should contain interrupt for thermal system
>>>>>  - clocks : The main clock for TMU device
>>>>>  - clock-names : Thermal system clock name
>>>>> @@ -43,6 +52,18 @@ Example 2):
>>>>>                 clock-names = "tmu_apbif";
>>>>>         };
>>>>>
>>>>> +Example 3): In case of Exynos5420 TMU channel 3
>>>>> +
>>>>> +       /* tmu for CPU3 */
>>>>> +       tmu@1006c000 {
>>>>> +               compatible = "samsung,exynos5420-tmu";
>>>>> +               /* 2nd reg is for the misplaced TRIMINFO register */
>>>>> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>>>>> +               interrupts = <0 185 0>;
>>>>> +               clocks = <&clock 318>;
>>>>> +               clock-names = "tmu_apbif";
>>>>> +       };
>>>>> +
>>>>>  Note: For multi-instance tmu each instance should have an alias correctly
>>>>>  numbered in "aliases" node.
>>>>>
>>>>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>>>>> index bfdfbd6..f95844e 100644
>>>>> --- a/drivers/thermal/samsung/exynos_tmu.c
>>>>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>>>>> @@ -42,6 +42,7 @@
>>>>>   * @pdata: pointer to the tmu platform/configuration data
>>>>>   * @base: base address of the single instance of the TMU controller.
>>>>>   * @base_common: base address of the common registers of the TMU controller.
>>>>> + * @triminfo_base: misplaced register base for TRIMINFO on Exynos5420 only
>>>>
>>>> Instead of creating this new field you can re-use base_common for
>>>> accessing the second set of register for misplaced triminfo address.
>>>> Also you can rename this variable as base_second.
>>>
>>> The purpose and the meaning of the fields are entirely different.
>>> The triminfo is a hardware bug present only in Exynos5420
>> My point is that for a bug a new field does not seem good as driver is
>> common across many Socs. Even In case of 5440 the common base can be
>> generalized and considered as second base address and documentation
>> can be updated accordingly. Also change the flag SHARED_MEMORY to
>> ADDRESS_TWO.
>
> Why ADDRESS_TWO, are we expecting ADDRESS_THREE as well.
or ADDRESS_MULTIPLE :)
>
>>> and the common registers are available only on Exynos5440 i guess.
>>>
>>> IMHO, reusing is not a nice idea.
>>> I'm willing to modify the code if there is a better idea.
>>>>
>>>>>   * @irq: irq number of the TMU controller.
>>>>>   * @soc: id of the SOC type.
>>>>>   * @irq_work: pointer to the irq work structure.
>>>>> @@ -57,6 +58,7 @@ struct exynos_tmu_data {
>>>>>         struct exynos_tmu_platform_data *pdata;
>>>>>         void __iomem *base;
>>>>>         void __iomem *base_common;
>>>>> +       void __iomem *triminfo_base;            /* Needed only Exynos5420 */
>>>>>         int irq;
>>>>>         enum soc_type soc;
>>>>>         struct work_struct irq_work;
>>>>> @@ -186,7 +188,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>>>>>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>>>>>                 }
>>>>>         } else {
>>>>> -               trim_info = readl(data->base + reg->triminfo_data);
>>>>> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
>>>>> +               if (data->triminfo_base)
>>>>> +                       trim_info = readl(data->triminfo_base +
>>>>> +                                               reg->triminfo_data);
>>>>> +               else
>>>>> +                       trim_info = readl(data->base + reg->triminfo_data);
>>>>>         }
>>>>>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>>>>>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
>>>>> @@ -586,8 +593,17 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>>>>>          * Check if the TMU shares some registers and then try to map the
>>>>>          * memory of common registers.
>>>>>          */
>>>>> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
>>>>> +       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) {
>>>>> +               /* For Exynos5420 The misplaced TERMINFO register address will
>>>>> +                * be passed from device tree node.
>>>>> +                *
>>>>> +                * We cannot use devm_request_and_ioremap, as the base address
>>>>> +                * over laps with the address space of the other TMU channel.
>>>>> +                * Check Documentation for details
>>>>> +                */
>>>>> +               data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
>>>>>                 return 0;
>>>>> +       }
>>>> In the below code, remove the request resource API for common_base and
>>>> use simple of_iomap API.
>>>
>>> That will be a separate fix patch. Will submit separately,
>>> This patchset is to add exynos5420 support
>>
>> Sorry for my earlier comment. Actually my suggested change is not
>> needed as the APIs used don't bind resources. Just enable the
>> SHARED_MEMORY flag and it should be fine.
>>
>>
>>>
>>> Is the res_size for the common registers fixed ?
>> Yes in 5440 it is same.
>>
>> Thanks,
>> Amit Daniel
>>
>>>
>>>>
>>>> Thanks,
>>>> Amit Daniel
>>>>>
>>>>>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
>>>>>                 dev_err(&pdev->dev, "failed to get Resource 1\n");
>>>>> @@ -632,12 +648,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>>>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>>>>>         if (IS_ERR(data->clk)) {
>>>>>                 dev_err(&pdev->dev, "Failed to get clock\n");
>>>>> -               return  PTR_ERR(data->clk);
>>>>> +               ret = PTR_ERR(data->clk);
>>>>> +               goto err_triminfo_base;
>>>>>         }
>>>>>
>>>>>         ret = clk_prepare(data->clk);
>>>>>         if (ret)
>>>>> -               return ret;
>>>>> +               goto err_triminfo_base;
>>>>>
>>>>>         if (pdata->type == SOC_ARCH_EXYNOS ||
>>>>>                 pdata->type == SOC_ARCH_EXYNOS4210 ||
>>>>> @@ -707,9 +724,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>>>         }
>>>>>
>>>>>         return 0;
>>>>> +
>>>>>  err_clk:
>>>>>         clk_unprepare(data->clk);
>>>>>         return ret;
>>>>> +err_triminfo_base:
>>>>> +       if (data->triminfo_base)
>>>>> +               iounmap(data->triminfo_base);
>>>>>  }
>>>>>
>>>>>  static int exynos_tmu_remove(struct platform_device *pdev)
>>>>> @@ -720,6 +741,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>>>>>
>>>>>         exynos_unregister_thermal(data->reg_conf);
>>>>>
>>>>> +       if (data->triminfo_base)
>>>>> +               iounmap(data->triminfo_base);
>>>>> +
>>>>>         clk_unprepare(data->clk);
>>>>>
>>>>>         if (!IS_ERR(data->regulator))
>>>>> --
>>>>> 1.7.9.5
>>>>>
>>>>> --
>>>>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>>>>> the body of a message to majordomo@vger.kernel.org
>>>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>>> Please read the FAQ at  http://www.tux.org/lkml/
>>>
>>>
>>>
>>> --
>>> Shine bright,
>>> (: Nav :)
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>> On Wed, Aug 28, 2013 at 11:49 AM, Naveen Krishna Ch
>> <naveenkrishna.ch@gmail.com> wrote:
>>> On 28 August 2013 11:33, amit daniel kachhap <amit.daniel@samsung.com> wrote:
>>>> Hi Naveen
>>>>
>>>> On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
>>>> <ch.naveen@samsung.com> wrote:
>>>>> This patch adds code to handle the misplaced TRIMINFO register
>>>>> incase of Exynos5420.
>>>>>
>>>>> On Exynos5420 we have a TRIMINFO register being misplaced for
>>>>> TMU channels 2, 3 and 4
>>>>>
>>>>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>>>>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>>>>> TRIMINFO at 0x10068000 contains data for TMU channel 2
>>>>>
>>>>> The misplaced register address is passed through devicetree and
>>>>> map it seperately during probe.
>>>>> Also, adds the documentation under devicetree/bindings/thermal/
>>>>>
>>>>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>>>>> ---
>>>>>  .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++++++++++
>>>>>  drivers/thermal/samsung/exynos_tmu.c               |   32 +++++++++++++++++---
>>>>>  2 files changed, 49 insertions(+), 4 deletions(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>>> index 284f530..e818473 100644
>>>>> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>>> @@ -7,12 +7,21 @@
>>>>>                "samsung,exynos4210-tmu"
>>>>>                "samsung,exynos5250-tmu"
>>>>>                "samsung,exynos5440-tmu"
>>>>> +              "samsung,exynos5420-tmu"
>>>>>  - interrupt-parent : The phandle for the interrupt controller
>>>>>  - reg : Address range of the thermal registers. For soc's which has multiple
>>>>>         instances of TMU and some registers are shared across all TMU's like
>>>>>         interrupt related then 2 set of register has to supplied. First set
>>>>>         belongs to each instance of TMU and second set belongs to common TMU
>>>>>         registers.
>>>>> +
>>>>> + ** NOTE FOR EXYNOS5420 **
>>>>> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
>>>>> +
>>>>> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
>>>>> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
>>>>> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
>>>>> +
>>>>>  - interrupts : Should contain interrupt for thermal system
>>>>>  - clocks : The main clock for TMU device
>>>>>  - clock-names : Thermal system clock name
>>>>> @@ -43,6 +52,18 @@ Example 2):
>>>>>                 clock-names = "tmu_apbif";
>>>>>         };
>>>>>
>>>>> +Example 3): In case of Exynos5420 TMU channel 3
>>>>> +
>>>>> +       /* tmu for CPU3 */
>>>>> +       tmu@1006c000 {
>>>>> +               compatible = "samsung,exynos5420-tmu";
>>>>> +               /* 2nd reg is for the misplaced TRIMINFO register */
>>>>> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>>>>> +               interrupts = <0 185 0>;
>>>>> +               clocks = <&clock 318>;
>>>>> +               clock-names = "tmu_apbif";
>>>>> +       };
>>>>> +
>>>>>  Note: For multi-instance tmu each instance should have an alias correctly
>>>>>  numbered in "aliases" node.
>>>>>
>>>>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>>>>> index bfdfbd6..f95844e 100644
>>>>> --- a/drivers/thermal/samsung/exynos_tmu.c
>>>>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>>>>> @@ -42,6 +42,7 @@
>>>>>   * @pdata: pointer to the tmu platform/configuration data
>>>>>   * @base: base address of the single instance of the TMU controller.
>>>>>   * @base_common: base address of the common registers of the TMU controller.
>>>>> + * @triminfo_base: misplaced register base for TRIMINFO on Exynos5420 only
>>>>
>>>> Instead of creating this new field you can re-use base_common for
>>>> accessing the second set of register for misplaced triminfo address.
>>>> Also you can rename this variable as base_second.
>>>
>>> The purpose and the meaning of the fields are entirely different.
>>> The triminfo is a hardware bug present only in Exynos5420
>>> and the common registers are available only on Exynos5440 i guess.
>>>
>>> IMHO, reusing is not a nice idea.
>>> I'm willing to modify the code if there is a better idea.
>>>>
>>>>>   * @irq: irq number of the TMU controller.
>>>>>   * @soc: id of the SOC type.
>>>>>   * @irq_work: pointer to the irq work structure.
>>>>> @@ -57,6 +58,7 @@ struct exynos_tmu_data {
>>>>>         struct exynos_tmu_platform_data *pdata;
>>>>>         void __iomem *base;
>>>>>         void __iomem *base_common;
>>>>> +       void __iomem *triminfo_base;            /* Needed only Exynos5420 */
>>>>>         int irq;
>>>>>         enum soc_type soc;
>>>>>         struct work_struct irq_work;
>>>>> @@ -186,7 +188,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>>>>>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>>>>>                 }
>>>>>         } else {
>>>>> -               trim_info = readl(data->base + reg->triminfo_data);
>>>>> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
>>>>> +               if (data->triminfo_base)
>>>>> +                       trim_info = readl(data->triminfo_base +
>>>>> +                                               reg->triminfo_data);
>>>>> +               else
>>>>> +                       trim_info = readl(data->base + reg->triminfo_data);
>>>>>         }
>>>>>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>>>>>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
>>>>> @@ -586,8 +593,17 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>>>>>          * Check if the TMU shares some registers and then try to map the
>>>>>          * memory of common registers.
>>>>>          */
>>>>> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
>>>>> +       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) {
>>>>> +               /* For Exynos5420 The misplaced TERMINFO register address will
>>>>> +                * be passed from device tree node.
>>>>> +                *
>>>>> +                * We cannot use devm_request_and_ioremap, as the base address
>>>>> +                * over laps with the address space of the other TMU channel.
>>>>> +                * Check Documentation for details
>>>>> +                */
>>>>> +               data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
>>>>>                 return 0;
>>>>> +       }
>>>> In the below code, remove the request resource API for common_base and
>>>> use simple of_iomap API.
>>>
>>> That will be a separate fix patch. Will submit separately,
>>> This patchset is to add exynos5420 support
>>>
>>> Is the res_size for the common registers fixed ?
>>>
>>>>
>>>> Thanks,
>>>> Amit Daniel
>>>>>
>>>>>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
>>>>>                 dev_err(&pdev->dev, "failed to get Resource 1\n");
>>>>> @@ -632,12 +648,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>>>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>>>>>         if (IS_ERR(data->clk)) {
>>>>>                 dev_err(&pdev->dev, "Failed to get clock\n");
>>>>> -               return  PTR_ERR(data->clk);
>>>>> +               ret = PTR_ERR(data->clk);
>>>>> +               goto err_triminfo_base;
>>>>>         }
>>>>>
>>>>>         ret = clk_prepare(data->clk);
>>>>>         if (ret)
>>>>> -               return ret;
>>>>> +               goto err_triminfo_base;
>>>>>
>>>>>         if (pdata->type == SOC_ARCH_EXYNOS ||
>>>>>                 pdata->type == SOC_ARCH_EXYNOS4210 ||
>>>>> @@ -707,9 +724,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>>>         }
>>>>>
>>>>>         return 0;
>>>>> +
>>>>>  err_clk:
>>>>>         clk_unprepare(data->clk);
>>>>>         return ret;
>>>>> +err_triminfo_base:
>>>>> +       if (data->triminfo_base)
>>>>> +               iounmap(data->triminfo_base);
>>>>>  }
>>>>>
>>>>>  static int exynos_tmu_remove(struct platform_device *pdev)
>>>>> @@ -720,6 +741,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>>>>>
>>>>>         exynos_unregister_thermal(data->reg_conf);
>>>>>
>>>>> +       if (data->triminfo_base)
>>>>> +               iounmap(data->triminfo_base);
>>>>> +
>>>>>         clk_unprepare(data->clk);
>>>>>
>>>>>         if (!IS_ERR(data->regulator))
>>>>> --
>>>>> 1.7.9.5
>>>>>
>>>>> --
>>>>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>>>>> the body of a message to majordomo@vger.kernel.org
>>>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>>> Please read the FAQ at  http://www.tux.org/lkml/
>>>
>>>
>>>
>>> --
>>> Shine bright,
>>> (: Nav :)
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Shine bright,
> (: Nav :)
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html


On Wed, Aug 28, 2013 at 2:27 PM, Naveen Krishna Ch
<naveenkrishna.ch@gmail.com> wrote:
> On 28 August 2013 14:13, amit daniel kachhap <amit.daniel@samsung.com> wrote:
>> Hi Naveen,
>>
>> On Wed, Aug 28, 2013 at 11:49 AM, Naveen Krishna Ch
>> <naveenkrishna.ch@gmail.com> wrote:
>>> On 28 August 2013 11:33, amit daniel kachhap <amit.daniel@samsung.com> wrote:
>>>> Hi Naveen
>>>>
>>>> On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
>>>> <ch.naveen@samsung.com> wrote:
>>>>> This patch adds code to handle the misplaced TRIMINFO register
>>>>> incase of Exynos5420.
>>>>>
>>>>> On Exynos5420 we have a TRIMINFO register being misplaced for
>>>>> TMU channels 2, 3 and 4
>>>>>
>>>>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>>>>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>>>>> TRIMINFO at 0x10068000 contains data for TMU channel 2
>>>>>
>>>>> The misplaced register address is passed through devicetree and
>>>>> map it seperately during probe.
>>>>> Also, adds the documentation under devicetree/bindings/thermal/
>>>>>
>>>>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>>>>> ---
>>>>>  .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++++++++++
>>>>>  drivers/thermal/samsung/exynos_tmu.c               |   32 +++++++++++++++++---
>>>>>  2 files changed, 49 insertions(+), 4 deletions(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>>> index 284f530..e818473 100644
>>>>> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>>> @@ -7,12 +7,21 @@
>>>>>                "samsung,exynos4210-tmu"
>>>>>                "samsung,exynos5250-tmu"
>>>>>                "samsung,exynos5440-tmu"
>>>>> +              "samsung,exynos5420-tmu"
>>>>>  - interrupt-parent : The phandle for the interrupt controller
>>>>>  - reg : Address range of the thermal registers. For soc's which has multiple
>>>>>         instances of TMU and some registers are shared across all TMU's like
>>>>>         interrupt related then 2 set of register has to supplied. First set
>>>>>         belongs to each instance of TMU and second set belongs to common TMU
>>>>>         registers.
>>>>> +
>>>>> + ** NOTE FOR EXYNOS5420 **
>>>>> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
>>>>> +
>>>>> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
>>>>> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
>>>>> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
>>>>> +
>>>>>  - interrupts : Should contain interrupt for thermal system
>>>>>  - clocks : The main clock for TMU device
>>>>>  - clock-names : Thermal system clock name
>>>>> @@ -43,6 +52,18 @@ Example 2):
>>>>>                 clock-names = "tmu_apbif";
>>>>>         };
>>>>>
>>>>> +Example 3): In case of Exynos5420 TMU channel 3
>>>>> +
>>>>> +       /* tmu for CPU3 */
>>>>> +       tmu@1006c000 {
>>>>> +               compatible = "samsung,exynos5420-tmu";
>>>>> +               /* 2nd reg is for the misplaced TRIMINFO register */
>>>>> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>>>>> +               interrupts = <0 185 0>;
>>>>> +               clocks = <&clock 318>;
>>>>> +               clock-names = "tmu_apbif";
>>>>> +       };
>>>>> +
>>>>>  Note: For multi-instance tmu each instance should have an alias correctly
>>>>>  numbered in "aliases" node.
>>>>>
>>>>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>>>>> index bfdfbd6..f95844e 100644
>>>>> --- a/drivers/thermal/samsung/exynos_tmu.c
>>>>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>>>>> @@ -42,6 +42,7 @@
>>>>>   * @pdata: pointer to the tmu platform/configuration data
>>>>>   * @base: base address of the single instance of the TMU controller.
>>>>>   * @base_common: base address of the common registers of the TMU controller.
>>>>> + * @triminfo_base: misplaced register base for TRIMINFO on Exynos5420 only
>>>>
>>>> Instead of creating this new field you can re-use base_common for
>>>> accessing the second set of register for misplaced triminfo address.
>>>> Also you can rename this variable as base_second.
>>>
>>> The purpose and the meaning of the fields are entirely different.
>>> The triminfo is a hardware bug present only in Exynos5420
>> My point is that for a bug a new field does not seem good as driver is
>> common across many Socs. Even In case of 5440 the common base can be
>> generalized and considered as second base address and documentation
>> can be updated accordingly. Also change the flag SHARED_MEMORY to
>> ADDRESS_TWO.
>
> Why ADDRESS_TWO, are we expecting ADDRESS_THREE as well.
>
>>> and the common registers are available only on Exynos5440 i guess.
>>>
>>> IMHO, reusing is not a nice idea.
>>> I'm willing to modify the code if there is a better idea.
>>>>
>>>>>   * @irq: irq number of the TMU controller.
>>>>>   * @soc: id of the SOC type.
>>>>>   * @irq_work: pointer to the irq work structure.
>>>>> @@ -57,6 +58,7 @@ struct exynos_tmu_data {
>>>>>         struct exynos_tmu_platform_data *pdata;
>>>>>         void __iomem *base;
>>>>>         void __iomem *base_common;
>>>>> +       void __iomem *triminfo_base;            /* Needed only Exynos5420 */
>>>>>         int irq;
>>>>>         enum soc_type soc;
>>>>>         struct work_struct irq_work;
>>>>> @@ -186,7 +188,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>>>>>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>>>>>                 }
>>>>>         } else {
>>>>> -               trim_info = readl(data->base + reg->triminfo_data);
>>>>> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
>>>>> +               if (data->triminfo_base)
>>>>> +                       trim_info = readl(data->triminfo_base +
>>>>> +                                               reg->triminfo_data);
>>>>> +               else
>>>>> +                       trim_info = readl(data->base + reg->triminfo_data);
>>>>>         }
>>>>>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>>>>>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
>>>>> @@ -586,8 +593,17 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>>>>>          * Check if the TMU shares some registers and then try to map the
>>>>>          * memory of common registers.
>>>>>          */
>>>>> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
>>>>> +       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) {
>>>>> +               /* For Exynos5420 The misplaced TERMINFO register address will
>>>>> +                * be passed from device tree node.
>>>>> +                *
>>>>> +                * We cannot use devm_request_and_ioremap, as the base address
>>>>> +                * over laps with the address space of the other TMU channel.
>>>>> +                * Check Documentation for details
>>>>> +                */
>>>>> +               data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
>>>>>                 return 0;
>>>>> +       }
>>>> In the below code, remove the request resource API for common_base and
>>>> use simple of_iomap API.
>>>
>>> That will be a separate fix patch. Will submit separately,
>>> This patchset is to add exynos5420 support
>>
>> Sorry for my earlier comment. Actually my suggested change is not
>> needed as the APIs used don't bind resources. Just enable the
>> SHARED_MEMORY flag and it should be fine.
>>
>>
>>>
>>> Is the res_size for the common registers fixed ?
>> Yes in 5440 it is same.
>>
>> Thanks,
>> Amit Daniel
>>
>>>
>>>>
>>>> Thanks,
>>>> Amit Daniel
>>>>>
>>>>>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
>>>>>                 dev_err(&pdev->dev, "failed to get Resource 1\n");
>>>>> @@ -632,12 +648,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>>>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>>>>>         if (IS_ERR(data->clk)) {
>>>>>                 dev_err(&pdev->dev, "Failed to get clock\n");
>>>>> -               return  PTR_ERR(data->clk);
>>>>> +               ret = PTR_ERR(data->clk);
>>>>> +               goto err_triminfo_base;
>>>>>         }
>>>>>
>>>>>         ret = clk_prepare(data->clk);
>>>>>         if (ret)
>>>>> -               return ret;
>>>>> +               goto err_triminfo_base;
>>>>>
>>>>>         if (pdata->type == SOC_ARCH_EXYNOS ||
>>>>>                 pdata->type == SOC_ARCH_EXYNOS4210 ||
>>>>> @@ -707,9 +724,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>>>         }
>>>>>
>>>>>         return 0;
>>>>> +
>>>>>  err_clk:
>>>>>         clk_unprepare(data->clk);
>>>>>         return ret;
>>>>> +err_triminfo_base:
>>>>> +       if (data->triminfo_base)
>>>>> +               iounmap(data->triminfo_base);
>>>>>  }
>>>>>
>>>>>  static int exynos_tmu_remove(struct platform_device *pdev)
>>>>> @@ -720,6 +741,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>>>>>
>>>>>         exynos_unregister_thermal(data->reg_conf);
>>>>>
>>>>> +       if (data->triminfo_base)
>>>>> +               iounmap(data->triminfo_base);
>>>>> +
>>>>>         clk_unprepare(data->clk);
>>>>>
>>>>>         if (!IS_ERR(data->regulator))
>>>>> --
>>>>> 1.7.9.5
>>>>>
>>>>> --
>>>>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>>>>> the body of a message to majordomo@vger.kernel.org
>>>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>>> Please read the FAQ at  http://www.tux.org/lkml/
>>>
>>>
>>>
>>> --
>>> Shine bright,
>>> (: Nav :)
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>
>> On Wed, Aug 28, 2013 at 11:49 AM, Naveen Krishna Ch
>> <naveenkrishna.ch@gmail.com> wrote:
>>> On 28 August 2013 11:33, amit daniel kachhap <amit.daniel@samsung.com> wrote:
>>>> Hi Naveen
>>>>
>>>> On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
>>>> <ch.naveen@samsung.com> wrote:
>>>>> This patch adds code to handle the misplaced TRIMINFO register
>>>>> incase of Exynos5420.
>>>>>
>>>>> On Exynos5420 we have a TRIMINFO register being misplaced for
>>>>> TMU channels 2, 3 and 4
>>>>>
>>>>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>>>>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>>>>> TRIMINFO at 0x10068000 contains data for TMU channel 2
>>>>>
>>>>> The misplaced register address is passed through devicetree and
>>>>> map it seperately during probe.
>>>>> Also, adds the documentation under devicetree/bindings/thermal/
>>>>>
>>>>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>>>>> ---
>>>>>  .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++++++++++
>>>>>  drivers/thermal/samsung/exynos_tmu.c               |   32 +++++++++++++++++---
>>>>>  2 files changed, 49 insertions(+), 4 deletions(-)
>>>>>
>>>>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>>> index 284f530..e818473 100644
>>>>> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>>>> @@ -7,12 +7,21 @@
>>>>>                "samsung,exynos4210-tmu"
>>>>>                "samsung,exynos5250-tmu"
>>>>>                "samsung,exynos5440-tmu"
>>>>> +              "samsung,exynos5420-tmu"
>>>>>  - interrupt-parent : The phandle for the interrupt controller
>>>>>  - reg : Address range of the thermal registers. For soc's which has multiple
>>>>>         instances of TMU and some registers are shared across all TMU's like
>>>>>         interrupt related then 2 set of register has to supplied. First set
>>>>>         belongs to each instance of TMU and second set belongs to common TMU
>>>>>         registers.
>>>>> +
>>>>> + ** NOTE FOR EXYNOS5420 **
>>>>> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
>>>>> +
>>>>> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
>>>>> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
>>>>> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
>>>>> +
>>>>>  - interrupts : Should contain interrupt for thermal system
>>>>>  - clocks : The main clock for TMU device
>>>>>  - clock-names : Thermal system clock name
>>>>> @@ -43,6 +52,18 @@ Example 2):
>>>>>                 clock-names = "tmu_apbif";
>>>>>         };
>>>>>
>>>>> +Example 3): In case of Exynos5420 TMU channel 3
>>>>> +
>>>>> +       /* tmu for CPU3 */
>>>>> +       tmu@1006c000 {
>>>>> +               compatible = "samsung,exynos5420-tmu";
>>>>> +               /* 2nd reg is for the misplaced TRIMINFO register */
>>>>> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>>>>> +               interrupts = <0 185 0>;
>>>>> +               clocks = <&clock 318>;
>>>>> +               clock-names = "tmu_apbif";
>>>>> +       };
>>>>> +
>>>>>  Note: For multi-instance tmu each instance should have an alias correctly
>>>>>  numbered in "aliases" node.
>>>>>
>>>>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>>>>> index bfdfbd6..f95844e 100644
>>>>> --- a/drivers/thermal/samsung/exynos_tmu.c
>>>>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>>>>> @@ -42,6 +42,7 @@
>>>>>   * @pdata: pointer to the tmu platform/configuration data
>>>>>   * @base: base address of the single instance of the TMU controller.
>>>>>   * @base_common: base address of the common registers of the TMU controller.
>>>>> + * @triminfo_base: misplaced register base for TRIMINFO on Exynos5420 only
>>>>
>>>> Instead of creating this new field you can re-use base_common for
>>>> accessing the second set of register for misplaced triminfo address.
>>>> Also you can rename this variable as base_second.
>>>
>>> The purpose and the meaning of the fields are entirely different.
>>> The triminfo is a hardware bug present only in Exynos5420
>>> and the common registers are available only on Exynos5440 i guess.
>>>
>>> IMHO, reusing is not a nice idea.
>>> I'm willing to modify the code if there is a better idea.
>>>>
>>>>>   * @irq: irq number of the TMU controller.
>>>>>   * @soc: id of the SOC type.
>>>>>   * @irq_work: pointer to the irq work structure.
>>>>> @@ -57,6 +58,7 @@ struct exynos_tmu_data {
>>>>>         struct exynos_tmu_platform_data *pdata;
>>>>>         void __iomem *base;
>>>>>         void __iomem *base_common;
>>>>> +       void __iomem *triminfo_base;            /* Needed only Exynos5420 */
>>>>>         int irq;
>>>>>         enum soc_type soc;
>>>>>         struct work_struct irq_work;
>>>>> @@ -186,7 +188,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>>>>>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>>>>>                 }
>>>>>         } else {
>>>>> -               trim_info = readl(data->base + reg->triminfo_data);
>>>>> +               /* On exynos5420 TRIMINFO is misplaced for some channels */
>>>>> +               if (data->triminfo_base)
>>>>> +                       trim_info = readl(data->triminfo_base +
>>>>> +                                               reg->triminfo_data);
>>>>> +               else
>>>>> +                       trim_info = readl(data->base + reg->triminfo_data);
>>>>>         }
>>>>>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>>>>>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
>>>>> @@ -586,8 +593,17 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>>>>>          * Check if the TMU shares some registers and then try to map the
>>>>>          * memory of common registers.
>>>>>          */
>>>>> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
>>>>> +       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) {
>>>>> +               /* For Exynos5420 The misplaced TERMINFO register address will
>>>>> +                * be passed from device tree node.
>>>>> +                *
>>>>> +                * We cannot use devm_request_and_ioremap, as the base address
>>>>> +                * over laps with the address space of the other TMU channel.
>>>>> +                * Check Documentation for details
>>>>> +                */
>>>>> +               data->triminfo_base = of_iomap(pdev->dev.of_node, 1);
>>>>>                 return 0;
>>>>> +       }
>>>> In the below code, remove the request resource API for common_base and
>>>> use simple of_iomap API.
>>>
>>> That will be a separate fix patch. Will submit separately,
>>> This patchset is to add exynos5420 support
>>>
>>> Is the res_size for the common registers fixed ?
>>>
>>>>
>>>> Thanks,
>>>> Amit Daniel
>>>>>
>>>>>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
>>>>>                 dev_err(&pdev->dev, "failed to get Resource 1\n");
>>>>> @@ -632,12 +648,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>>>         data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>>>>>         if (IS_ERR(data->clk)) {
>>>>>                 dev_err(&pdev->dev, "Failed to get clock\n");
>>>>> -               return  PTR_ERR(data->clk);
>>>>> +               ret = PTR_ERR(data->clk);
>>>>> +               goto err_triminfo_base;
>>>>>         }
>>>>>
>>>>>         ret = clk_prepare(data->clk);
>>>>>         if (ret)
>>>>> -               return ret;
>>>>> +               goto err_triminfo_base;
>>>>>
>>>>>         if (pdata->type == SOC_ARCH_EXYNOS ||
>>>>>                 pdata->type == SOC_ARCH_EXYNOS4210 ||
>>>>> @@ -707,9 +724,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>>>>         }
>>>>>
>>>>>         return 0;
>>>>> +
>>>>>  err_clk:
>>>>>         clk_unprepare(data->clk);
>>>>>         return ret;
>>>>> +err_triminfo_base:
>>>>> +       if (data->triminfo_base)
>>>>> +               iounmap(data->triminfo_base);
>>>>>  }
>>>>>
>>>>>  static int exynos_tmu_remove(struct platform_device *pdev)
>>>>> @@ -720,6 +741,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>>>>>
>>>>>         exynos_unregister_thermal(data->reg_conf);
>>>>>
>>>>> +       if (data->triminfo_base)
>>>>> +               iounmap(data->triminfo_base);
>>>>> +
>>>>>         clk_unprepare(data->clk);
>>>>>
>>>>>         if (!IS_ERR(data->regulator))
>>>>> --
>>>>> 1.7.9.5
>>>>>
>>>>> --
>>>>> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
>>>>> the body of a message to majordomo@vger.kernel.org
>>>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>>>>> Please read the FAQ at  http://www.tux.org/lkml/
>>>
>>>
>>>
>>> --
>>> Shine bright,
>>> (: Nav :)
>>> --
>>> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
>>> the body of a message to majordomo@vger.kernel.org
>>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
>
>
> --
> Shine bright,
> (: Nav :)
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

[PATCH 1/3 v2] thermal: samsung: correct the fall interrupt en, status bit fields

[Naveen Krishna Chatradhi]

The FALL interrupt related en, status bits are available at an offset of
16 on INTEN, INTSTAT registers and at an offset of
12 on INTCLEAR register.

This patch corrects the same for exyns5250 and exynos5440

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---

Changes since v1:
  None

 drivers/thermal/samsung/exynos_tmu.c      |    2 +-
 drivers/thermal/samsung/exynos_tmu.h      |    2 ++
 drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
 drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
 4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index ec01dfe..d201ed8 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -265,7 +265,7 @@ skip_calib_data:
 				data->base + reg->threshold_th1);
 
 		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
-			(reg->inten_fall_mask << reg->inten_fall_shift),
+			(reg->inten_fall_mask << reg->intclr_fall_shift),
 				data->base + reg->tmu_intclear);
 
 		/* if last threshold limit is also present */
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index b364c9e..7c6c34a 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -134,6 +134,7 @@ enum soc_type {
  * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
  * @tmu_intstat: Register containing the interrupt status values.
  * @tmu_intclear: Register for clearing the raised interrupt status.
+ * @intclr_fall_shift: shift bits for interrupt clear fall 0
  * @emul_con: TMU emulation controller register.
  * @emul_temp_shift: shift bits of emulation temperature.
  * @emul_time_shift: shift bits of emulation time.
@@ -204,6 +205,7 @@ struct exynos_tmu_registers {
 	u32	tmu_intstat;
 
 	u32	tmu_intclear;
+	u32	intclr_fall_shift;
 
 	u32	emul_con;
 	u32	emul_temp_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 9002499..23fea23 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
 	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 	.emul_con = EXYNOS_EMUL_CON,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index dc7feb5..8788a87 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -69,9 +69,10 @@
 #define EXYNOS_TMU_RISE_INT_MASK	0x111
 #define EXYNOS_TMU_RISE_INT_SHIFT	0
 #define EXYNOS_TMU_FALL_INT_MASK	0x111
-#define EXYNOS_TMU_FALL_INT_SHIFT	12
+#define EXYNOS_TMU_FALL_INT_SHIFT	16
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
+#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
-- 
1.7.9.5

[PATCH 2/3] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Chatradhi]

On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.

To support that, we introduced a SHARED_MEMORY flag in the
driver and the 2nd set of register base and size are provided
in the "reg" property of the node.

As per Amit's suggestion, this patch changes the base_common
to base_second.
https://lkml.org/lkml/2013/8/1/38

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
 .../devicetree/bindings/thermal/exynos-thermal.txt |    4 ++--
 drivers/thermal/samsung/exynos_tmu.c               |   10 +++++-----
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 284f530..116cca0 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -11,8 +11,8 @@
 - reg : Address range of the thermal registers. For soc's which has multiple
 	instances of TMU and some registers are shared across all TMU's like
 	interrupt related then 2 set of register has to supplied. First set
-	belongs	to each instance of TMU and second set belongs to common TMU
-	registers.
+	belongs	to each instance of TMU and second set belongs to second set
+	of common TMU registers.
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index d201ed8..c56f7e5 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -41,7 +41,7 @@
  * @id: identifier of the one instance of the TMU controller.
  * @pdata: pointer to the tmu platform/configuration data
  * @base: base address of the single instance of the TMU controller.
- * @base_common: base address of the common registers of the TMU controller.
+ * @base_second: base address of the common registers of the TMU controller.
  * @irq: irq number of the TMU controller.
  * @soc: id of the SOC type.
  * @irq_work: pointer to the irq work structure.
@@ -56,7 +56,7 @@ struct exynos_tmu_data {
 	int id;
 	struct exynos_tmu_platform_data *pdata;
 	void __iomem *base;
-	void __iomem *base_common;
+	void __iomem *base_second;
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -297,7 +297,7 @@ skip_calib_data:
 	}
 	/*Clear the PMIN in the common TMU register*/
 	if (reg->tmu_pmin && !data->id)
-		writel(0, data->base_common + reg->tmu_pmin);
+		writel(0, data->base_second + reg->tmu_pmin);
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
@@ -451,7 +451,7 @@ static void exynos_tmu_work(struct work_struct *work)
 
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
-		val_type = readl(data->base_common + reg->tmu_irqstatus);
+		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
@@ -590,7 +590,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	data->base_common = devm_ioremap(&pdev->dev, res.start,
+	data->base_second = devm_ioremap(&pdev->dev, res.start,
 					resource_size(&res));
 	if (!data->base) {
 		dev_err(&pdev->dev, "Failed to ioremap memory\n");
-- 
1.7.9.5

[PATCH v2: 3/3] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Chatradhi]

This patch adds the neccessary register changes and arch information
to support Exynos5420 SoCs
Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU

Note: The platform data structure will be handled properly once the driver
 moves to complete device driver solution.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
1. modified the platform data structure in order to pass SHARED flag
   for channels that need sharing of address space.
2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
   As the changes are minimum and can be added here.

 drivers/thermal/samsung/exynos_tmu.c      |   14 +++-
 drivers/thermal/samsung/exynos_tmu.h      |    1 +
 drivers/thermal/samsung/exynos_tmu_data.c |  130 +++++++++++++++++++++++++++++
 drivers/thermal/samsung/exynos_tmu_data.h |    7 ++
 4 files changed, 150 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index c56f7e5..d57a4e2 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -186,7 +186,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
 		}
 	} else {
-		trim_info = readl(data->base + reg->triminfo_data);
+		/* On exynos5420 the triminfo register is in the shared space */
+		if (data->base_second && (data->soc == SOC_ARCH_EXYNOS5420))
+			trim_info = readl(data->base_second +
+							reg->triminfo_data);
+		else
+			trim_info = readl(data->base + reg->triminfo_data);
 	}
 	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
@@ -499,6 +504,10 @@ static const struct of_device_id exynos_tmu_match[] = {
 		.compatible = "samsung,exynos5440-tmu",
 		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
 	},
+	{
+		.compatible = "samsung,exynos5420-tmu",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
@@ -637,7 +646,8 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 
 	if (pdata->type == SOC_ARCH_EXYNOS ||
 		pdata->type == SOC_ARCH_EXYNOS4210 ||
-				pdata->type == SOC_ARCH_EXYNOS5440)
+				pdata->type == SOC_ARCH_EXYNOS5440 ||
+				pdata->type == SOC_ARCH_EXYNOS5420)
 		data->soc = pdata->type;
 	else {
 		ret = -EINVAL;
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 7c6c34a..d88a536 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -43,6 +43,7 @@ enum soc_type {
 	SOC_ARCH_EXYNOS4210 = 1,
 	SOC_ARCH_EXYNOS,
 	SOC_ARCH_EXYNOS5440,
+	SOC_ARCH_EXYNOS5420,
 };
 
 /**
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 23fea23..c3cdfbb 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -177,6 +177,136 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+static const struct exynos_tmu_registers exynos5420_tmu_registers = {
+	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+	.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+	.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+	.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+	.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+	.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+	.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+	.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+	.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+	.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+	.tmu_status = EXYNOS_TMU_REG_STATUS,
+	.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
+	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
+	.tmu_inten = EXYNOS_TMU_REG_INTEN,
+	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
+	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+	/* INTEN_RISE3 Not availble in exynos5420 */
+	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
+	.emul_con = EXYNOS_EMUL_CON,
+	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+	.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define EXYNOS5420_TMU_DATA \
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.type = SOC_ARCH_EXYNOS5420, \
+	.registers = &exynos5420_tmu_registers, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME)
+
+#define EXYNOS5420_TMU_DATA_SHARED \
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.type = SOC_ARCH_EXYNOS5420, \
+	.registers = &exynos5420_tmu_registers, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_SHARED_MEMORY)
+
+struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
+	.tmu_data = {
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+	},
+	.tmu_count = 5,
+};
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index 8788a87..3ce94cd 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -153,4 +153,11 @@ extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
 #define EXYNOS5440_TMU_DRV_DATA (NULL)
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
+#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
+#else
+#define EXYNOS5420_TMU_DRV_DATA (NULL)
+#endif
+
 #endif /*_EXYNOS_TMU_DATA_H*/
-- 
1.7.9.5

Re: [PATCH 2/3] thermal: samsung: Add TMU support for Exynos5420 SoCs

[amit daniel kachhap]

On Wed, Aug 28, 2013 at 11:15 AM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> This patch adds the neccessary register changes and arch information
> to support Exynos5420 SoCs
> Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
For all patch in this series,
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>.

A minor comment, please rename the flag SHARED_MEMORY to
MULTIPLE_MEMORY as this is more consistent.

Thanks,
Amit Daniel
> ---
>  drivers/thermal/samsung/exynos_tmu.c      |    4 ++
>  drivers/thermal/samsung/exynos_tmu.h      |    1 +
>  drivers/thermal/samsung/exynos_tmu_data.c |   90 +++++++++++++++++++++++++++++
>  drivers/thermal/samsung/exynos_tmu_data.h |    7 +++
>  4 files changed, 102 insertions(+)
>
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index d201ed8..bfdfbd6 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -499,6 +499,10 @@ static const struct of_device_id exynos_tmu_match[] = {
>                 .compatible = "samsung,exynos5440-tmu",
>                 .data = (void *)EXYNOS5440_TMU_DRV_DATA,
>         },
> +       {
> +               .compatible = "samsung,exynos5420-tmu",
> +               .data = (void *)EXYNOS5420_TMU_DRV_DATA,
> +       },
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, exynos_tmu_match);
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 7c6c34a..d88a536 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -43,6 +43,7 @@ enum soc_type {
>         SOC_ARCH_EXYNOS4210 = 1,
>         SOC_ARCH_EXYNOS,
>         SOC_ARCH_EXYNOS5440,
> +       SOC_ARCH_EXYNOS5420,
>  };
>
>  /**
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 23fea23..5adbb36 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -177,6 +177,96 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
>  };
>  #endif
>
> +#if defined(CONFIG_SOC_EXYNOS5420)
> +static const struct exynos_tmu_registers exynos5420_tmu_registers = {
> +       .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
> +       .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
> +       .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
> +       .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
> +       .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
> +       .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
> +       .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
> +       .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
> +       .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
> +       .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
> +       .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
> +       .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
> +       .tmu_status = EXYNOS_TMU_REG_STATUS,
> +       .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
> +       .threshold_th0 = EXYNOS_THD_TEMP_RISE,
> +       .threshold_th1 = EXYNOS_THD_TEMP_FALL,
> +       .tmu_inten = EXYNOS_TMU_REG_INTEN,
> +       .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> +       .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> +       .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
> +       .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
> +       .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
> +       .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
> +       .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
> +       /* INTEN_RISE3 Not availble in exynos5420 */
> +       .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
> +       .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
> +       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
> +       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +       .intclr_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
> +       .emul_con = EXYNOS_EMUL_CON,
> +       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> +       .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> +       .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
> +};
> +
> +#define EXYNOS5420_TMU_DATA \
> +       .threshold_falling = 10, \
> +       .trigger_levels[0] = 85, \
> +       .trigger_levels[1] = 103, \
> +       .trigger_levels[2] = 110, \
> +       .trigger_levels[3] = 120, \
> +       .trigger_enable[0] = true, \
> +       .trigger_enable[1] = true, \
> +       .trigger_enable[2] = true, \
> +       .trigger_enable[3] = false, \
> +       .trigger_type[0] = THROTTLE_ACTIVE, \
> +       .trigger_type[1] = THROTTLE_ACTIVE, \
> +       .trigger_type[2] = SW_TRIP, \
> +       .trigger_type[3] = HW_TRIP, \
> +       .max_trigger_level = 4, \
> +       .gain = 8, \
> +       .reference_voltage = 16, \
> +       .noise_cancel_mode = 4, \
> +       .cal_type = TYPE_ONE_POINT_TRIMMING, \
> +       .efuse_value = 55, \
> +       .min_efuse_value = 40, \
> +       .max_efuse_value = 100, \
> +       .first_point_trim = 25, \
> +       .second_point_trim = 85, \
> +       .default_temp_offset = 50, \
> +       .freq_tab[0] = { \
> +               .freq_clip_max = 800 * 1000, \
> +               .temp_level = 85, \
> +       }, \
> +       .freq_tab[1] = { \
> +               .freq_clip_max = 200 * 1000, \
> +               .temp_level = 103, \
> +       }, \
> +       .freq_tab_count = 2, \
> +       .type = SOC_ARCH_EXYNOS5420, \
> +       .registers = &exynos5420_tmu_registers, \
> +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +                       TMU_SUPPORT_EMUL_TIME)
> +
> +struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
> +       .tmu_data = {
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA },
> +       },
> +       .tmu_count = 5,
> +};
> +#endif
> +
>  #if defined(CONFIG_SOC_EXYNOS5440)
>  static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> index 8788a87..3ce94cd 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> @@ -153,4 +153,11 @@ extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
>  #define EXYNOS5440_TMU_DRV_DATA (NULL)
>  #endif
>
> +#if defined(CONFIG_SOC_EXYNOS5420)
> +extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
> +#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
> +#else
> +#define EXYNOS5420_TMU_DRV_DATA (NULL)
> +#endif
> +
>  #endif /*_EXYNOS_TMU_DATA_H*/
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at  http://www.tux.org/lkml/

Re: [PATCH 3/3] thermal: exynos: Handle the misplaced TRIMINFO register

[Bartlomiej Zolnierkiewicz]

Hi,

On Wednesday, August 28, 2013 11:15:19 AM Naveen Krishna Chatradhi wrote:
> This patch adds code to handle the misplaced TRIMINFO register
> incase of Exynos5420.
> 
> On Exynos5420 we have a TRIMINFO register being misplaced for
> TMU channels 2, 3 and 4
> 
> TRIMINFO at 0x1006c000 contains data for TMU channel 3
> TRIMINFO at 0x100a0000 contains data for TMU channel 4
> TRIMINFO at 0x10068000 contains data for TMU channel 2
> 
> The misplaced register address is passed through devicetree and
> map it seperately during probe.
> Also, adds the documentation under devicetree/bindings/thermal/
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   21 +++++++++++++
>  drivers/thermal/samsung/exynos_tmu.c               |   32 +++++++++++++++++---
>  2 files changed, 49 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 284f530..e818473 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -7,12 +7,21 @@
>  	       "samsung,exynos4210-tmu"
>  	       "samsung,exynos5250-tmu"
>  	       "samsung,exynos5440-tmu"
> +	       "samsung,exynos5420-tmu"
>  - interrupt-parent : The phandle for the interrupt controller
>  - reg : Address range of the thermal registers. For soc's which has multiple
>  	instances of TMU and some registers are shared across all TMU's like
>  	interrupt related then 2 set of register has to supplied. First set
>  	belongs	to each instance of TMU and second set belongs to common TMU
>  	registers.
> +
> + ** NOTE FOR EXYNOS5420 **
> +    TRIMINFO register is being misplaced for TMU channels 2, 3 and 4
> +
> +    TERMINFO for TMU channel 2 is present in address space of TMU channel 3
> +    TERMINFO for TMU channel 3 is present in address space of TMU channel 4
> +    TERMINFO for TMU channel 4 is present in address space of TMU channel 2
> +
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> @@ -43,6 +52,18 @@ Example 2):
>  		clock-names = "tmu_apbif";
>  	};
>  
> +Example 3): In case of Exynos5420 TMU channel 3
> +
> +	/* tmu for CPU3 */
> +	tmu@1006c000 {
> +		compatible = "samsung,exynos5420-tmu";
> +		/* 2nd reg is for the misplaced TRIMINFO register */
> +		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
> +		interrupts = <0 185 0>;
> +		clocks = <&clock 318>;
> +		clock-names = "tmu_apbif";
> +	};
> +
>  Note: For multi-instance tmu each instance should have an alias correctly
>  numbered in "aliases" node.
>  
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index bfdfbd6..f95844e 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -42,6 +42,7 @@
>   * @pdata: pointer to the tmu platform/configuration data
>   * @base: base address of the single instance of the TMU controller.
>   * @base_common: base address of the common registers of the TMU controller.
> + * @triminfo_base: misplaced register base for TRIMINFO on Exynos5420 only
>   * @irq: irq number of the TMU controller.
>   * @soc: id of the SOC type.
>   * @irq_work: pointer to the irq work structure.
> @@ -57,6 +58,7 @@ struct exynos_tmu_data {
>  	struct exynos_tmu_platform_data *pdata;
>  	void __iomem *base;
>  	void __iomem *base_common;
> +	void __iomem *triminfo_base;		/* Needed only Exynos5420 */
>  	int irq;
>  	enum soc_type soc;
>  	struct work_struct irq_work;
> @@ -186,7 +188,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>  			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>  		}
>  	} else {
> -		trim_info = readl(data->base + reg->triminfo_data);
> +		/* On exynos5420 TRIMINFO is misplaced for some channels */
> +		if (data->triminfo_base)
> +			trim_info = readl(data->triminfo_base +
> +						reg->triminfo_data);
> +		else
> +			trim_info = readl(data->base + reg->triminfo_data);

If you always set data->triminfo_base (to data->base for EXYNOS SoCs
different from EXYNOS420) you could simplify the code above.

>  	}
>  	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>  	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
> @@ -586,8 +593,17 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>  	 * Check if the TMU shares some registers and then try to map the
>  	 * memory of common registers.
>  	 */
> -	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
> +	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY)) {

Please use a different flag for this quirk (i.e. TRIMINFO_QUIRK) instead
of overloading SHARED_MEMORY. Then you can do:

if (TMU_SUPPORTS(pdata, TRIMINFO_QUIRK) {
	...
} else
	data->triminfo_base = data->base;

> +		/* For Exynos5420 The misplaced TERMINFO register address will
> +		 * be passed from device tree node.
> +		 *
> +		 * We cannot use devm_request_and_ioremap, as the base address
> +		 * over laps with the address space of the other TMU channel.
> +		 * Check Documentation for details
> +		 */
> +		data->triminfo_base = of_iomap(pdev->dev.of_node, 1);

Shouldn't there be a check here (for EXYNOS5420) for of_iomap()
return value != NULL  here so if somebody makes an error in device
tree description it gets caught instead of failing silently?

Please note that if you use the new features flag you wouldn't need
an extra check for EXYNOS5420.

>  		return 0;
> +	}
>  
>  	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
>  		dev_err(&pdev->dev, "failed to get Resource 1\n");
> @@ -632,12 +648,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>  	data->clk = devm_clk_get(&pdev->dev, "tmu_apbif");
>  	if (IS_ERR(data->clk)) {
>  		dev_err(&pdev->dev, "Failed to get clock\n");
> -		return  PTR_ERR(data->clk);
> +		ret = PTR_ERR(data->clk);
> +		goto err_triminfo_base;
>  	}
>  
>  	ret = clk_prepare(data->clk);
>  	if (ret)
> -		return ret;
> +		goto err_triminfo_base;
>  
>  	if (pdata->type == SOC_ARCH_EXYNOS ||
>  		pdata->type == SOC_ARCH_EXYNOS4210 ||
> @@ -707,9 +724,13 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>  	}
>  
>  	return 0;
> +
>  err_clk:
>  	clk_unprepare(data->clk);
>  	return ret;
> +err_triminfo_base:
> +	if (data->triminfo_base)
> +		iounmap(data->triminfo_base);

There is a return missing here and iounmap() is missing for err_clk.

I suspect that this code should look like:

err_clk:
	clk_unprepare(data->clk);
err_triminfo_base:
	if (data->triminfo_base)
		iounmap(data->triminfo_base);
	return ret;

>  }
>  
>  static int exynos_tmu_remove(struct platform_device *pdev)
> @@ -720,6 +741,9 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>  
>  	exynos_unregister_thermal(data->reg_conf);
>  
> +	if (data->triminfo_base)
> +		iounmap(data->triminfo_base);
> +
>  	clk_unprepare(data->clk);

It would be better to do clk_unprepare() first to keep consistency with
failure path in exynos_tmu_probe().
 
>  	if (!IS_ERR(data->regulator))

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Re: [PATCH v2: 3/3] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Bartlomiej Zolnierkiewicz]

Hi,

On Wednesday, August 28, 2013 02:46:49 PM Naveen Krishna Chatradhi wrote:
> This patch adds the neccessary register changes and arch information
> to support Exynos5420 SoCs
> Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
> 
> Note: The platform data structure will be handled properly once the driver
>  moves to complete device driver solution.
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>

OK, this is also an acceptable solution (though it seems to be worse
in terms of simplicity and long term maintainance). Anyway please ignore
my comments to v1, just remember to rename this flag (as already pointed
by out by Amit). TMU_SUPPORT_SHARED_MEMORY documentation in exynos_tmu.h
also requires an update.

> ---
> Changes since v1:
> 1. modified the platform data structure in order to pass SHARED flag
>    for channels that need sharing of address space.
> 2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
>    As the changes are minimum and can be added here.

Documentation/devicetree/bindings/thermal/exynos-thermal.txt update got
lost and it is quite important now as second address servers multiple
purposes. Please fix it.

>  drivers/thermal/samsung/exynos_tmu.c      |   14 +++-
>  drivers/thermal/samsung/exynos_tmu.h      |    1 +
>  drivers/thermal/samsung/exynos_tmu_data.c |  130 +++++++++++++++++++++++++++++
>  drivers/thermal/samsung/exynos_tmu_data.h |    7 ++
>  4 files changed, 150 insertions(+), 2 deletions(-)

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

[PATCH 1/3] thermal: samsung: correct the fall interrupt en, status bit fields

[Naveen Krishna Chatradhi]

The FALL interrupt related en, status bits are available at an offset of
16 on INTEN, INTSTAT registers and at an offset of
12 on INTCLEAR register.

This patch corrects the same for exyns5250 and exynos5440

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---

Changes since v1:
  None

 drivers/thermal/samsung/exynos_tmu.c      |    2 +-
 drivers/thermal/samsung/exynos_tmu.h      |    2 ++
 drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
 drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
 4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index ec01dfe..d201ed8 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -265,7 +265,7 @@ skip_calib_data:
 				data->base + reg->threshold_th1);
 
 		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
-			(reg->inten_fall_mask << reg->inten_fall_shift),
+			(reg->inten_fall_mask << reg->intclr_fall_shift),
 				data->base + reg->tmu_intclear);
 
 		/* if last threshold limit is also present */
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index b364c9e..7c6c34a 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -134,6 +134,7 @@ enum soc_type {
  * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
  * @tmu_intstat: Register containing the interrupt status values.
  * @tmu_intclear: Register for clearing the raised interrupt status.
+ * @intclr_fall_shift: shift bits for interrupt clear fall 0
  * @emul_con: TMU emulation controller register.
  * @emul_temp_shift: shift bits of emulation temperature.
  * @emul_time_shift: shift bits of emulation time.
@@ -204,6 +205,7 @@ struct exynos_tmu_registers {
 	u32	tmu_intstat;
 
 	u32	tmu_intclear;
+	u32	intclr_fall_shift;
 
 	u32	emul_con;
 	u32	emul_temp_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 9002499..23fea23 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
 	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 	.emul_con = EXYNOS_EMUL_CON,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index dc7feb5..8788a87 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -69,9 +69,10 @@
 #define EXYNOS_TMU_RISE_INT_MASK	0x111
 #define EXYNOS_TMU_RISE_INT_SHIFT	0
 #define EXYNOS_TMU_FALL_INT_MASK	0x111
-#define EXYNOS_TMU_FALL_INT_SHIFT	12
+#define EXYNOS_TMU_FALL_INT_SHIFT	16
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
+#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
-- 
1.7.9.5

[PATCH 2/3] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Chatradhi]

On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.

To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the "reg" property of the node.

As per Amit's suggestion, this patch changes the base_common
to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v2:
Changed the flag name from SHARED_MEMORY to ADDRESS_MULTIPLE.
https://lkml.org/lkml/2013/8/1/38

 .../devicetree/bindings/thermal/exynos-thermal.txt |    4 ++--
 drivers/thermal/samsung/exynos_tmu.c               |   12 ++++++------
 drivers/thermal/samsung/exynos_tmu.h               |    4 ++--
 drivers/thermal/samsung/exynos_tmu_data.c          |    2 +-
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 284f530..116cca0 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -11,8 +11,8 @@
 - reg : Address range of the thermal registers. For soc's which has multiple
 	instances of TMU and some registers are shared across all TMU's like
 	interrupt related then 2 set of register has to supplied. First set
-	belongs	to each instance of TMU and second set belongs to common TMU
-	registers.
+	belongs	to each instance of TMU and second set belongs to second set
+	of common TMU registers.
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index d201ed8..3a55caf 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -41,7 +41,7 @@
  * @id: identifier of the one instance of the TMU controller.
  * @pdata: pointer to the tmu platform/configuration data
  * @base: base address of the single instance of the TMU controller.
- * @base_common: base address of the common registers of the TMU controller.
+ * @base_second: base address of the common registers of the TMU controller.
  * @irq: irq number of the TMU controller.
  * @soc: id of the SOC type.
  * @irq_work: pointer to the irq work structure.
@@ -56,7 +56,7 @@ struct exynos_tmu_data {
 	int id;
 	struct exynos_tmu_platform_data *pdata;
 	void __iomem *base;
-	void __iomem *base_common;
+	void __iomem *base_second;
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -297,7 +297,7 @@ skip_calib_data:
 	}
 	/*Clear the PMIN in the common TMU register*/
 	if (reg->tmu_pmin && !data->id)
-		writel(0, data->base_common + reg->tmu_pmin);
+		writel(0, data->base_second + reg->tmu_pmin);
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
@@ -451,7 +451,7 @@ static void exynos_tmu_work(struct work_struct *work)
 
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
-		val_type = readl(data->base_common + reg->tmu_irqstatus);
+		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
@@ -582,7 +582,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 	 * Check if the TMU shares some registers and then try to map the
 	 * memory of common registers.
 	 */
-	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
+	if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
 		return 0;
 
 	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
@@ -590,7 +590,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	data->base_common = devm_ioremap(&pdev->dev, res.start,
+	data->base_second = devm_ioremap(&pdev->dev, res.start,
 					resource_size(&res));
 	if (!data->base) {
 		dev_err(&pdev->dev, "Failed to ioremap memory\n");
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 7c6c34a..ebd2ec1 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -59,7 +59,7 @@ enum soc_type {
  *			state(active/idle) can be checked.
  * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
  *			sample time.
- * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
+ * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
  *			sensors shares some common registers.
  * TMU_SUPPORT - macro to compare the above features with the supplied.
  */
@@ -69,7 +69,7 @@ enum soc_type {
 #define TMU_SUPPORT_FALLING_TRIP		BIT(3)
 #define TMU_SUPPORT_READY_STATUS		BIT(4)
 #define TMU_SUPPORT_EMUL_TIME			BIT(5)
-#define TMU_SUPPORT_SHARED_MEMORY		BIT(6)
+#define TMU_SUPPORT_ADDRESS_MULTIPLE		BIT(6)
 
 #define TMU_SUPPORTS(a, b)	(a->features & TMU_SUPPORT_ ## b)
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 23fea23..58570d0 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -239,7 +239,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.type = SOC_ARCH_EXYNOS5440, \
 	.registers = &exynos5440_tmu_registers, \
 	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
-			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
+			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 
 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 	.tmu_data = {
-- 
1.7.9.5

[PATCH 3/3] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Chatradhi]

This patch adds the neccessary register changes and arch information
to support Exynos5420 SoCs
Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU

Also updated the Documentation at
Documentation/devicetree/bindings/thermal/exynos-thermal.txt

Note: The platform data structure will be handled properly once the driver
 moves to complete device driver solution.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
1. modified the platform data structure in order to pass SHARED flag
   for channels that need sharing of address space.
2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
   As the changes are minimum and can be added here.

 .../devicetree/bindings/thermal/exynos-thermal.txt |   39 ++++++
 drivers/thermal/samsung/exynos_tmu.c               |   14 ++-
 drivers/thermal/samsung/exynos_tmu.h               |    1 +
 drivers/thermal/samsung/exynos_tmu_data.c          |  130 ++++++++++++++++++++
 drivers/thermal/samsung/exynos_tmu_data.h          |    7 ++
 5 files changed, 189 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 116cca0..d70f2a4 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -7,12 +7,23 @@
 	       "samsung,exynos4210-tmu"
 	       "samsung,exynos5250-tmu"
 	       "samsung,exynos5440-tmu"
+	       "samsung,exynos5420-tmu"
 - interrupt-parent : The phandle for the interrupt controller
 - reg : Address range of the thermal registers. For soc's which has multiple
 	instances of TMU and some registers are shared across all TMU's like
 	interrupt related then 2 set of register has to supplied. First set
 	belongs	to each instance of TMU and second set belongs to second set
 	of common TMU registers.
+  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
+	channels 2, 3 and 4
+
+	TRIMINFO at 0x1006c000 contains data for TMU channel 3
+	TRIMINFO at 0x100a0000 contains data for TMU channel 4
+	TRIMINFO at 0x10068000 contains data for TMU channel 2
+
+	The misplaced register address is passed through devicetree as the
+	second base
+
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
@@ -43,6 +54,34 @@ Example 2):
 		clock-names = "tmu_apbif";
 	};
 
+Example 3): (In case of Exynos5420)
+	/* tmu for CPU2 */
+	tmu@10068000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+		interrupts = <0 184 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+	/* tmu for CPU3 */
+	tmu@1006c000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+		interrupts = <0 185 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+	/* tmu for GPU */
+	tmu@100a0000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
+		interrupts = <0 215 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
 Note: For multi-instance tmu each instance should have an alias correctly
 numbered in "aliases" node.
 
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 3a55caf..6d34652 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -186,7 +186,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
 		}
 	} else {
-		trim_info = readl(data->base + reg->triminfo_data);
+		/* On exynos5420 the triminfo register is in the shared space */
+		if (data->base_second && (data->soc == SOC_ARCH_EXYNOS5420))
+			trim_info = readl(data->base_second +
+							reg->triminfo_data);
+		else
+			trim_info = readl(data->base + reg->triminfo_data);
 	}
 	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
@@ -499,6 +504,10 @@ static const struct of_device_id exynos_tmu_match[] = {
 		.compatible = "samsung,exynos5440-tmu",
 		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
 	},
+	{
+		.compatible = "samsung,exynos5420-tmu",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, exynos_tmu_match);
@@ -637,7 +646,8 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 
 	if (pdata->type == SOC_ARCH_EXYNOS ||
 		pdata->type == SOC_ARCH_EXYNOS4210 ||
-				pdata->type == SOC_ARCH_EXYNOS5440)
+				pdata->type == SOC_ARCH_EXYNOS5440 ||
+				pdata->type == SOC_ARCH_EXYNOS5420)
 		data->soc = pdata->type;
 	else {
 		ret = -EINVAL;
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index ebd2ec1..774ab03 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -43,6 +43,7 @@ enum soc_type {
 	SOC_ARCH_EXYNOS4210 = 1,
 	SOC_ARCH_EXYNOS,
 	SOC_ARCH_EXYNOS5440,
+	SOC_ARCH_EXYNOS5420,
 };
 
 /**
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 58570d0..a6d5cb5 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -177,6 +177,136 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+static const struct exynos_tmu_registers exynos5420_tmu_registers = {
+	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+	.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+	.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+	.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+	.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+	.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+	.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+	.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+	.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+	.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+	.tmu_status = EXYNOS_TMU_REG_STATUS,
+	.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
+	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
+	.tmu_inten = EXYNOS_TMU_REG_INTEN,
+	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
+	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+	/* INTEN_RISE3 Not availble in exynos5420 */
+	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
+	.emul_con = EXYNOS_EMUL_CON,
+	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+	.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define EXYNOS5420_TMU_DATA \
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.type = SOC_ARCH_EXYNOS5420, \
+	.registers = &exynos5420_tmu_registers, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME)
+
+#define EXYNOS5420_TMU_DATA_SHARED \
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.type = SOC_ARCH_EXYNOS5420, \
+	.registers = &exynos5420_tmu_registers, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
+
+struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
+	.tmu_data = {
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+	},
+	.tmu_count = 5,
+};
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index 8788a87..3ce94cd 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -153,4 +153,11 @@ extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
 #define EXYNOS5440_TMU_DRV_DATA (NULL)
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
+#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
+#else
+#define EXYNOS5420_TMU_DRV_DATA (NULL)
+#endif
+
 #endif /*_EXYNOS_TMU_DATA_H*/
-- 
1.7.9.5

Re: [PATCH 2/3] thermal: samsung: change base_common to more meaningful base_second

[amit daniel kachhap]

On Wed, Sep 4, 2013 at 9:53 AM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> On Exynos5440 and Exynos5420 there are registers common
> across the TMU channels.
>
> To support that, we introduced a ADDRESS_MULTIPLE flag in the
> driver and the 2nd set of register base and size are provided
> in the "reg" property of the node.
>
> As per Amit's suggestion, this patch changes the base_common
> to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
The changes look good. For all the 3 patches in the series,

Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: Amit Daniel Kachhap<amit.daniel@samsung.com>

Thanks,
Amit Daniel
> ---
> Changes since v2:
> Changed the flag name from SHARED_MEMORY to ADDRESS_MULTIPLE.
> https://lkml.org/lkml/2013/8/1/38
>
>  .../devicetree/bindings/thermal/exynos-thermal.txt |    4 ++--
>  drivers/thermal/samsung/exynos_tmu.c               |   12 ++++++------
>  drivers/thermal/samsung/exynos_tmu.h               |    4 ++--
>  drivers/thermal/samsung/exynos_tmu_data.c          |    2 +-
>  4 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 284f530..116cca0 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -11,8 +11,8 @@
>  - reg : Address range of the thermal registers. For soc's which has multiple
>         instances of TMU and some registers are shared across all TMU's like
>         interrupt related then 2 set of register has to supplied. First set
> -       belongs to each instance of TMU and second set belongs to common TMU
> -       registers.
> +       belongs to each instance of TMU and second set belongs to second set
> +       of common TMU registers.
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index d201ed8..3a55caf 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -41,7 +41,7 @@
>   * @id: identifier of the one instance of the TMU controller.
>   * @pdata: pointer to the tmu platform/configuration data
>   * @base: base address of the single instance of the TMU controller.
> - * @base_common: base address of the common registers of the TMU controller.
> + * @base_second: base address of the common registers of the TMU controller.
>   * @irq: irq number of the TMU controller.
>   * @soc: id of the SOC type.
>   * @irq_work: pointer to the irq work structure.
> @@ -56,7 +56,7 @@ struct exynos_tmu_data {
>         int id;
>         struct exynos_tmu_platform_data *pdata;
>         void __iomem *base;
> -       void __iomem *base_common;
> +       void __iomem *base_second;
>         int irq;
>         enum soc_type soc;
>         struct work_struct irq_work;
> @@ -297,7 +297,7 @@ skip_calib_data:
>         }
>         /*Clear the PMIN in the common TMU register*/
>         if (reg->tmu_pmin && !data->id)
> -               writel(0, data->base_common + reg->tmu_pmin);
> +               writel(0, data->base_second + reg->tmu_pmin);
>  out:
>         clk_disable(data->clk);
>         mutex_unlock(&data->lock);
> @@ -451,7 +451,7 @@ static void exynos_tmu_work(struct work_struct *work)
>
>         /* Find which sensor generated this interrupt */
>         if (reg->tmu_irqstatus) {
> -               val_type = readl(data->base_common + reg->tmu_irqstatus);
> +               val_type = readl(data->base_second + reg->tmu_irqstatus);
>                 if (!((val_type >> data->id) & 0x1))
>                         goto out;
>         }
> @@ -582,7 +582,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>          * Check if the TMU shares some registers and then try to map the
>          * memory of common registers.
>          */
> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
> +       if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
>                 return 0;
>
>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
> @@ -590,7 +590,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>                 return -ENODEV;
>         }
>
> -       data->base_common = devm_ioremap(&pdev->dev, res.start,
> +       data->base_second = devm_ioremap(&pdev->dev, res.start,
>                                         resource_size(&res));
>         if (!data->base) {
>                 dev_err(&pdev->dev, "Failed to ioremap memory\n");
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 7c6c34a..ebd2ec1 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -59,7 +59,7 @@ enum soc_type {
>   *                     state(active/idle) can be checked.
>   * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
>   *                     sample time.
> - * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
> + * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
>   *                     sensors shares some common registers.
>   * TMU_SUPPORT - macro to compare the above features with the supplied.
>   */
> @@ -69,7 +69,7 @@ enum soc_type {
>  #define TMU_SUPPORT_FALLING_TRIP               BIT(3)
>  #define TMU_SUPPORT_READY_STATUS               BIT(4)
>  #define TMU_SUPPORT_EMUL_TIME                  BIT(5)
> -#define TMU_SUPPORT_SHARED_MEMORY              BIT(6)
> +#define TMU_SUPPORT_ADDRESS_MULTIPLE           BIT(6)
>
>  #define TMU_SUPPORTS(a, b)     (a->features & TMU_SUPPORT_ ## b)
>
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 23fea23..58570d0 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -239,7 +239,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .type = SOC_ARCH_EXYNOS5440, \
>         .registers = &exynos5440_tmu_registers, \
>         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
> -                       TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
> +                       TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
>
>  struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
>         .tmu_data = {
> --
> 1.7.9.5
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-pm" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 3/3] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Ch]

On 4 September 2013 09:53, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> This patch adds the neccessary register changes and arch information
> to support Exynos5420 SoCs
> Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
>
> Also updated the Documentation at
> Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>
> Note: The platform data structure will be handled properly once the driver
>  moves to complete device driver solution.
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> Changes since v1:
> 1. modified the platform data structure in order to pass SHARED flag
>    for channels that need sharing of address space.
> 2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
>    As the changes are minimum and can be added here.
>
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   39 ++++++
>  drivers/thermal/samsung/exynos_tmu.c               |   14 ++-
>  drivers/thermal/samsung/exynos_tmu.h               |    1 +
>  drivers/thermal/samsung/exynos_tmu_data.c          |  130 ++++++++++++++++++++
>  drivers/thermal/samsung/exynos_tmu_data.h          |    7 ++
>  5 files changed, 189 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 116cca0..d70f2a4 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -7,12 +7,23 @@
>                "samsung,exynos4210-tmu"
>                "samsung,exynos5250-tmu"
>                "samsung,exynos5440-tmu"
> +              "samsung,exynos5420-tmu"
>  - interrupt-parent : The phandle for the interrupt controller
>  - reg : Address range of the thermal registers. For soc's which has multiple
>         instances of TMU and some registers are shared across all TMU's like
>         interrupt related then 2 set of register has to supplied. First set
>         belongs to each instance of TMU and second set belongs to second set
>         of common TMU registers.
> +  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
> +       channels 2, 3 and 4
> +
> +       TRIMINFO at 0x1006c000 contains data for TMU channel 3
> +       TRIMINFO at 0x100a0000 contains data for TMU channel 4
> +       TRIMINFO at 0x10068000 contains data for TMU channel 2
> +
> +       The misplaced register address is passed through devicetree as the
> +       second base
> +
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> @@ -43,6 +54,34 @@ Example 2):
>                 clock-names = "tmu_apbif";
>         };
>
> +Example 3): (In case of Exynos5420)
> +       /* tmu for CPU2 */
> +       tmu@10068000 {
> +               compatible = "samsung,exynos5420-tmu";
> +               reg = <0x10068000 0x100>, <0x1006c000 0x4>;
> +               interrupts = <0 184 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif";
> +       };
> +
> +       /* tmu for CPU3 */
> +       tmu@1006c000 {
> +               compatible = "samsung,exynos5420-tmu";
> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
> +               interrupts = <0 185 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif";
> +       };
> +
> +       /* tmu for GPU */
> +       tmu@100a0000 {
> +               compatible = "samsung,exynos5420-tmu";
> +               reg = <0x100a0000 0x100>, <0x10068000 0x4>;
> +               interrupts = <0 215 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif";
> +       };
> +
>  Note: For multi-instance tmu each instance should have an alias correctly
>  numbered in "aliases" node.
>
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index 3a55caf..6d34652 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -186,7 +186,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>                 }
>         } else {
> -               trim_info = readl(data->base + reg->triminfo_data);
> +               /* On exynos5420 the triminfo register is in the shared space */
> +               if (data->base_second && (data->soc == SOC_ARCH_EXYNOS5420))
> +                       trim_info = readl(data->base_second +
> +                                                       reg->triminfo_data);
> +               else
> +                       trim_info = readl(data->base + reg->triminfo_data);
>         }
>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
> @@ -499,6 +504,10 @@ static const struct of_device_id exynos_tmu_match[] = {
>                 .compatible = "samsung,exynos5440-tmu",
>                 .data = (void *)EXYNOS5440_TMU_DRV_DATA,
>         },
> +       {
> +               .compatible = "samsung,exynos5420-tmu",
> +               .data = (void *)EXYNOS5420_TMU_DRV_DATA,
> +       },
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, exynos_tmu_match);
> @@ -637,7 +646,8 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>
>         if (pdata->type == SOC_ARCH_EXYNOS ||
>                 pdata->type == SOC_ARCH_EXYNOS4210 ||
> -                               pdata->type == SOC_ARCH_EXYNOS5440)
> +                               pdata->type == SOC_ARCH_EXYNOS5440 ||
> +                               pdata->type == SOC_ARCH_EXYNOS5420)
>                 data->soc = pdata->type;
>         else {
>                 ret = -EINVAL;
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index ebd2ec1..774ab03 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -43,6 +43,7 @@ enum soc_type {
>         SOC_ARCH_EXYNOS4210 = 1,
>         SOC_ARCH_EXYNOS,
>         SOC_ARCH_EXYNOS5440,
> +       SOC_ARCH_EXYNOS5420,
>  };
>
>  /**
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 58570d0..a6d5cb5 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -177,6 +177,136 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
>  };
>  #endif
>
> +#if defined(CONFIG_SOC_EXYNOS5420)
> +static const struct exynos_tmu_registers exynos5420_tmu_registers = {
> +       .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
> +       .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
> +       .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
> +       .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
> +       .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
> +       .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
> +       .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
> +       .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
> +       .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
> +       .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
> +       .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
> +       .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
> +       .tmu_status = EXYNOS_TMU_REG_STATUS,
> +       .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
> +       .threshold_th0 = EXYNOS_THD_TEMP_RISE,
> +       .threshold_th1 = EXYNOS_THD_TEMP_FALL,
> +       .tmu_inten = EXYNOS_TMU_REG_INTEN,
> +       .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> +       .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> +       .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
> +       .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
> +       .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
> +       .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
> +       .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
> +       /* INTEN_RISE3 Not availble in exynos5420 */
> +       .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
> +       .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
> +       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
> +       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +       .intclr_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
> +       .emul_con = EXYNOS_EMUL_CON,
> +       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> +       .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> +       .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
> +};
> +
> +#define EXYNOS5420_TMU_DATA \
> +       .threshold_falling = 10, \
> +       .trigger_levels[0] = 85, \
> +       .trigger_levels[1] = 103, \
> +       .trigger_levels[2] = 110, \
> +       .trigger_levels[3] = 120, \
> +       .trigger_enable[0] = true, \
> +       .trigger_enable[1] = true, \
> +       .trigger_enable[2] = true, \
> +       .trigger_enable[3] = false, \
> +       .trigger_type[0] = THROTTLE_ACTIVE, \
> +       .trigger_type[1] = THROTTLE_ACTIVE, \
> +       .trigger_type[2] = SW_TRIP, \
> +       .trigger_type[3] = HW_TRIP, \
> +       .max_trigger_level = 4, \
> +       .gain = 8, \
> +       .reference_voltage = 16, \
> +       .noise_cancel_mode = 4, \
> +       .cal_type = TYPE_ONE_POINT_TRIMMING, \
> +       .efuse_value = 55, \
> +       .min_efuse_value = 40, \
> +       .max_efuse_value = 100, \
> +       .first_point_trim = 25, \
> +       .second_point_trim = 85, \
> +       .default_temp_offset = 50, \
> +       .freq_tab[0] = { \
> +               .freq_clip_max = 800 * 1000, \
> +               .temp_level = 85, \
> +       }, \
> +       .freq_tab[1] = { \
> +               .freq_clip_max = 200 * 1000, \
> +               .temp_level = 103, \
> +       }, \
> +       .freq_tab_count = 2, \
> +       .type = SOC_ARCH_EXYNOS5420, \
> +       .registers = &exynos5420_tmu_registers, \
> +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +                       TMU_SUPPORT_EMUL_TIME)
> +
> +#define EXYNOS5420_TMU_DATA_SHARED \
> +       .threshold_falling = 10, \
> +       .trigger_levels[0] = 85, \
> +       .trigger_levels[1] = 103, \
> +       .trigger_levels[2] = 110, \
> +       .trigger_levels[3] = 120, \
> +       .trigger_enable[0] = true, \
> +       .trigger_enable[1] = true, \
> +       .trigger_enable[2] = true, \
> +       .trigger_enable[3] = false, \
> +       .trigger_type[0] = THROTTLE_ACTIVE, \
> +       .trigger_type[1] = THROTTLE_ACTIVE, \
> +       .trigger_type[2] = SW_TRIP, \
> +       .trigger_type[3] = HW_TRIP, \
> +       .max_trigger_level = 4, \
> +       .gain = 8, \
> +       .reference_voltage = 16, \
> +       .noise_cancel_mode = 4, \
> +       .cal_type = TYPE_ONE_POINT_TRIMMING, \
> +       .efuse_value = 55, \
> +       .min_efuse_value = 40, \
> +       .max_efuse_value = 100, \
> +       .first_point_trim = 25, \
> +       .second_point_trim = 85, \
> +       .default_temp_offset = 50, \
> +       .freq_tab[0] = { \
> +               .freq_clip_max = 800 * 1000, \
> +               .temp_level = 85, \
> +       }, \
> +       .freq_tab[1] = { \
> +               .freq_clip_max = 200 * 1000, \
> +               .temp_level = 103, \
> +       }, \
> +       .freq_tab_count = 2, \
> +       .type = SOC_ARCH_EXYNOS5420, \
> +       .registers = &exynos5420_tmu_registers, \
> +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +                       TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
> +
> +struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
> +       .tmu_data = {
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA_SHARED },
> +               { EXYNOS5420_TMU_DATA_SHARED },
> +               { EXYNOS5420_TMU_DATA_SHARED },
> +       },
> +       .tmu_count = 5,
> +};
> +#endif
> +
>  #if defined(CONFIG_SOC_EXYNOS5440)
>  static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> index 8788a87..3ce94cd 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> @@ -153,4 +153,11 @@ extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
>  #define EXYNOS5440_TMU_DRV_DATA (NULL)
>  #endif
>
> +#if defined(CONFIG_SOC_EXYNOS5420)
> +extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
> +#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
> +#else
> +#define EXYNOS5420_TMU_DRV_DATA (NULL)
> +#endif
> +
>  #endif /*_EXYNOS_TMU_DATA_H*/
> --
> 1.7.9.5
Hello All,

Amit Daniel, has Acked these patches a while ago
Any other review comments or updates on this patch ??
>


Thanks & Regards,
-- 
Shine bright,
(: Nav :)

Re: [PATCH 3/3] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Bartlomiej Zolnierkiewicz]

Hi,

I would like to see few minor cleanup changes, please see below:

On Thursday, October 03, 2013 05:31:42 PM Naveen Krishna Ch wrote:
> On 4 September 2013 09:53, Naveen Krishna Chatradhi
> <ch.naveen@samsung.com> wrote:
> > This patch adds the neccessary register changes and arch information
> > to support Exynos5420 SoCs
> > Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
> >
> > Also updated the Documentation at
> > Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> >
> > Note: The platform data structure will be handled properly once the driver
> >  moves to complete device driver solution.
> >
> > Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> > ---
> > Changes since v1:
> > 1. modified the platform data structure in order to pass SHARED flag
> >    for channels that need sharing of address space.
> > 2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
> >    As the changes are minimum and can be added here.
> >
> >  .../devicetree/bindings/thermal/exynos-thermal.txt |   39 ++++++
> >  drivers/thermal/samsung/exynos_tmu.c               |   14 ++-
> >  drivers/thermal/samsung/exynos_tmu.h               |    1 +
> >  drivers/thermal/samsung/exynos_tmu_data.c          |  130 ++++++++++++++++++++
> >  drivers/thermal/samsung/exynos_tmu_data.h          |    7 ++
> >  5 files changed, 189 insertions(+), 2 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> > index 116cca0..d70f2a4 100644
> > --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> > +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> > @@ -7,12 +7,23 @@
> >                "samsung,exynos4210-tmu"
> >                "samsung,exynos5250-tmu"
> >                "samsung,exynos5440-tmu"
> > +              "samsung,exynos5420-tmu"

it should come before "samsung,exynos5440-tmu"

> >  - interrupt-parent : The phandle for the interrupt controller
> >  - reg : Address range of the thermal registers. For soc's which has multiple
> >         instances of TMU and some registers are shared across all TMU's like
> >         interrupt related then 2 set of register has to supplied. First set
> >         belongs to each instance of TMU and second set belongs to second set
> >         of common TMU registers.
> > +  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
> > +       channels 2, 3 and 4
> > +
> > +       TRIMINFO at 0x1006c000 contains data for TMU channel 3
> > +       TRIMINFO at 0x100a0000 contains data for TMU channel 4
> > +       TRIMINFO at 0x10068000 contains data for TMU channel 2
> > +
> > +       The misplaced register address is passed through devicetree as the
> > +       second base
> > +
> >  - interrupts : Should contain interrupt for thermal system
> >  - clocks : The main clock for TMU device
> >  - clock-names : Thermal system clock name
> > @@ -43,6 +54,34 @@ Example 2):
> >                 clock-names = "tmu_apbif";
> >         };
> >
> > +Example 3): (In case of Exynos5420)
> > +       /* tmu for CPU2 */
> > +       tmu@10068000 {
> > +               compatible = "samsung,exynos5420-tmu";
> > +               reg = <0x10068000 0x100>, <0x1006c000 0x4>;
> > +               interrupts = <0 184 0>;
> > +               clocks = <&clock 318>;
> > +               clock-names = "tmu_apbif";
> > +       };
> > +
> > +       /* tmu for CPU3 */
> > +       tmu@1006c000 {
> > +               compatible = "samsung,exynos5420-tmu";
> > +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
> > +               interrupts = <0 185 0>;
> > +               clocks = <&clock 318>;
> > +               clock-names = "tmu_apbif";
> > +       };
> > +
> > +       /* tmu for GPU */
> > +       tmu@100a0000 {
> > +               compatible = "samsung,exynos5420-tmu";
> > +               reg = <0x100a0000 0x100>, <0x10068000 0x4>;
> > +               interrupts = <0 215 0>;
> > +               clocks = <&clock 318>;
> > +               clock-names = "tmu_apbif";
> > +       };
> > +
> >  Note: For multi-instance tmu each instance should have an alias correctly
> >  numbered in "aliases" node.
> >
> > diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> > index 3a55caf..6d34652 100644
> > --- a/drivers/thermal/samsung/exynos_tmu.c
> > +++ b/drivers/thermal/samsung/exynos_tmu.c
> > @@ -186,7 +186,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
> >                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
> >                 }
> >         } else {
> > -               trim_info = readl(data->base + reg->triminfo_data);
> > +               /* On exynos5420 the triminfo register is in the shared space */
> > +               if (data->base_second && (data->soc == SOC_ARCH_EXYNOS5420))
> > +                       trim_info = readl(data->base_second +
> > +                                                       reg->triminfo_data);
> > +               else
> > +                       trim_info = readl(data->base + reg->triminfo_data);
> >         }
> >         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
> >         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
> > @@ -499,6 +504,10 @@ static const struct of_device_id exynos_tmu_match[] = {
> >                 .compatible = "samsung,exynos5440-tmu",
> >                 .data = (void *)EXYNOS5440_TMU_DRV_DATA,
> >         },
> > +       {
> > +               .compatible = "samsung,exynos5420-tmu",
> > +               .data = (void *)EXYNOS5420_TMU_DRV_DATA,
> > +       },

it should come before 5440 entry

> >         {},
> >  };
> >  MODULE_DEVICE_TABLE(of, exynos_tmu_match);
> > @@ -637,7 +646,8 @@ static int exynos_tmu_probe(struct platform_device *pdev)
> >
> >         if (pdata->type == SOC_ARCH_EXYNOS ||
> >                 pdata->type == SOC_ARCH_EXYNOS4210 ||
> > -                               pdata->type == SOC_ARCH_EXYNOS5440)
> > +                               pdata->type == SOC_ARCH_EXYNOS5440 ||
> > +                               pdata->type == SOC_ARCH_EXYNOS5420)

please check for 5420 before 5440

> >                 data->soc = pdata->type;
> >         else {
> >                 ret = -EINVAL;
> > diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> > index ebd2ec1..774ab03 100644
> > --- a/drivers/thermal/samsung/exynos_tmu.h
> > +++ b/drivers/thermal/samsung/exynos_tmu.h
> > @@ -43,6 +43,7 @@ enum soc_type {
> >         SOC_ARCH_EXYNOS4210 = 1,
> >         SOC_ARCH_EXYNOS,
> >         SOC_ARCH_EXYNOS5440,
> > +       SOC_ARCH_EXYNOS5420,

5420 should come before 5440

> >  };
> >
> >  /**
> > diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> > index 58570d0..a6d5cb5 100644
> > --- a/drivers/thermal/samsung/exynos_tmu_data.c
> > +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> > @@ -177,6 +177,136 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
> >  };
> >  #endif
> >
> > +#if defined(CONFIG_SOC_EXYNOS5420)
> > +static const struct exynos_tmu_registers exynos5420_tmu_registers = {
> > +       .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
> > +       .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
> > +       .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
> > +       .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
> > +       .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
> > +       .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
> > +       .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
> > +       .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
> > +       .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
> > +       .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
> > +       .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
> > +       .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
> > +       .tmu_status = EXYNOS_TMU_REG_STATUS,
> > +       .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
> > +       .threshold_th0 = EXYNOS_THD_TEMP_RISE,
> > +       .threshold_th1 = EXYNOS_THD_TEMP_FALL,
> > +       .tmu_inten = EXYNOS_TMU_REG_INTEN,
> > +       .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> > +       .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> > +       .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
> > +       .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
> > +       .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
> > +       .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
> > +       .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
> > +       /* INTEN_RISE3 Not availble in exynos5420 */
> > +       .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
> > +       .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
> > +       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
> > +       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> > +       .intclr_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
> > +       .emul_con = EXYNOS_EMUL_CON,
> > +       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> > +       .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> > +       .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
> > +};
> > +
> > +#define EXYNOS5420_TMU_DATA \
> > +       .threshold_falling = 10, \
> > +       .trigger_levels[0] = 85, \
> > +       .trigger_levels[1] = 103, \
> > +       .trigger_levels[2] = 110, \
> > +       .trigger_levels[3] = 120, \
> > +       .trigger_enable[0] = true, \
> > +       .trigger_enable[1] = true, \
> > +       .trigger_enable[2] = true, \
> > +       .trigger_enable[3] = false, \
> > +       .trigger_type[0] = THROTTLE_ACTIVE, \
> > +       .trigger_type[1] = THROTTLE_ACTIVE, \
> > +       .trigger_type[2] = SW_TRIP, \
> > +       .trigger_type[3] = HW_TRIP, \
> > +       .max_trigger_level = 4, \
> > +       .gain = 8, \
> > +       .reference_voltage = 16, \
> > +       .noise_cancel_mode = 4, \
> > +       .cal_type = TYPE_ONE_POINT_TRIMMING, \
> > +       .efuse_value = 55, \
> > +       .min_efuse_value = 40, \
> > +       .max_efuse_value = 100, \
> > +       .first_point_trim = 25, \
> > +       .second_point_trim = 85, \
> > +       .default_temp_offset = 50, \
> > +       .freq_tab[0] = { \
> > +               .freq_clip_max = 800 * 1000, \
> > +               .temp_level = 85, \
> > +       }, \
> > +       .freq_tab[1] = { \
> > +               .freq_clip_max = 200 * 1000, \
> > +               .temp_level = 103, \
> > +       }, \
> > +       .freq_tab_count = 2, \
> > +       .type = SOC_ARCH_EXYNOS5420, \
> > +       .registers = &exynos5420_tmu_registers, \
> > +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> > +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> > +                       TMU_SUPPORT_EMUL_TIME)
> > +
> > +#define EXYNOS5420_TMU_DATA_SHARED \
> > +       .threshold_falling = 10, \
> > +       .trigger_levels[0] = 85, \
> > +       .trigger_levels[1] = 103, \
> > +       .trigger_levels[2] = 110, \
> > +       .trigger_levels[3] = 120, \
> > +       .trigger_enable[0] = true, \
> > +       .trigger_enable[1] = true, \
> > +       .trigger_enable[2] = true, \
> > +       .trigger_enable[3] = false, \
> > +       .trigger_type[0] = THROTTLE_ACTIVE, \
> > +       .trigger_type[1] = THROTTLE_ACTIVE, \
> > +       .trigger_type[2] = SW_TRIP, \
> > +       .trigger_type[3] = HW_TRIP, \
> > +       .max_trigger_level = 4, \
> > +       .gain = 8, \
> > +       .reference_voltage = 16, \
> > +       .noise_cancel_mode = 4, \
> > +       .cal_type = TYPE_ONE_POINT_TRIMMING, \
> > +       .efuse_value = 55, \
> > +       .min_efuse_value = 40, \
> > +       .max_efuse_value = 100, \
> > +       .first_point_trim = 25, \
> > +       .second_point_trim = 85, \
> > +       .default_temp_offset = 50, \
> > +       .freq_tab[0] = { \
> > +               .freq_clip_max = 800 * 1000, \
> > +               .temp_level = 85, \
> > +       }, \
> > +       .freq_tab[1] = { \
> > +               .freq_clip_max = 200 * 1000, \
> > +               .temp_level = 103, \
> > +       }, \
> > +       .freq_tab_count = 2, \
> > +       .type = SOC_ARCH_EXYNOS5420, \
> > +       .registers = &exynos5420_tmu_registers, \
> > +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> > +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> > +                       TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)

EXYNOS5420_TMU_DATA and EXYNOS5420_TMU_DATA_SHARED are identical
besides .features content so to avoid code duplication please define
__EXYNOS5420_TMU_DATA with all shared entries and just do:

#define EXYNOS5420_TMU_DATA \
	__EXYNOS5420_TMU_DATA \
	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
		     TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
		     TMU_SUPPORT_EMUL_TIME)

#define EXYNOS5420_TMU_DATA_SHARED \
	__EXYNOS5420_TMU_DATA \
	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
		     TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
		     TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)

> > +struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
> > +       .tmu_data = {
> > +               { EXYNOS5420_TMU_DATA },
> > +               { EXYNOS5420_TMU_DATA },
> > +               { EXYNOS5420_TMU_DATA_SHARED },
> > +               { EXYNOS5420_TMU_DATA_SHARED },
> > +               { EXYNOS5420_TMU_DATA_SHARED },
> > +       },
> > +       .tmu_count = 5,
> > +};
> > +#endif
> > +
> >  #if defined(CONFIG_SOC_EXYNOS5440)
> >  static const struct exynos_tmu_registers exynos5440_tmu_registers = {
> >         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
> > diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> > index 8788a87..3ce94cd 100644
> > --- a/drivers/thermal/samsung/exynos_tmu_data.h
> > +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> > @@ -153,4 +153,11 @@ extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
> >  #define EXYNOS5440_TMU_DRV_DATA (NULL)
> >  #endif
> >
> > +#if defined(CONFIG_SOC_EXYNOS5420)
> > +extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
> > +#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
> > +#else
> > +#define EXYNOS5420_TMU_DRV_DATA (NULL)
> > +#endif

this should come before 5440 entry

> >  #endif /*_EXYNOS_TMU_DATA_H*/
> > --
> > 1.7.9.5
> Hello All,
> 
> Amit Daniel, has Acked these patches a while ago
> Any other review comments or updates on this patch ??
> >
> 
> 
> Thanks & Regards,

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Re: [PATCH 3/3] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Ch]

Hello Bartlomiej,

On 3 October 2013 18:12, Bartlomiej Zolnierkiewicz
<b.zolnierkie@samsung.com> wrote:
>
> Hi,
>
> I would like to see few minor cleanup changes, please see below:
Sure.
>
> On Thursday, October 03, 2013 05:31:42 PM Naveen Krishna Ch wrote:
>> On 4 September 2013 09:53, Naveen Krishna Chatradhi
>> <ch.naveen@samsung.com> wrote:
>> > This patch adds the neccessary register changes and arch information
>> > to support Exynos5420 SoCs
>> > Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
>> >
>> > Also updated the Documentation at
>> > Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> >
>> > Note: The platform data structure will be handled properly once the driver
>> >  moves to complete device driver solution.
>> >
>> > Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> > ---
>> > Changes since v1:
>> > 1. modified the platform data structure in order to pass SHARED flag
>> >    for channels that need sharing of address space.
>> > 2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
>> >    As the changes are minimum and can be added here.
>> >
>> >  .../devicetree/bindings/thermal/exynos-thermal.txt |   39 ++++++
>> >  drivers/thermal/samsung/exynos_tmu.c               |   14 ++-
>> >  drivers/thermal/samsung/exynos_tmu.h               |    1 +
>> >  drivers/thermal/samsung/exynos_tmu_data.c          |  130 ++++++++++++++++++++
>> >  drivers/thermal/samsung/exynos_tmu_data.h          |    7 ++
>> >  5 files changed, 189 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> > index 116cca0..d70f2a4 100644
>> > --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> > +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> > @@ -7,12 +7,23 @@
>> >                "samsung,exynos4210-tmu"
>> >                "samsung,exynos5250-tmu"
>> >                "samsung,exynos5440-tmu"
>> > +              "samsung,exynos5420-tmu"
>
> it should come before "samsung,exynos5440-tmu"
Done
>
>> >  - interrupt-parent : The phandle for the interrupt controller
>> >  - reg : Address range of the thermal registers. For soc's which has multiple
>> >         instances of TMU and some registers are shared across all TMU's like
>> >         interrupt related then 2 set of register has to supplied. First set
>> >         belongs to each instance of TMU and second set belongs to second set
>> >         of common TMU registers.
>> > +  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
>> > +       channels 2, 3 and 4
>> > +
>> > +       TRIMINFO at 0x1006c000 contains data for TMU channel 3
>> > +       TRIMINFO at 0x100a0000 contains data for TMU channel 4
>> > +       TRIMINFO at 0x10068000 contains data for TMU channel 2
>> > +
>> > +       The misplaced register address is passed through devicetree as the
>> > +       second base
>> > +
>> >  - interrupts : Should contain interrupt for thermal system
>> >  - clocks : The main clock for TMU device
>> >  - clock-names : Thermal system clock name
>> > @@ -43,6 +54,34 @@ Example 2):
>> >                 clock-names = "tmu_apbif";
>> >         };
>> >
>> > +Example 3): (In case of Exynos5420)
>> > +       /* tmu for CPU2 */
>> > +       tmu@10068000 {
>> > +               compatible = "samsung,exynos5420-tmu";
>> > +               reg = <0x10068000 0x100>, <0x1006c000 0x4>;
>> > +               interrupts = <0 184 0>;
>> > +               clocks = <&clock 318>;
>> > +               clock-names = "tmu_apbif";
>> > +       };
>> > +
>> > +       /* tmu for CPU3 */
>> > +       tmu@1006c000 {
>> > +               compatible = "samsung,exynos5420-tmu";
>> > +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>> > +               interrupts = <0 185 0>;
>> > +               clocks = <&clock 318>;
>> > +               clock-names = "tmu_apbif";
>> > +       };
>> > +
>> > +       /* tmu for GPU */
>> > +       tmu@100a0000 {
>> > +               compatible = "samsung,exynos5420-tmu";
>> > +               reg = <0x100a0000 0x100>, <0x10068000 0x4>;
>> > +               interrupts = <0 215 0>;
>> > +               clocks = <&clock 318>;
>> > +               clock-names = "tmu_apbif";
>> > +       };
>> > +
>> >  Note: For multi-instance tmu each instance should have an alias correctly
>> >  numbered in "aliases" node.
>> >
>> > diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>> > index 3a55caf..6d34652 100644
>> > --- a/drivers/thermal/samsung/exynos_tmu.c
>> > +++ b/drivers/thermal/samsung/exynos_tmu.c
>> > @@ -186,7 +186,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>> >                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>> >                 }
>> >         } else {
>> > -               trim_info = readl(data->base + reg->triminfo_data);
>> > +               /* On exynos5420 the triminfo register is in the shared space */
>> > +               if (data->base_second && (data->soc == SOC_ARCH_EXYNOS5420))
>> > +                       trim_info = readl(data->base_second +
>> > +                                                       reg->triminfo_data);
>> > +               else
>> > +                       trim_info = readl(data->base + reg->triminfo_data);
>> >         }
>> >         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>> >         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
>> > @@ -499,6 +504,10 @@ static const struct of_device_id exynos_tmu_match[] = {
>> >                 .compatible = "samsung,exynos5440-tmu",
>> >                 .data = (void *)EXYNOS5440_TMU_DRV_DATA,
>> >         },
>> > +       {
>> > +               .compatible = "samsung,exynos5420-tmu",
>> > +               .data = (void *)EXYNOS5420_TMU_DRV_DATA,
>> > +       },
>
> it should come before 5440 entry
Done
>
>> >         {},
>> >  };
>> >  MODULE_DEVICE_TABLE(of, exynos_tmu_match);
>> > @@ -637,7 +646,8 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>> >
>> >         if (pdata->type == SOC_ARCH_EXYNOS ||
>> >                 pdata->type == SOC_ARCH_EXYNOS4210 ||
>> > -                               pdata->type == SOC_ARCH_EXYNOS5440)
>> > +                               pdata->type == SOC_ARCH_EXYNOS5440 ||
>> > +                               pdata->type == SOC_ARCH_EXYNOS5420)
>
> please check for 5420 before 5440
Done
>
>> >                 data->soc = pdata->type;
>> >         else {
>> >                 ret = -EINVAL;
>> > diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
>> > index ebd2ec1..774ab03 100644
>> > --- a/drivers/thermal/samsung/exynos_tmu.h
>> > +++ b/drivers/thermal/samsung/exynos_tmu.h
>> > @@ -43,6 +43,7 @@ enum soc_type {
>> >         SOC_ARCH_EXYNOS4210 = 1,
>> >         SOC_ARCH_EXYNOS,
>> >         SOC_ARCH_EXYNOS5440,
>> > +       SOC_ARCH_EXYNOS5420,
>
> 5420 should come before 5440
Done
>
>> >  };
>> >
>> >  /**
>> > diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
>> > index 58570d0..a6d5cb5 100644
>> > --- a/drivers/thermal/samsung/exynos_tmu_data.c
>> > +++ b/drivers/thermal/samsung/exynos_tmu_data.c
>> > @@ -177,6 +177,136 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
>> >  };
>> >  #endif
>> >
>> > +#if defined(CONFIG_SOC_EXYNOS5420)
>> > +static const struct exynos_tmu_registers exynos5420_tmu_registers = {
>> > +       .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
>> > +       .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
>> > +       .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
>> > +       .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
>> > +       .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
>> > +       .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
>> > +       .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
>> > +       .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
>> > +       .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
>> > +       .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
>> > +       .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
>> > +       .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
>> > +       .tmu_status = EXYNOS_TMU_REG_STATUS,
>> > +       .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
>> > +       .threshold_th0 = EXYNOS_THD_TEMP_RISE,
>> > +       .threshold_th1 = EXYNOS_THD_TEMP_FALL,
>> > +       .tmu_inten = EXYNOS_TMU_REG_INTEN,
>> > +       .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
>> > +       .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
>> > +       .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
>> > +       .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
>> > +       .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
>> > +       .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
>> > +       .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
>> > +       /* INTEN_RISE3 Not availble in exynos5420 */
>> > +       .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
>> > +       .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>> > +       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>> > +       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
>> > +       .intclr_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
>> > +       .emul_con = EXYNOS_EMUL_CON,
>> > +       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>> > +       .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
>> > +       .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
>> > +};
>> > +
>> > +#define EXYNOS5420_TMU_DATA \
>> > +       .threshold_falling = 10, \
>> > +       .trigger_levels[0] = 85, \
>> > +       .trigger_levels[1] = 103, \
>> > +       .trigger_levels[2] = 110, \
>> > +       .trigger_levels[3] = 120, \
>> > +       .trigger_enable[0] = true, \
>> > +       .trigger_enable[1] = true, \
>> > +       .trigger_enable[2] = true, \
>> > +       .trigger_enable[3] = false, \
>> > +       .trigger_type[0] = THROTTLE_ACTIVE, \
>> > +       .trigger_type[1] = THROTTLE_ACTIVE, \
>> > +       .trigger_type[2] = SW_TRIP, \
>> > +       .trigger_type[3] = HW_TRIP, \
>> > +       .max_trigger_level = 4, \
>> > +       .gain = 8, \
>> > +       .reference_voltage = 16, \
>> > +       .noise_cancel_mode = 4, \
>> > +       .cal_type = TYPE_ONE_POINT_TRIMMING, \
>> > +       .efuse_value = 55, \
>> > +       .min_efuse_value = 40, \
>> > +       .max_efuse_value = 100, \
>> > +       .first_point_trim = 25, \
>> > +       .second_point_trim = 85, \
>> > +       .default_temp_offset = 50, \
>> > +       .freq_tab[0] = { \
>> > +               .freq_clip_max = 800 * 1000, \
>> > +               .temp_level = 85, \
>> > +       }, \
>> > +       .freq_tab[1] = { \
>> > +               .freq_clip_max = 200 * 1000, \
>> > +               .temp_level = 103, \
>> > +       }, \
>> > +       .freq_tab_count = 2, \
>> > +       .type = SOC_ARCH_EXYNOS5420, \
>> > +       .registers = &exynos5420_tmu_registers, \
>> > +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
>> > +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
>> > +                       TMU_SUPPORT_EMUL_TIME)
>> > +
>> > +#define EXYNOS5420_TMU_DATA_SHARED \
>> > +       .threshold_falling = 10, \
>> > +       .trigger_levels[0] = 85, \
>> > +       .trigger_levels[1] = 103, \
>> > +       .trigger_levels[2] = 110, \
>> > +       .trigger_levels[3] = 120, \
>> > +       .trigger_enable[0] = true, \
>> > +       .trigger_enable[1] = true, \
>> > +       .trigger_enable[2] = true, \
>> > +       .trigger_enable[3] = false, \
>> > +       .trigger_type[0] = THROTTLE_ACTIVE, \
>> > +       .trigger_type[1] = THROTTLE_ACTIVE, \
>> > +       .trigger_type[2] = SW_TRIP, \
>> > +       .trigger_type[3] = HW_TRIP, \
>> > +       .max_trigger_level = 4, \
>> > +       .gain = 8, \
>> > +       .reference_voltage = 16, \
>> > +       .noise_cancel_mode = 4, \
>> > +       .cal_type = TYPE_ONE_POINT_TRIMMING, \
>> > +       .efuse_value = 55, \
>> > +       .min_efuse_value = 40, \
>> > +       .max_efuse_value = 100, \
>> > +       .first_point_trim = 25, \
>> > +       .second_point_trim = 85, \
>> > +       .default_temp_offset = 50, \
>> > +       .freq_tab[0] = { \
>> > +               .freq_clip_max = 800 * 1000, \
>> > +               .temp_level = 85, \
>> > +       }, \
>> > +       .freq_tab[1] = { \
>> > +               .freq_clip_max = 200 * 1000, \
>> > +               .temp_level = 103, \
>> > +       }, \
>> > +       .freq_tab_count = 2, \
>> > +       .type = SOC_ARCH_EXYNOS5420, \
>> > +       .registers = &exynos5420_tmu_registers, \
>> > +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
>> > +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
>> > +                       TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
>
> EXYNOS5420_TMU_DATA and EXYNOS5420_TMU_DATA_SHARED are identical
> besides .features content so to avoid code duplication please define
> __EXYNOS5420_TMU_DATA with all shared entries and just do:
>
> #define EXYNOS5420_TMU_DATA \
>         __EXYNOS5420_TMU_DATA \
>         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
>                      TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
>                      TMU_SUPPORT_EMUL_TIME)
>
> #define EXYNOS5420_TMU_DATA_SHARED \
>         __EXYNOS5420_TMU_DATA \
>         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
>                      TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
>                      TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
yeah, It saves.
>
>> > +struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
>> > +       .tmu_data = {
>> > +               { EXYNOS5420_TMU_DATA },
>> > +               { EXYNOS5420_TMU_DATA },
>> > +               { EXYNOS5420_TMU_DATA_SHARED },
>> > +               { EXYNOS5420_TMU_DATA_SHARED },
>> > +               { EXYNOS5420_TMU_DATA_SHARED },
>> > +       },
>> > +       .tmu_count = 5,
>> > +};
>> > +#endif
>> > +
>> >  #if defined(CONFIG_SOC_EXYNOS5440)
>> >  static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>> >         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
>> > diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
>> > index 8788a87..3ce94cd 100644
>> > --- a/drivers/thermal/samsung/exynos_tmu_data.h
>> > +++ b/drivers/thermal/samsung/exynos_tmu_data.h
>> > @@ -153,4 +153,11 @@ extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
>> >  #define EXYNOS5440_TMU_DRV_DATA (NULL)
>> >  #endif
>> >
>> > +#if defined(CONFIG_SOC_EXYNOS5420)
>> > +extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
>> > +#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
>> > +#else
>> > +#define EXYNOS5420_TMU_DRV_DATA (NULL)
>> > +#endif
>
> this should come before 5440 entry
Done
>
>> >  #endif /*_EXYNOS_TMU_DATA_H*/
>> > --
>> > 1.7.9.5
>> Hello All,
>>
>> Amit Daniel, has Acked these patches a while ago
>> Any other review comments or updates on this patch ??
>> >
>>
>>
>> Thanks & Regards,
>
> Best regards,
Thanks for review and the suggestions. will post v4 right away.
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
>



-- 
Shine bright,
(: Nav :)

[PATCH 1/3 v4] thermal: samsung: correct the fall interrupt en, status bit fields

[Naveen Krishna Chatradhi]

The FALL interrupt related en, status bits are available at an offset of
16 on INTEN, INTSTAT registers and at an offset of
12 on INTCLEAR register.

This patch corrects the same for exyns5250 and exynos5440

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
Changes since v2:
Changes since v3:
  None

 drivers/thermal/samsung/exynos_tmu.c      |    2 +-
 drivers/thermal/samsung/exynos_tmu.h      |    2 ++
 drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
 drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
 4 files changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index b43afda..af69209 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -265,7 +265,7 @@ skip_calib_data:
 				data->base + reg->threshold_th1);
 
 		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
-			(reg->inten_fall_mask << reg->inten_fall_shift),
+			(reg->inten_fall_mask << reg->intclr_fall_shift),
 				data->base + reg->tmu_intclear);
 
 		/* if last threshold limit is also present */
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index b364c9e..7c6c34a 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -134,6 +134,7 @@ enum soc_type {
  * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
  * @tmu_intstat: Register containing the interrupt status values.
  * @tmu_intclear: Register for clearing the raised interrupt status.
+ * @intclr_fall_shift: shift bits for interrupt clear fall 0
  * @emul_con: TMU emulation controller register.
  * @emul_temp_shift: shift bits of emulation temperature.
  * @emul_time_shift: shift bits of emulation time.
@@ -204,6 +205,7 @@ struct exynos_tmu_registers {
 	u32	tmu_intstat;
 
 	u32	tmu_intclear;
+	u32	intclr_fall_shift;
 
 	u32	emul_con;
 	u32	emul_temp_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 9002499..23fea23 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
 	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 	.emul_con = EXYNOS_EMUL_CON,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index dc7feb5..8788a87 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -69,9 +69,10 @@
 #define EXYNOS_TMU_RISE_INT_MASK	0x111
 #define EXYNOS_TMU_RISE_INT_SHIFT	0
 #define EXYNOS_TMU_FALL_INT_MASK	0x111
-#define EXYNOS_TMU_FALL_INT_SHIFT	12
+#define EXYNOS_TMU_FALL_INT_SHIFT	16
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
+#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
-- 
1.7.10.4

[PATCH 2/3 v4] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Chatradhi]

On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.

To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the "reg" property of the node.

As per Amit's suggestion, this patch changes the base_common
to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
 None
Changes since v2:
 Changed the flag name from SHARED_MEMORY to ADDRESS_MULTIPLE.
 https://lkml.org/lkml/2013/8/1/38
Changes since v3:
 None

 .../devicetree/bindings/thermal/exynos-thermal.txt         |    4 ++--
 drivers/thermal/samsung/exynos_tmu.c                       |   12 ++++++------
 drivers/thermal/samsung/exynos_tmu.h                       |    4 ++--
 drivers/thermal/samsung/exynos_tmu_data.c                  |    2 +-
 4 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 284f530..116cca0 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -11,8 +11,8 @@
 - reg : Address range of the thermal registers. For soc's which has multiple
 	instances of TMU and some registers are shared across all TMU's like
 	interrupt related then 2 set of register has to supplied. First set
-	belongs	to each instance of TMU and second set belongs to common TMU
-	registers.
+	belongs	to each instance of TMU and second set belongs to second set
+	of common TMU registers.
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index af69209..40c4243 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -41,7 +41,7 @@
  * @id: identifier of the one instance of the TMU controller.
  * @pdata: pointer to the tmu platform/configuration data
  * @base: base address of the single instance of the TMU controller.
- * @base_common: base address of the common registers of the TMU controller.
+ * @base_second: base address of the common registers of the TMU controller.
  * @irq: irq number of the TMU controller.
  * @soc: id of the SOC type.
  * @irq_work: pointer to the irq work structure.
@@ -56,7 +56,7 @@ struct exynos_tmu_data {
 	int id;
 	struct exynos_tmu_platform_data *pdata;
 	void __iomem *base;
-	void __iomem *base_common;
+	void __iomem *base_second;
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -297,7 +297,7 @@ skip_calib_data:
 	}
 	/*Clear the PMIN in the common TMU register*/
 	if (reg->tmu_pmin && !data->id)
-		writel(0, data->base_common + reg->tmu_pmin);
+		writel(0, data->base_second + reg->tmu_pmin);
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
@@ -451,7 +451,7 @@ static void exynos_tmu_work(struct work_struct *work)
 
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
-		val_type = readl(data->base_common + reg->tmu_irqstatus);
+		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
@@ -576,7 +576,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 	 * Check if the TMU shares some registers and then try to map the
 	 * memory of common registers.
 	 */
-	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
+	if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
 		return 0;
 
 	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
@@ -584,7 +584,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	data->base_common = devm_ioremap(&pdev->dev, res.start,
+	data->base_second = devm_ioremap(&pdev->dev, res.start,
 					resource_size(&res));
 	if (!data->base_common) {
 		dev_err(&pdev->dev, "Failed to ioremap memory\n");
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 7c6c34a..ebd2ec1 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -59,7 +59,7 @@ enum soc_type {
  *			state(active/idle) can be checked.
  * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
  *			sample time.
- * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
+ * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
  *			sensors shares some common registers.
  * TMU_SUPPORT - macro to compare the above features with the supplied.
  */
@@ -69,7 +69,7 @@ enum soc_type {
 #define TMU_SUPPORT_FALLING_TRIP		BIT(3)
 #define TMU_SUPPORT_READY_STATUS		BIT(4)
 #define TMU_SUPPORT_EMUL_TIME			BIT(5)
-#define TMU_SUPPORT_SHARED_MEMORY		BIT(6)
+#define TMU_SUPPORT_ADDRESS_MULTIPLE		BIT(6)
 
 #define TMU_SUPPORTS(a, b)	(a->features & TMU_SUPPORT_ ## b)
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 23fea23..58570d0 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -239,7 +239,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.type = SOC_ARCH_EXYNOS5440, \
 	.registers = &exynos5440_tmu_registers, \
 	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
-			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
+			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 
 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 	.tmu_data = {
-- 
1.7.10.4

[PATCH 3/3 v4] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Chatradhi]

This patch adds the neccessary register changes and arch information
to support Exynos5420 SoCs
Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU

Also updated the Documentation at
Documentation/devicetree/bindings/thermal/exynos-thermal.txt

Note: The platform data structure will be handled properly once the driver
 moves to complete device driver solution.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
-Changes since v1:
1. modified the platform data structure in order to pass SHARED flag
   for channels that need sharing of address space.
2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
   As the changes are minimum and can be added here.
Changes since v3:
   a. Rearraged the code alphabetically, make exynso5420 come before exynso5440
   b. Reduce code duplication in passing platform data by introducing a common macro
      Bartlomiej Zolnierkiewicz Thanks for review and suggestions
---
 .../devicetree/bindings/thermal/exynos-thermal.txt |   39 ++++++++
 drivers/thermal/samsung/exynos_tmu.c               |   12 ++-
 drivers/thermal/samsung/exynos_tmu.h               |    1 +
 drivers/thermal/samsung/exynos_tmu_data.c          |   99 ++++++++++++++++++++
 drivers/thermal/samsung/exynos_tmu_data.h          |    7 ++
 5 files changed, 157 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 116cca0..c5f9a74 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -6,6 +6,7 @@
 	       "samsung,exynos4412-tmu"
 	       "samsung,exynos4210-tmu"
 	       "samsung,exynos5250-tmu"
+	       "samsung,exynos5420-tmu"
 	       "samsung,exynos5440-tmu"
 - interrupt-parent : The phandle for the interrupt controller
 - reg : Address range of the thermal registers. For soc's which has multiple
@@ -13,6 +14,16 @@
 	interrupt related then 2 set of register has to supplied. First set
 	belongs	to each instance of TMU and second set belongs to second set
 	of common TMU registers.
+  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
+	channels 2, 3 and 4
+
+	TRIMINFO at 0x1006c000 contains data for TMU channel 3
+	TRIMINFO at 0x100a0000 contains data for TMU channel 4
+	TRIMINFO at 0x10068000 contains data for TMU channel 2
+
+	The misplaced register address is passed through devicetree as the
+	second base
+
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
@@ -43,6 +54,34 @@ Example 2):
 		clock-names = "tmu_apbif";
 	};
 
+Example 3): (In case of Exynos5420)
+	/* tmu for CPU2 */
+	tmu@10068000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+		interrupts = <0 184 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+	/* tmu for CPU3 */
+	tmu@1006c000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+		interrupts = <0 185 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+	/* tmu for GPU */
+	tmu@100a0000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
+		interrupts = <0 215 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
 Note: For multi-instance tmu each instance should have an alias correctly
 numbered in "aliases" node.
 
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 40c4243..852034f 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -186,7 +186,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
 		}
 	} else {
-		trim_info = readl(data->base + reg->triminfo_data);
+		/* On exynos5420 the triminfo register is in the shared space */
+		if (data->base_second && (data->soc == SOC_ARCH_EXYNOS5420))
+			trim_info = readl(data->base_second +
+							reg->triminfo_data);
+		else
+			trim_info = readl(data->base + reg->triminfo_data);
 	}
 	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
@@ -495,6 +500,10 @@ static const struct of_device_id exynos_tmu_match[] = {
 		.data = (void *)EXYNOS5250_TMU_DRV_DATA,
 	},
 	{
+		.compatible = "samsung,exynos5420-tmu",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
 		.compatible = "samsung,exynos5440-tmu",
 		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
 	},
@@ -631,6 +640,7 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 
 	if (pdata->type == SOC_ARCH_EXYNOS ||
 		pdata->type == SOC_ARCH_EXYNOS4210 ||
+				pdata->type == SOC_ARCH_EXYNOS5420 ||
 				pdata->type == SOC_ARCH_EXYNOS5440)
 		data->soc = pdata->type;
 	else {
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index ebd2ec1..c2f362f 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -42,6 +42,7 @@ enum calibration_mode {
 enum soc_type {
 	SOC_ARCH_EXYNOS4210 = 1,
 	SOC_ARCH_EXYNOS,
+	SOC_ARCH_EXYNOS5420,
 	SOC_ARCH_EXYNOS5440,
 };
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 58570d0..8610f12 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -177,6 +177,105 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+static const struct exynos_tmu_registers exynos5420_tmu_registers = {
+	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+	.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+	.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+	.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+	.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+	.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+	.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+	.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+	.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+	.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+	.tmu_status = EXYNOS_TMU_REG_STATUS,
+	.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
+	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
+	.tmu_inten = EXYNOS_TMU_REG_INTEN,
+	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
+	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+	/* INTEN_RISE3 Not availble in exynos5420 */
+	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
+	.emul_con = EXYNOS_EMUL_CON,
+	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+	.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define __EXYNOS5420_TMU_DATA	\
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.type = SOC_ARCH_EXYNOS5420, \
+	.registers = &exynos5420_tmu_registers, \
+
+#define EXYNOS5420_TMU_DATA \
+	__EXYNOS5420_TMU_DATA \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME)
+
+#define EXYNOS5420_TMU_DATA_SHARED \
+	__EXYNOS5420_TMU_DATA \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
+
+struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
+	.tmu_data = {
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+	},
+	.tmu_count = 5,
+};
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index 8788a87..59e2f33 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -146,6 +146,13 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
 #define EXYNOS5250_TMU_DRV_DATA (NULL)
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
+#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
+#else
+#define EXYNOS5420_TMU_DRV_DATA (NULL)
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
 #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
-- 
1.7.10.4

Re: [PATCH 1/3 v4] thermal: samsung: correct the fall interrupt en, status bit fields

[Bartlomiej Zolnierkiewicz]

Hi,

All patches (#1-#3) look good to me, FWIW you can add:

	Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>

Please note that (at least) patch #3 conflicts with Lukasz's EXYNOS4412
fixup patchset:

	https://lkml.org/lkml/2013/10/9/35

It is up to Eduardo to resolve this but it probably would be better to
merge EXYNOS4412 fixes first and then add EXYNOS5420 support. This would
require you to port patch #3 over Lukasz's patchset though.

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

On Wednesday, October 09, 2013 05:38:27 PM Naveen Krishna Chatradhi wrote:
> The FALL interrupt related en, status bits are available at an offset of
> 16 on INTEN, INTSTAT registers and at an offset of
> 12 on INTCLEAR register.
> 
> This patch corrects the same for exyns5250 and exynos5440
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> Changes since v1:
> Changes since v2:
> Changes since v3:
>   None
> 
>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
>  drivers/thermal/samsung/exynos_tmu.h      |    2 ++
>  drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
>  drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
>  4 files changed, 7 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index b43afda..af69209 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -265,7 +265,7 @@ skip_calib_data:
>  				data->base + reg->threshold_th1);
>  
>  		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
> -			(reg->inten_fall_mask << reg->inten_fall_shift),
> +			(reg->inten_fall_mask << reg->intclr_fall_shift),
>  				data->base + reg->tmu_intclear);
>  
>  		/* if last threshold limit is also present */
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index b364c9e..7c6c34a 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -134,6 +134,7 @@ enum soc_type {
>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
>   * @tmu_intstat: Register containing the interrupt status values.
>   * @tmu_intclear: Register for clearing the raised interrupt status.
> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
>   * @emul_con: TMU emulation controller register.
>   * @emul_temp_shift: shift bits of emulation temperature.
>   * @emul_time_shift: shift bits of emulation time.
> @@ -204,6 +205,7 @@ struct exynos_tmu_registers {
>  	u32	tmu_intstat;
>  
>  	u32	tmu_intclear;
> +	u32	intclr_fall_shift;
>  
>  	u32	emul_con;
>  	u32	emul_temp_shift;
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 9002499..23fea23 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
>  	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>  	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>  	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>  	.emul_con = EXYNOS_EMUL_CON,
>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>  	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> @@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>  	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
>  	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
>  	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>  	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
>  	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> index dc7feb5..8788a87 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> @@ -69,9 +69,10 @@
>  #define EXYNOS_TMU_RISE_INT_MASK	0x111
>  #define EXYNOS_TMU_RISE_INT_SHIFT	0
>  #define EXYNOS_TMU_FALL_INT_MASK	0x111
> -#define EXYNOS_TMU_FALL_INT_SHIFT	12
> +#define EXYNOS_TMU_FALL_INT_SHIFT	16
>  #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
>  #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
>  #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
>  #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12

Re: [PATCH 1/3 v4] thermal: samsung: correct the fall interrupt en, status bit fields

[Eduardo Valentin]

[-- Attachment #1: Type: text/plain, Size: 5272 bytes --]

Hi Naveen,

On 09-10-2013 10:03, Bartlomiej Zolnierkiewicz wrote:
> 
> Hi,
> 
> All patches (#1-#3) look good to me, FWIW you can add:
> 
> 	Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> 
> Please note that (at least) patch #3 conflicts with Lukasz's EXYNOS4412
> fixup patchset:
> 
> 	https://lkml.org/lkml/2013/10/9/35
> 
> It is up to Eduardo to resolve this but it probably would be better to
> merge EXYNOS4412 fixes first and then add EXYNOS5420 support. This would
> require you to port patch #3 over Lukasz's patchset though.

My question is if this fix applies also to EXYNOS4412, as it  is not
mentioned in the patch description and the change affects all supported
chip version deliberately. Has this change been validated on all
supported chip versions?

Amit, I saw you ack, but still, it is not clear how this change behaves
across supported hardware.

> 
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
> 
> On Wednesday, October 09, 2013 05:38:27 PM Naveen Krishna Chatradhi wrote:
>> The FALL interrupt related en, status bits are available at an offset of
>> 16 on INTEN, INTSTAT registers and at an offset of
>> 12 on INTCLEAR register.
>>
>> This patch corrects the same for exyns5250 and exynos5440
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> ---
>> Changes since v1:
>> Changes since v2:
>> Changes since v3:
>>   None
>>
>>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
>>  drivers/thermal/samsung/exynos_tmu.h      |    2 ++
>>  drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
>>  drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
>>  4 files changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>> index b43afda..af69209 100644
>> --- a/drivers/thermal/samsung/exynos_tmu.c
>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>> @@ -265,7 +265,7 @@ skip_calib_data:
>>  				data->base + reg->threshold_th1);
>>  
>>  		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
>> -			(reg->inten_fall_mask << reg->inten_fall_shift),
>> +			(reg->inten_fall_mask << reg->intclr_fall_shift),
>>  				data->base + reg->tmu_intclear);
>>  
>>  		/* if last threshold limit is also present */
>> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
>> index b364c9e..7c6c34a 100644
>> --- a/drivers/thermal/samsung/exynos_tmu.h
>> +++ b/drivers/thermal/samsung/exynos_tmu.h
>> @@ -134,6 +134,7 @@ enum soc_type {
>>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
>>   * @tmu_intstat: Register containing the interrupt status values.
>>   * @tmu_intclear: Register for clearing the raised interrupt status.
>> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
>>   * @emul_con: TMU emulation controller register.
>>   * @emul_temp_shift: shift bits of emulation temperature.
>>   * @emul_time_shift: shift bits of emulation time.
>> @@ -204,6 +205,7 @@ struct exynos_tmu_registers {
>>  	u32	tmu_intstat;
>>  
>>  	u32	tmu_intclear;
>> +	u32	intclr_fall_shift;
>>  
>>  	u32	emul_con;
>>  	u32	emul_temp_shift;
>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
>> index 9002499..23fea23 100644
>> --- a/drivers/thermal/samsung/exynos_tmu_data.c
>> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
>> @@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
>>  	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>>  	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>>  	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
>> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>>  	.emul_con = EXYNOS_EMUL_CON,
>>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>>  	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
>> @@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>>  	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
>>  	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
>>  	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
>> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>>  	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
>>  	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
>>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
>> index dc7feb5..8788a87 100644
>> --- a/drivers/thermal/samsung/exynos_tmu_data.h
>> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
>> @@ -69,9 +69,10 @@
>>  #define EXYNOS_TMU_RISE_INT_MASK	0x111
>>  #define EXYNOS_TMU_RISE_INT_SHIFT	0
>>  #define EXYNOS_TMU_FALL_INT_MASK	0x111
>> -#define EXYNOS_TMU_FALL_INT_SHIFT	12
>> +#define EXYNOS_TMU_FALL_INT_SHIFT	16
>>  #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
>>  #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
>> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
>>  #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
>>  #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
>>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
> 
> 
> 


-- 
You have got to be excited about what you are doing. (L. Lamport)

Eduardo Valentin


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 295 bytes --]

Re: [PATCH 1/3 v4] thermal: samsung: correct the fall interrupt en, status bit fields

[Bartlomiej Zolnierkiewicz]

Hi,

On Friday, October 11, 2013 11:10:38 AM Eduardo Valentin wrote:
> Hi Naveen,
> 
> On 09-10-2013 10:03, Bartlomiej Zolnierkiewicz wrote:
> > 
> > Hi,
> > 
> > All patches (#1-#3) look good to me, FWIW you can add:
> > 
> > 	Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> > 
> > Please note that (at least) patch #3 conflicts with Lukasz's EXYNOS4412
> > fixup patchset:
> > 
> > 	https://lkml.org/lkml/2013/10/9/35
> > 
> > It is up to Eduardo to resolve this but it probably would be better to
> > merge EXYNOS4412 fixes first and then add EXYNOS5420 support. This would
> > require you to port patch #3 over Lukasz's patchset though.
> 
> My question is if this fix applies also to EXYNOS4412, as it  is not
> mentioned in the patch description and the change affects all supported

This patch doesn't affect EXYNOS4210 as exynos4210_tmu_registers struct
uses the default zero value for inten_fall_mask, inten_fall_shift and
intclr_fall_shift.

> chip version deliberately. Has this change been validated on all
> supported chip versions?
> 
> Amit, I saw you ack, but still, it is not clear how this change behaves
> across supported hardware.

For EXYNOS4412 and EXYNOS5250 this patch doesn't cause any functionality
changes because while the patch changes inten_fall_shift usage to
intclr_fall_shift one in exynos_tmu_initialize() it defines
EXYNOS_TMU_CLEAR_FALL_INT_SHIFT to 12 (old EXYNOS_TMU_FALL_INT_SHIFT
value).

This patch only changes driver behavior for EXYNOS5440 on which the
used shift value changes from 4 to 12.

PS I've only noticed it now but after this patch inten_fall_shift becomes
unused and can be removed.

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

> > 
> > Best regards,
> > --
> > Bartlomiej Zolnierkiewicz
> > Samsung R&D Institute Poland
> > Samsung Electronics
> > 
> > On Wednesday, October 09, 2013 05:38:27 PM Naveen Krishna Chatradhi wrote:
> >> The FALL interrupt related en, status bits are available at an offset of
> >> 16 on INTEN, INTSTAT registers and at an offset of
> >> 12 on INTCLEAR register.
> >>
> >> This patch corrects the same for exyns5250 and exynos5440
> >>
> >> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> >> ---
> >> Changes since v1:
> >> Changes since v2:
> >> Changes since v3:
> >>   None
> >>
> >>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
> >>  drivers/thermal/samsung/exynos_tmu.h      |    2 ++
> >>  drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
> >>  drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
> >>  4 files changed, 7 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> >> index b43afda..af69209 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu.c
> >> +++ b/drivers/thermal/samsung/exynos_tmu.c
> >> @@ -265,7 +265,7 @@ skip_calib_data:
> >>  				data->base + reg->threshold_th1);
> >>  
> >>  		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
> >> -			(reg->inten_fall_mask << reg->inten_fall_shift),
> >> +			(reg->inten_fall_mask << reg->intclr_fall_shift),
> >>  				data->base + reg->tmu_intclear);
> >>  
> >>  		/* if last threshold limit is also present */
> >> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> >> index b364c9e..7c6c34a 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu.h
> >> +++ b/drivers/thermal/samsung/exynos_tmu.h
> >> @@ -134,6 +134,7 @@ enum soc_type {
> >>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
> >>   * @tmu_intstat: Register containing the interrupt status values.
> >>   * @tmu_intclear: Register for clearing the raised interrupt status.
> >> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
> >>   * @emul_con: TMU emulation controller register.
> >>   * @emul_temp_shift: shift bits of emulation temperature.
> >>   * @emul_time_shift: shift bits of emulation time.
> >> @@ -204,6 +205,7 @@ struct exynos_tmu_registers {
> >>  	u32	tmu_intstat;
> >>  
> >>  	u32	tmu_intclear;
> >> +	u32	intclr_fall_shift;
> >>  
> >>  	u32	emul_con;
> >>  	u32	emul_temp_shift;
> >> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> >> index 9002499..23fea23 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> >> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> >> @@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
> >>  	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
> >>  	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
> >>  	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> >> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
> >>  	.emul_con = EXYNOS_EMUL_CON,
> >>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> >>  	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> >> @@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
> >>  	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
> >>  	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
> >>  	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
> >> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
> >>  	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
> >>  	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
> >>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> >> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> >> index dc7feb5..8788a87 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> >> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> >> @@ -69,9 +69,10 @@
> >>  #define EXYNOS_TMU_RISE_INT_MASK	0x111
> >>  #define EXYNOS_TMU_RISE_INT_SHIFT	0
> >>  #define EXYNOS_TMU_FALL_INT_MASK	0x111
> >> -#define EXYNOS_TMU_FALL_INT_SHIFT	12
> >> +#define EXYNOS_TMU_FALL_INT_SHIFT	16
> >>  #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
> >>  #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
> >> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
> >>  #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
> >>  #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
> >>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12

Re: [PATCH 2/3 v4] thermal: samsung: change base_common to more meaningful base_second

[Eduardo Valentin]

[-- Attachment #1: Type: text/plain, Size: 7408 bytes --]

On 09-10-2013 08:08, Naveen Krishna Chatradhi wrote:
> On Exynos5440 and Exynos5420 there are registers common
> across the TMU channels.
> 
> To support that, we introduced a ADDRESS_MULTIPLE flag in the
> driver and the 2nd set of register base and size are provided
> in the "reg" property of the node.
> 
> As per Amit's suggestion, this patch changes the base_common
> to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> Changes since v1:
>  None
> Changes since v2:
>  Changed the flag name from SHARED_MEMORY to ADDRESS_MULTIPLE.
>  https://lkml.org/lkml/2013/8/1/38
> Changes since v3:
>  None

 This patch generates build error:
 CC [M]  drivers/thermal/samsung/exynos_tmu.o
 drivers/thermal/samsung/exynos_tmu.c: In function 'exynos_map_dt_data':
 drivers/thermal/samsung/exynos_tmu.c:592:11: error: 'struct
exynos_tmu_data' has no member named 'base_common'
 make[3]: *** [drivers/thermal/samsung/exynos_tmu.o] Error 1
 make[2]: *** [drivers/thermal/samsung] Error 2
 make[1]: *** [drivers/thermal] Error 2
 make[1]: *** Waiting for unfinished jobs....


You've missed one occurrence while renaming the symbol:
diff --git a/drivers/thermal/samsung/exynos_tmu.c
b/drivers/thermal/samsung/exynos_tmu.c
index cd8dc12..ae80a87 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -589,7 +589,7 @@ static int exynos_map_dt_data(struct platform_device
*pdev)

        data->base_second = devm_ioremap(&pdev->dev, res.start,
                                        resource_size(&res));
-       if (!data->base_common) {
+       if (!data->base_second) {
                dev_err(&pdev->dev, "Failed to ioremap memory\n");
                return -ENOMEM;
        }

Please compile test your patch before submitting!

> 
>  .../devicetree/bindings/thermal/exynos-thermal.txt         |    4 ++--
>  drivers/thermal/samsung/exynos_tmu.c                       |   12 ++++++------
>  drivers/thermal/samsung/exynos_tmu.h                       |    4 ++--
>  drivers/thermal/samsung/exynos_tmu_data.c                  |    2 +-
>  4 files changed, 11 insertions(+), 11 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 284f530..116cca0 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -11,8 +11,8 @@
>  - reg : Address range of the thermal registers. For soc's which has multiple
>  	instances of TMU and some registers are shared across all TMU's like
>  	interrupt related then 2 set of register has to supplied. First set
> -	belongs	to each instance of TMU and second set belongs to common TMU
> -	registers.
> +	belongs	to each instance of TMU and second set belongs to second set
> +	of common TMU registers.
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index af69209..40c4243 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -41,7 +41,7 @@
>   * @id: identifier of the one instance of the TMU controller.
>   * @pdata: pointer to the tmu platform/configuration data
>   * @base: base address of the single instance of the TMU controller.
> - * @base_common: base address of the common registers of the TMU controller.
> + * @base_second: base address of the common registers of the TMU controller.
>   * @irq: irq number of the TMU controller.
>   * @soc: id of the SOC type.
>   * @irq_work: pointer to the irq work structure.
> @@ -56,7 +56,7 @@ struct exynos_tmu_data {
>  	int id;
>  	struct exynos_tmu_platform_data *pdata;
>  	void __iomem *base;
> -	void __iomem *base_common;
> +	void __iomem *base_second;
>  	int irq;
>  	enum soc_type soc;
>  	struct work_struct irq_work;
> @@ -297,7 +297,7 @@ skip_calib_data:
>  	}
>  	/*Clear the PMIN in the common TMU register*/
>  	if (reg->tmu_pmin && !data->id)
> -		writel(0, data->base_common + reg->tmu_pmin);
> +		writel(0, data->base_second + reg->tmu_pmin);
>  out:
>  	clk_disable(data->clk);
>  	mutex_unlock(&data->lock);
> @@ -451,7 +451,7 @@ static void exynos_tmu_work(struct work_struct *work)
>  
>  	/* Find which sensor generated this interrupt */
>  	if (reg->tmu_irqstatus) {
> -		val_type = readl(data->base_common + reg->tmu_irqstatus);
> +		val_type = readl(data->base_second + reg->tmu_irqstatus);
>  		if (!((val_type >> data->id) & 0x1))
>  			goto out;
>  	}
> @@ -576,7 +576,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>  	 * Check if the TMU shares some registers and then try to map the
>  	 * memory of common registers.
>  	 */
> -	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
> +	if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
>  		return 0;
>  
>  	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
> @@ -584,7 +584,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>  		return -ENODEV;
>  	}
>  
> -	data->base_common = devm_ioremap(&pdev->dev, res.start,
> +	data->base_second = devm_ioremap(&pdev->dev, res.start,
>  					resource_size(&res));
>  	if (!data->base_common) {
>  		dev_err(&pdev->dev, "Failed to ioremap memory\n");
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 7c6c34a..ebd2ec1 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -59,7 +59,7 @@ enum soc_type {
>   *			state(active/idle) can be checked.
>   * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
>   *			sample time.
> - * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
> + * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
>   *			sensors shares some common registers.
>   * TMU_SUPPORT - macro to compare the above features with the supplied.
>   */
> @@ -69,7 +69,7 @@ enum soc_type {
>  #define TMU_SUPPORT_FALLING_TRIP		BIT(3)
>  #define TMU_SUPPORT_READY_STATUS		BIT(4)
>  #define TMU_SUPPORT_EMUL_TIME			BIT(5)
> -#define TMU_SUPPORT_SHARED_MEMORY		BIT(6)
> +#define TMU_SUPPORT_ADDRESS_MULTIPLE		BIT(6)
>  
>  #define TMU_SUPPORTS(a, b)	(a->features & TMU_SUPPORT_ ## b)
>  
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 23fea23..58570d0 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -239,7 +239,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>  	.type = SOC_ARCH_EXYNOS5440, \
>  	.registers = &exynos5440_tmu_registers, \
>  	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
> -			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
> +			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
>  
>  struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
>  	.tmu_data = {
> 


-- 
You have got to be excited about what you are doing. (L. Lamport)

Eduardo Valentin


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 295 bytes --]

Re: [PATCH 1/3 v4] thermal: samsung: correct the fall interrupt en, status bit fields

[Eduardo Valentin]

[-- Attachment #1: Type: text/plain, Size: 5105 bytes --]


Naveen,

On 09-10-2013 10:03, Bartlomiej Zolnierkiewicz wrote:
> 
> Hi,
> 
> All patches (#1-#3) look good to me, FWIW you can add:
> 
> 	Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> 
> Please note that (at least) patch #3 conflicts with Lukasz's EXYNOS4412
> fixup patchset:
> 
> 	https://lkml.org/lkml/2013/10/9/35
> 
> It is up to Eduardo to resolve this but it probably would be better to
> merge EXYNOS4412 fixes first and then add EXYNOS5420 support. This would
> require you to port patch #3 over Lukasz's patchset though.
> 

Please rebase your patch set on top of Lukasz'. There are conflicts
while applying patch 3. Please also compile test it before posting,
check comment I made on patch 2.

> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
> 
> On Wednesday, October 09, 2013 05:38:27 PM Naveen Krishna Chatradhi wrote:
>> The FALL interrupt related en, status bits are available at an offset of
>> 16 on INTEN, INTSTAT registers and at an offset of
>> 12 on INTCLEAR register.
>>
>> This patch corrects the same for exyns5250 and exynos5440
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> ---
>> Changes since v1:
>> Changes since v2:
>> Changes since v3:
>>   None
>>
>>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
>>  drivers/thermal/samsung/exynos_tmu.h      |    2 ++
>>  drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
>>  drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
>>  4 files changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>> index b43afda..af69209 100644
>> --- a/drivers/thermal/samsung/exynos_tmu.c
>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>> @@ -265,7 +265,7 @@ skip_calib_data:
>>  				data->base + reg->threshold_th1);
>>  
>>  		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
>> -			(reg->inten_fall_mask << reg->inten_fall_shift),
>> +			(reg->inten_fall_mask << reg->intclr_fall_shift),
>>  				data->base + reg->tmu_intclear);
>>  
>>  		/* if last threshold limit is also present */
>> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
>> index b364c9e..7c6c34a 100644
>> --- a/drivers/thermal/samsung/exynos_tmu.h
>> +++ b/drivers/thermal/samsung/exynos_tmu.h
>> @@ -134,6 +134,7 @@ enum soc_type {
>>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
>>   * @tmu_intstat: Register containing the interrupt status values.
>>   * @tmu_intclear: Register for clearing the raised interrupt status.
>> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
>>   * @emul_con: TMU emulation controller register.
>>   * @emul_temp_shift: shift bits of emulation temperature.
>>   * @emul_time_shift: shift bits of emulation time.
>> @@ -204,6 +205,7 @@ struct exynos_tmu_registers {
>>  	u32	tmu_intstat;
>>  
>>  	u32	tmu_intclear;
>> +	u32	intclr_fall_shift;
>>  
>>  	u32	emul_con;
>>  	u32	emul_temp_shift;
>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
>> index 9002499..23fea23 100644
>> --- a/drivers/thermal/samsung/exynos_tmu_data.c
>> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
>> @@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
>>  	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>>  	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>>  	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
>> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>>  	.emul_con = EXYNOS_EMUL_CON,
>>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>>  	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
>> @@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>>  	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
>>  	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
>>  	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
>> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>>  	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
>>  	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
>>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
>> index dc7feb5..8788a87 100644
>> --- a/drivers/thermal/samsung/exynos_tmu_data.h
>> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
>> @@ -69,9 +69,10 @@
>>  #define EXYNOS_TMU_RISE_INT_MASK	0x111
>>  #define EXYNOS_TMU_RISE_INT_SHIFT	0
>>  #define EXYNOS_TMU_FALL_INT_MASK	0x111
>> -#define EXYNOS_TMU_FALL_INT_SHIFT	12
>> +#define EXYNOS_TMU_FALL_INT_SHIFT	16
>>  #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
>>  #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
>> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
>>  #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
>>  #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
>>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
> 
> 
> 


-- 
You have got to be excited about what you are doing. (L. Lamport)

Eduardo Valentin


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 295 bytes --]

Re: [PATCH 1/3 v4] thermal: samsung: correct the fall interrupt en, status bit fields

[Eduardo Valentin]

[-- Attachment #1: Type: text/plain, Size: 6645 bytes --]

On 11-10-2013 11:57, Bartlomiej Zolnierkiewicz wrote:
> 
> Hi,
> 
> On Friday, October 11, 2013 11:10:38 AM Eduardo Valentin wrote:
>> Hi Naveen,
>>
>> On 09-10-2013 10:03, Bartlomiej Zolnierkiewicz wrote:
>>>
>>> Hi,
>>>
>>> All patches (#1-#3) look good to me, FWIW you can add:
>>>
>>> 	Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>>>
>>> Please note that (at least) patch #3 conflicts with Lukasz's EXYNOS4412
>>> fixup patchset:
>>>
>>> 	https://lkml.org/lkml/2013/10/9/35
>>>
>>> It is up to Eduardo to resolve this but it probably would be better to
>>> merge EXYNOS4412 fixes first and then add EXYNOS5420 support. This would
>>> require you to port patch #3 over Lukasz's patchset though.
>>
>> My question is if this fix applies also to EXYNOS4412, as it  is not
>> mentioned in the patch description and the change affects all supported
> 
> This patch doesn't affect EXYNOS4210 as exynos4210_tmu_registers struct

I was, at least for now, worried about 4412, as I mentioned above.

> uses the default zero value for inten_fall_mask, inten_fall_shift and
> intclr_fall_shift.
> 
>> chip version deliberately. Has this change been validated on all
>> supported chip versions?
>>
>> Amit, I saw you ack, but still, it is not clear how this change behaves
>> across supported hardware.
> 
> For EXYNOS4412 and EXYNOS5250 this patch doesn't cause any functionality
> changes because while the patch changes inten_fall_shift usage to
> intclr_fall_shift one in exynos_tmu_initialize() it defines
> EXYNOS_TMU_CLEAR_FALL_INT_SHIFT to 12 (old EXYNOS_TMU_FALL_INT_SHIFT
> value).
> 

OK. Then the patch is about a symbol rename, right?

> This patch only changes driver behavior for EXYNOS5440 on which the
> used shift value changes from 4 to 12.

I see.

> 
> PS I've only noticed it now but after this patch inten_fall_shift becomes
> unused and can be removed.
> 


Then we should remove it.



> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
> 
>>>
>>> Best regards,
>>> --
>>> Bartlomiej Zolnierkiewicz
>>> Samsung R&D Institute Poland
>>> Samsung Electronics
>>>
>>> On Wednesday, October 09, 2013 05:38:27 PM Naveen Krishna Chatradhi wrote:
>>>> The FALL interrupt related en, status bits are available at an offset of
>>>> 16 on INTEN, INTSTAT registers and at an offset of
>>>> 12 on INTCLEAR register.
>>>>
>>>> This patch corrects the same for exyns5250 and exynos5440
>>>>
>>>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>>>> ---
>>>> Changes since v1:
>>>> Changes since v2:
>>>> Changes since v3:
>>>>   None
>>>>
>>>>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
>>>>  drivers/thermal/samsung/exynos_tmu.h      |    2 ++
>>>>  drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
>>>>  drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
>>>>  4 files changed, 7 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>>>> index b43afda..af69209 100644
>>>> --- a/drivers/thermal/samsung/exynos_tmu.c
>>>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>>>> @@ -265,7 +265,7 @@ skip_calib_data:
>>>>  				data->base + reg->threshold_th1);
>>>>  
>>>>  		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
>>>> -			(reg->inten_fall_mask << reg->inten_fall_shift),
>>>> +			(reg->inten_fall_mask << reg->intclr_fall_shift),
>>>>  				data->base + reg->tmu_intclear);
>>>>  
>>>>  		/* if last threshold limit is also present */
>>>> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
>>>> index b364c9e..7c6c34a 100644
>>>> --- a/drivers/thermal/samsung/exynos_tmu.h
>>>> +++ b/drivers/thermal/samsung/exynos_tmu.h
>>>> @@ -134,6 +134,7 @@ enum soc_type {
>>>>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
>>>>   * @tmu_intstat: Register containing the interrupt status values.
>>>>   * @tmu_intclear: Register for clearing the raised interrupt status.
>>>> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
>>>>   * @emul_con: TMU emulation controller register.
>>>>   * @emul_temp_shift: shift bits of emulation temperature.
>>>>   * @emul_time_shift: shift bits of emulation time.
>>>> @@ -204,6 +205,7 @@ struct exynos_tmu_registers {
>>>>  	u32	tmu_intstat;
>>>>  
>>>>  	u32	tmu_intclear;
>>>> +	u32	intclr_fall_shift;
>>>>  
>>>>  	u32	emul_con;
>>>>  	u32	emul_temp_shift;
>>>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
>>>> index 9002499..23fea23 100644
>>>> --- a/drivers/thermal/samsung/exynos_tmu_data.c
>>>> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
>>>> @@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
>>>>  	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>>>>  	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>>>>  	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
>>>> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>>>>  	.emul_con = EXYNOS_EMUL_CON,
>>>>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>>>>  	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
>>>> @@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>>>>  	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
>>>>  	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
>>>>  	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
>>>> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>>>>  	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
>>>>  	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
>>>>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>>>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
>>>> index dc7feb5..8788a87 100644
>>>> --- a/drivers/thermal/samsung/exynos_tmu_data.h
>>>> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
>>>> @@ -69,9 +69,10 @@
>>>>  #define EXYNOS_TMU_RISE_INT_MASK	0x111
>>>>  #define EXYNOS_TMU_RISE_INT_SHIFT	0
>>>>  #define EXYNOS_TMU_FALL_INT_MASK	0x111
>>>> -#define EXYNOS_TMU_FALL_INT_SHIFT	12
>>>> +#define EXYNOS_TMU_FALL_INT_SHIFT	16
>>>>  #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
>>>>  #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
>>>> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
>>>>  #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
>>>>  #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
>>>>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
> 
> 
> 


-- 
You have got to be excited about what you are doing. (L. Lamport)

Eduardo Valentin


[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 295 bytes --]

Re: [PATCH 1/3 v4] thermal: samsung: correct the fall interrupt en, status bit fields

[Bartlomiej Zolnierkiewicz]

On Monday, October 14, 2013 10:18:03 AM Eduardo Valentin wrote:
> On 11-10-2013 11:57, Bartlomiej Zolnierkiewicz wrote:
> > 
> > Hi,
> > 
> > On Friday, October 11, 2013 11:10:38 AM Eduardo Valentin wrote:
> >> Hi Naveen,
> >>
> >> On 09-10-2013 10:03, Bartlomiej Zolnierkiewicz wrote:
> >>>
> >>> Hi,
> >>>
> >>> All patches (#1-#3) look good to me, FWIW you can add:
> >>>
> >>> 	Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> >>>
> >>> Please note that (at least) patch #3 conflicts with Lukasz's EXYNOS4412
> >>> fixup patchset:
> >>>
> >>> 	https://lkml.org/lkml/2013/10/9/35
> >>>
> >>> It is up to Eduardo to resolve this but it probably would be better to
> >>> merge EXYNOS4412 fixes first and then add EXYNOS5420 support. This would
> >>> require you to port patch #3 over Lukasz's patchset though.
> >>
> >> My question is if this fix applies also to EXYNOS4412, as it  is not
> >> mentioned in the patch description and the change affects all supported
> > 
> > This patch doesn't affect EXYNOS4210 as exynos4210_tmu_registers struct
> 
> I was, at least for now, worried about 4412, as I mentioned above.
> 
> > uses the default zero value for inten_fall_mask, inten_fall_shift and
> > intclr_fall_shift.
> > 
> >> chip version deliberately. Has this change been validated on all
> >> supported chip versions?
> >>
> >> Amit, I saw you ack, but still, it is not clear how this change behaves
> >> across supported hardware.
> > 
> > For EXYNOS4412 and EXYNOS5250 this patch doesn't cause any functionality
> > changes because while the patch changes inten_fall_shift usage to
> > intclr_fall_shift one in exynos_tmu_initialize() it defines
> > EXYNOS_TMU_CLEAR_FALL_INT_SHIFT to 12 (old EXYNOS_TMU_FALL_INT_SHIFT
> > value).
> > 
> 
> OK. Then the patch is about a symbol rename, right?

Yes and while doing so it also changes the define and the value used on
EXYNOS5440. I checked this change against the documentation today (please
see below).

> > This patch only changes driver behavior for EXYNOS5440 on which the
> > used shift value changes from 4 to 12.
> 
> I see.

tmu_intstat and tmu_intclear refer to the same register on EXYNOS5440
(EXYNOS5440_TMU_S0_7_IRQ defined to 0x230) and the documentation that
I have says that the value 4 (which matches EXYNOS5440_TMU_FALL_INT_SHIFT
before the patch) should be used for the shift value. However the patch
doesn't define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT and instead makes
the code use generic EXYNOS_TMU_CLEAR_FALL_INT_SHIFT (defined to value
12) also on EXYNOS5440. This doesn't seem correct.

Naveen, this issue needs to be either fixed or explained properly (if
the documentation is wrong) in the patch description. Please also put some
information about hardware that you've tested your patch on in the patch
description.

> > 
> > PS I've only noticed it now but after this patch inten_fall_shift becomes
> > unused and can be removed.
> > 
> 
> 
> Then we should remove it.

I completely agree.

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

> > Best regards,
> > --
> > Bartlomiej Zolnierkiewicz
> > Samsung R&D Institute Poland
> > Samsung Electronics
> > 
> >>>
> >>> Best regards,
> >>> --
> >>> Bartlomiej Zolnierkiewicz
> >>> Samsung R&D Institute Poland
> >>> Samsung Electronics
> >>>
> >>> On Wednesday, October 09, 2013 05:38:27 PM Naveen Krishna Chatradhi wrote:
> >>>> The FALL interrupt related en, status bits are available at an offset of
> >>>> 16 on INTEN, INTSTAT registers and at an offset of
> >>>> 12 on INTCLEAR register.
> >>>>
> >>>> This patch corrects the same for exyns5250 and exynos5440
> >>>>
> >>>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> >>>> ---
> >>>> Changes since v1:
> >>>> Changes since v2:
> >>>> Changes since v3:
> >>>>   None
> >>>>
> >>>>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
> >>>>  drivers/thermal/samsung/exynos_tmu.h      |    2 ++
> >>>>  drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
> >>>>  drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
> >>>>  4 files changed, 7 insertions(+), 2 deletions(-)
> >>>>
> >>>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> >>>> index b43afda..af69209 100644
> >>>> --- a/drivers/thermal/samsung/exynos_tmu.c
> >>>> +++ b/drivers/thermal/samsung/exynos_tmu.c
> >>>> @@ -265,7 +265,7 @@ skip_calib_data:
> >>>>  				data->base + reg->threshold_th1);
> >>>>  
> >>>>  		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
> >>>> -			(reg->inten_fall_mask << reg->inten_fall_shift),
> >>>> +			(reg->inten_fall_mask << reg->intclr_fall_shift),
> >>>>  				data->base + reg->tmu_intclear);
> >>>>  
> >>>>  		/* if last threshold limit is also present */
> >>>> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> >>>> index b364c9e..7c6c34a 100644
> >>>> --- a/drivers/thermal/samsung/exynos_tmu.h
> >>>> +++ b/drivers/thermal/samsung/exynos_tmu.h
> >>>> @@ -134,6 +134,7 @@ enum soc_type {
> >>>>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
> >>>>   * @tmu_intstat: Register containing the interrupt status values.
> >>>>   * @tmu_intclear: Register for clearing the raised interrupt status.
> >>>> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
> >>>>   * @emul_con: TMU emulation controller register.
> >>>>   * @emul_temp_shift: shift bits of emulation temperature.
> >>>>   * @emul_time_shift: shift bits of emulation time.
> >>>> @@ -204,6 +205,7 @@ struct exynos_tmu_registers {
> >>>>  	u32	tmu_intstat;
> >>>>  
> >>>>  	u32	tmu_intclear;
> >>>> +	u32	intclr_fall_shift;
> >>>>  
> >>>>  	u32	emul_con;
> >>>>  	u32	emul_temp_shift;
> >>>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> >>>> index 9002499..23fea23 100644
> >>>> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> >>>> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> >>>> @@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
> >>>>  	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
> >>>>  	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
> >>>>  	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> >>>> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
> >>>>  	.emul_con = EXYNOS_EMUL_CON,
> >>>>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> >>>>  	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> >>>> @@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
> >>>>  	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
> >>>>  	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
> >>>>  	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
> >>>> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
> >>>>  	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
> >>>>  	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
> >>>>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> >>>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> >>>> index dc7feb5..8788a87 100644
> >>>> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> >>>> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> >>>> @@ -69,9 +69,10 @@
> >>>>  #define EXYNOS_TMU_RISE_INT_MASK	0x111
> >>>>  #define EXYNOS_TMU_RISE_INT_SHIFT	0
> >>>>  #define EXYNOS_TMU_FALL_INT_MASK	0x111
> >>>> -#define EXYNOS_TMU_FALL_INT_SHIFT	12
> >>>> +#define EXYNOS_TMU_FALL_INT_SHIFT	16
> >>>>  #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
> >>>>  #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
> >>>> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
> >>>>  #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
> >>>>  #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
> >>>>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12

Re: [PATCH 1/3 v4] thermal: samsung: correct the fall interrupt en, status bit fields

[Naveen Krishna Ch]

On 14 October 2013 21:31, Bartlomiej Zolnierkiewicz
<b.zolnierkie@samsung.com> wrote:
> On Monday, October 14, 2013 10:18:03 AM Eduardo Valentin wrote:
>> On 11-10-2013 11:57, Bartlomiej Zolnierkiewicz wrote:
>> >
>> > Hi,
>> >
>> > On Friday, October 11, 2013 11:10:38 AM Eduardo Valentin wrote:
>> >> Hi Naveen,
>> >>
>> >> On 09-10-2013 10:03, Bartlomiej Zolnierkiewicz wrote:
>> >>>
>> >>> Hi,
>> >>>
>> >>> All patches (#1-#3) look good to me, FWIW you can add:
>> >>>
>> >>>   Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>> >>>
>> >>> Please note that (at least) patch #3 conflicts with Lukasz's EXYNOS4412
>> >>> fixup patchset:
>> >>>
>> >>>   https://lkml.org/lkml/2013/10/9/35
>> >>>
>> >>> It is up to Eduardo to resolve this but it probably would be better to
>> >>> merge EXYNOS4412 fixes first and then add EXYNOS5420 support. This would
>> >>> require you to port patch #3 over Lukasz's patchset though.
>> >>
>> >> My question is if this fix applies also to EXYNOS4412, as it  is not
>> >> mentioned in the patch description and the change affects all supported
>> >
>> > This patch doesn't affect EXYNOS4210 as exynos4210_tmu_registers struct
>>
>> I was, at least for now, worried about 4412, as I mentioned above.
>>
>> > uses the default zero value for inten_fall_mask, inten_fall_shift and
>> > intclr_fall_shift.
>> >
>> >> chip version deliberately. Has this change been validated on all
>> >> supported chip versions?
>> >>
>> >> Amit, I saw you ack, but still, it is not clear how this change behaves
>> >> across supported hardware.
>> >
>> > For EXYNOS4412 and EXYNOS5250 this patch doesn't cause any functionality
>> > changes because while the patch changes inten_fall_shift usage to
>> > intclr_fall_shift one in exynos_tmu_initialize() it defines
>> > EXYNOS_TMU_CLEAR_FALL_INT_SHIFT to 12 (old EXYNOS_TMU_FALL_INT_SHIFT
>> > value).
>> >
>>
>> OK. Then the patch is about a symbol rename, right?
>
> Yes and while doing so it also changes the define and the value used on
> EXYNOS5440. I checked this change against the documentation today (please
> see below).
>
>> > This patch only changes driver behavior for EXYNOS5440 on which the
>> > used shift value changes from 4 to 12.
>>
>> I see.
>
> tmu_intstat and tmu_intclear refer to the same register on EXYNOS5440
> (EXYNOS5440_TMU_S0_7_IRQ defined to 0x230) and the documentation that
> I have says that the value 4 (which matches EXYNOS5440_TMU_FALL_INT_SHIFT
> before the patch) should be used for the shift value. However the patch
> doesn't define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT and instead makes
> the code use generic EXYNOS_TMU_CLEAR_FALL_INT_SHIFT (defined to value
> 12) also on EXYNOS5440. This doesn't seem correct.

Right EXYNOS5440  User manual says TMU_S0-7_IRQEN register fields
RISE_IRQEN 3:0
FALL_IRQEN 7:4
Will make changes accordingly.

I've only tested on Exynos5250 and Exynos5420.
Depending on Amit for Exynos5440 as i don't hardware available.
>
> Naveen, this issue needs to be either fixed or explained properly (if
> the documentation is wrong) in the patch description. Please also put some
> information about hardware that you've tested your patch on in the patch
> description.
I've seen that the patches won't apply straight.
and there is a compilation warning introduced. Will fix both of them.
>
>> >
>> > PS I've only noticed it now but after this patch inten_fall_shift becomes
>> > unused and can be removed.
>> >
>>
>>
>> Then we should remove it.
>
> I completely agree.
>
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
>
>> > Best regards,
>> > --
>> > Bartlomiej Zolnierkiewicz
>> > Samsung R&D Institute Poland
>> > Samsung Electronics
>> >
>> >>>
>> >>> Best regards,
>> >>> --
>> >>> Bartlomiej Zolnierkiewicz
>> >>> Samsung R&D Institute Poland
>> >>> Samsung Electronics
>> >>>
>> >>> On Wednesday, October 09, 2013 05:38:27 PM Naveen Krishna Chatradhi wrote:
>> >>>> The FALL interrupt related en, status bits are available at an offset of
>> >>>> 16 on INTEN, INTSTAT registers and at an offset of
>> >>>> 12 on INTCLEAR register.
>> >>>>
>> >>>> This patch corrects the same for exyns5250 and exynos5440
>> >>>>
>> >>>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> >>>> ---
>> >>>> Changes since v1:
>> >>>> Changes since v2:
>> >>>> Changes since v3:
>> >>>>   None
>> >>>>
>> >>>>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
>> >>>>  drivers/thermal/samsung/exynos_tmu.h      |    2 ++
>> >>>>  drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
>> >>>>  drivers/thermal/samsung/exynos_tmu_data.h |    3 ++-
>> >>>>  4 files changed, 7 insertions(+), 2 deletions(-)
>> >>>>
>> >>>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>> >>>> index b43afda..af69209 100644
>> >>>> --- a/drivers/thermal/samsung/exynos_tmu.c
>> >>>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>> >>>> @@ -265,7 +265,7 @@ skip_calib_data:
>> >>>>                                  data->base + reg->threshold_th1);
>> >>>>
>> >>>>                  writel((reg->inten_rise_mask << reg->inten_rise_shift) |
>> >>>> -                        (reg->inten_fall_mask << reg->inten_fall_shift),
>> >>>> +                        (reg->inten_fall_mask << reg->intclr_fall_shift),
>> >>>>                                  data->base + reg->tmu_intclear);
>> >>>>
>> >>>>                  /* if last threshold limit is also present */
>> >>>> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
>> >>>> index b364c9e..7c6c34a 100644
>> >>>> --- a/drivers/thermal/samsung/exynos_tmu.h
>> >>>> +++ b/drivers/thermal/samsung/exynos_tmu.h
>> >>>> @@ -134,6 +134,7 @@ enum soc_type {
>> >>>>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
>> >>>>   * @tmu_intstat: Register containing the interrupt status values.
>> >>>>   * @tmu_intclear: Register for clearing the raised interrupt status.
>> >>>> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
>> >>>>   * @emul_con: TMU emulation controller register.
>> >>>>   * @emul_temp_shift: shift bits of emulation temperature.
>> >>>>   * @emul_time_shift: shift bits of emulation time.
>> >>>> @@ -204,6 +205,7 @@ struct exynos_tmu_registers {
>> >>>>          u32     tmu_intstat;
>> >>>>
>> >>>>          u32     tmu_intclear;
>> >>>> +        u32     intclr_fall_shift;
>> >>>>
>> >>>>          u32     emul_con;
>> >>>>          u32     emul_temp_shift;
>> >>>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
>> >>>> index 9002499..23fea23 100644
>> >>>> --- a/drivers/thermal/samsung/exynos_tmu_data.c
>> >>>> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
>> >>>> @@ -122,6 +122,7 @@ static const struct exynos_tmu_registers exynos5250_tmu_registers = {
>> >>>>          .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>> >>>>          .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>> >>>>          .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
>> >>>> +        .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>> >>>>          .emul_con = EXYNOS_EMUL_CON,
>> >>>>          .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>> >>>>          .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
>> >>>> @@ -210,6 +211,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>> >>>>          .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
>> >>>>          .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
>> >>>>          .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
>> >>>> +        .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>> >>>>          .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
>> >>>>          .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
>> >>>>          .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>> >>>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
>> >>>> index dc7feb5..8788a87 100644
>> >>>> --- a/drivers/thermal/samsung/exynos_tmu_data.h
>> >>>> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
>> >>>> @@ -69,9 +69,10 @@
>> >>>>  #define EXYNOS_TMU_RISE_INT_MASK        0x111
>> >>>>  #define EXYNOS_TMU_RISE_INT_SHIFT       0
>> >>>>  #define EXYNOS_TMU_FALL_INT_MASK        0x111
>> >>>> -#define EXYNOS_TMU_FALL_INT_SHIFT       12
>> >>>> +#define EXYNOS_TMU_FALL_INT_SHIFT       16
>> >>>>  #define EXYNOS_TMU_CLEAR_RISE_INT       0x111
>> >>>>  #define EXYNOS_TMU_CLEAR_FALL_INT       (0x111 << 12)
>> >>>> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT 12
>> >>>>  #define EXYNOS_TMU_TRIP_MODE_SHIFT      13
>> >>>>  #define EXYNOS_TMU_TRIP_MODE_MASK       0x7
>> >>>>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT  12
>



-- 
Shine bright,
(: Nav :)

[PATCH 1/3 v6] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register

[Naveen Krishna Chatradhi]

On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT registers and at an offset of
12 in INTCLEAR register.

On Exynos5420, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT and INTCLEAR registers.

On Exynos5440,
the FALL_IRQEN bits are at an offset of 4
and the RISE_IRQEN bits are at an offset of 0

This patch introduces a new bit field intclr_fall_shift to handle the
offset for exyns5250 and exynos5440

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
Changes since v2:
Changes since v3:
  None
Changes since v4:
 Correct the CLEAR_FALL_INT_SHIFT for Exynos5250/Exynos5440
Changes since v5:
 Modify the commit message

 drivers/thermal/samsung/exynos_tmu.c      |    2 +-
 drivers/thermal/samsung/exynos_tmu.h      |    2 ++
 drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
 drivers/thermal/samsung/exynos_tmu_data.h |    4 +++-
 4 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 32f38b9..b2202fa 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -265,7 +265,7 @@ skip_calib_data:
 				data->base + reg->threshold_th1);
 
 		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
-			(reg->inten_fall_mask << reg->inten_fall_shift),
+			(reg->inten_fall_mask << reg->intclr_fall_shift),
 				data->base + reg->tmu_intclear);
 
 		/* if last threshold limit is also present */
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 3fb6554..5f4fe6c 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -136,6 +136,7 @@ enum soc_type {
  * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
  * @tmu_intstat: Register containing the interrupt status values.
  * @tmu_intclear: Register for clearing the raised interrupt status.
+ * @intclr_fall_shift: shift bits for interrupt clear fall 0
  * @emul_con: TMU emulation controller register.
  * @emul_temp_shift: shift bits of emulation temperature.
  * @emul_time_shift: shift bits of emulation time.
@@ -207,6 +208,7 @@ struct exynos_tmu_registers {
 	u32	tmu_intstat;
 
 	u32	tmu_intclear;
+	u32	intclr_fall_shift;
 
 	u32	emul_con;
 	u32	emul_temp_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 073c292..09a8a27 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -123,6 +123,7 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS5250_TMU_CLEAR_FALL_INT_SHIFT,
 	.emul_con = EXYNOS_EMUL_CON,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -228,6 +229,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
+	.intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
 	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index a1ea19d..9c1e2c8 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -69,9 +69,11 @@
 #define EXYNOS_TMU_RISE_INT_MASK	0x111
 #define EXYNOS_TMU_RISE_INT_SHIFT	0
 #define EXYNOS_TMU_FALL_INT_MASK	0x111
-#define EXYNOS_TMU_FALL_INT_SHIFT	12
+#define EXYNOS_TMU_FALL_INT_SHIFT	16
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
+#define EXYNOS5250_TMU_CLEAR_FALL_INT_SHIFT	12
+#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
-- 
1.7.10.4

[PATCH 2/3 v6] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Chatradhi]

On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.

To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the "reg" property of the node.

As per Amit's suggestion, this patch changes the base_common
to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
 None
Changes since v2:
 Changed the flag name from SHARED_MEMORY to ADDRESS_MULTIPLE.
 https://lkml.org/lkml/2013/8/1/38
Changes since v3:
 None
Changes since v4:
 Corrected a compilation error, undeclared variable
Changes since v5:
 None

 .../devicetree/bindings/thermal/exynos-thermal.txt       |    4 ++--
 drivers/thermal/samsung/exynos_tmu.c                     |   14 +++++++-------
 drivers/thermal/samsung/exynos_tmu.h                     |    4 ++--
 drivers/thermal/samsung/exynos_tmu_data.c                |    2 +-
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 284f530..116cca0 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -11,8 +11,8 @@
 - reg : Address range of the thermal registers. For soc's which has multiple
 	instances of TMU and some registers are shared across all TMU's like
 	interrupt related then 2 set of register has to supplied. First set
-	belongs	to each instance of TMU and second set belongs to common TMU
-	registers.
+	belongs	to each instance of TMU and second set belongs to second set
+	of common TMU registers.
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index b2202fa..ae80a87 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -41,7 +41,7 @@
  * @id: identifier of the one instance of the TMU controller.
  * @pdata: pointer to the tmu platform/configuration data
  * @base: base address of the single instance of the TMU controller.
- * @base_common: base address of the common registers of the TMU controller.
+ * @base_second: base address of the common registers of the TMU controller.
  * @irq: irq number of the TMU controller.
  * @soc: id of the SOC type.
  * @irq_work: pointer to the irq work structure.
@@ -56,7 +56,7 @@ struct exynos_tmu_data {
 	int id;
 	struct exynos_tmu_platform_data *pdata;
 	void __iomem *base;
-	void __iomem *base_common;
+	void __iomem *base_second;
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -297,7 +297,7 @@ skip_calib_data:
 	}
 	/*Clear the PMIN in the common TMU register*/
 	if (reg->tmu_pmin && !data->id)
-		writel(0, data->base_common + reg->tmu_pmin);
+		writel(0, data->base_second + reg->tmu_pmin);
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
@@ -454,7 +454,7 @@ static void exynos_tmu_work(struct work_struct *work)
 
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
-		val_type = readl(data->base_common + reg->tmu_irqstatus);
+		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
@@ -579,7 +579,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 	 * Check if the TMU shares some registers and then try to map the
 	 * memory of common registers.
 	 */
-	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
+	if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
 		return 0;
 
 	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
@@ -587,9 +587,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	data->base_common = devm_ioremap(&pdev->dev, res.start,
+	data->base_second = devm_ioremap(&pdev->dev, res.start,
 					resource_size(&res));
-	if (!data->base_common) {
+	if (!data->base_second) {
 		dev_err(&pdev->dev, "Failed to ioremap memory\n");
 		return -ENOMEM;
 	}
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 5f4fe6c..d79264f 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -60,7 +60,7 @@ enum soc_type {
  *			state(active/idle) can be checked.
  * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
  *			sample time.
- * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
+ * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
  *			sensors shares some common registers.
  * TMU_SUPPORT - macro to compare the above features with the supplied.
  */
@@ -70,7 +70,7 @@ enum soc_type {
 #define TMU_SUPPORT_FALLING_TRIP		BIT(3)
 #define TMU_SUPPORT_READY_STATUS		BIT(4)
 #define TMU_SUPPORT_EMUL_TIME			BIT(5)
-#define TMU_SUPPORT_SHARED_MEMORY		BIT(6)
+#define TMU_SUPPORT_ADDRESS_MULTIPLE		BIT(6)
 
 #define TMU_SUPPORTS(a, b)	(a->features & TMU_SUPPORT_ ## b)
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 09a8a27..3d9ade5 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -257,7 +257,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.type = SOC_ARCH_EXYNOS5440, \
 	.registers = &exynos5440_tmu_registers, \
 	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
-			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
+			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 
 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 	.tmu_data = {
-- 
1.7.10.4

[PATCH 3/3 v6] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Chatradhi]

This patch adds the neccessary register changes and arch information
to support Exynos5420 SoCs
Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU

Also updated the Documentation at
Documentation/devicetree/bindings/thermal/exynos-thermal.txt

Note: The platform data structure will be handled properly once the driver
 moves to complete device driver solution.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
1. modified the platform data structure in order to pass SHARED flag
   for channels that need sharing of address space.
2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
   As the changes are minimum and can be added here.
Changes since v3:
   a. Rearraged the code alphabetically, make exynso5420 come before exynso5440
   b. Reduce code duplication in passing platform data by introducing a common macro
      Bartlomiej Zolnierkiewicz Thanks for review and suggestions
Changes since v4:
 None
Changes since v5:
 None

 .../devicetree/bindings/thermal/exynos-thermal.txt |   39 ++++++++
 drivers/thermal/samsung/exynos_tmu.c               |   12 ++-
 drivers/thermal/samsung/exynos_tmu.h               |    1 +
 drivers/thermal/samsung/exynos_tmu_data.c          |   99 ++++++++++++++++++++
 drivers/thermal/samsung/exynos_tmu_data.h          |    7 ++
 5 files changed, 157 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 116cca0..c5f9a74 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -6,6 +6,7 @@
 	       "samsung,exynos4412-tmu"
 	       "samsung,exynos4210-tmu"
 	       "samsung,exynos5250-tmu"
+	       "samsung,exynos5420-tmu"
 	       "samsung,exynos5440-tmu"
 - interrupt-parent : The phandle for the interrupt controller
 - reg : Address range of the thermal registers. For soc's which has multiple
@@ -13,6 +14,16 @@
 	interrupt related then 2 set of register has to supplied. First set
 	belongs	to each instance of TMU and second set belongs to second set
 	of common TMU registers.
+  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
+	channels 2, 3 and 4
+
+	TRIMINFO at 0x1006c000 contains data for TMU channel 3
+	TRIMINFO at 0x100a0000 contains data for TMU channel 4
+	TRIMINFO at 0x10068000 contains data for TMU channel 2
+
+	The misplaced register address is passed through devicetree as the
+	second base
+
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
@@ -43,6 +54,34 @@ Example 2):
 		clock-names = "tmu_apbif";
 	};
 
+Example 3): (In case of Exynos5420)
+	/* tmu for CPU2 */
+	tmu@10068000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+		interrupts = <0 184 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+	/* tmu for CPU3 */
+	tmu@1006c000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+		interrupts = <0 185 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+	/* tmu for GPU */
+	tmu@100a0000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
+		interrupts = <0 215 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
 Note: For multi-instance tmu each instance should have an alias correctly
 numbered in "aliases" node.
 
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index ae80a87..b54825a 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -186,7 +186,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
 		}
 	} else {
-		trim_info = readl(data->base + reg->triminfo_data);
+		/* On exynos5420 the triminfo register is in the shared space */
+		if (data->base_second && (data->soc == SOC_ARCH_EXYNOS5420))
+			trim_info = readl(data->base_second +
+							reg->triminfo_data);
+		else
+			trim_info = readl(data->base + reg->triminfo_data);
 	}
 	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
@@ -498,6 +503,10 @@ static const struct of_device_id exynos_tmu_match[] = {
 		.data = (void *)EXYNOS5250_TMU_DRV_DATA,
 	},
 	{
+		.compatible = "samsung,exynos5420-tmu",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
 		.compatible = "samsung,exynos5440-tmu",
 		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
 	},
@@ -635,6 +644,7 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 	if (pdata->type == SOC_ARCH_EXYNOS4210 ||
 	    pdata->type == SOC_ARCH_EXYNOS4412 ||
 	    pdata->type == SOC_ARCH_EXYNOS5250 ||
+	    pdata->type == SOC_ARCH_EXYNOS5420 ||
 	    pdata->type == SOC_ARCH_EXYNOS5440)
 		data->soc = pdata->type;
 	else {
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index d79264f..4b9be23 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -43,6 +43,7 @@ enum soc_type {
 	SOC_ARCH_EXYNOS4210 = 1,
 	SOC_ARCH_EXYNOS4412,
 	SOC_ARCH_EXYNOS5250,
+	SOC_ARCH_EXYNOS5420,
 	SOC_ARCH_EXYNOS5440,
 };
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 3d9ade5..7ad8248 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -195,6 +195,105 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+static const struct exynos_tmu_registers exynos5420_tmu_registers = {
+	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+	.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+	.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+	.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+	.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+	.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+	.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+	.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+	.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+	.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+	.tmu_status = EXYNOS_TMU_REG_STATUS,
+	.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
+	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
+	.tmu_inten = EXYNOS_TMU_REG_INTEN,
+	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
+	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+	/* INTEN_RISE3 Not availble in exynos5420 */
+	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
+	.emul_con = EXYNOS_EMUL_CON,
+	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+	.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define __EXYNOS5420_TMU_DATA	\
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.type = SOC_ARCH_EXYNOS5420, \
+	.registers = &exynos5420_tmu_registers, \
+
+#define EXYNOS5420_TMU_DATA \
+	__EXYNOS5420_TMU_DATA \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME)
+
+#define EXYNOS5420_TMU_DATA_SHARED \
+	__EXYNOS5420_TMU_DATA \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
+
+struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
+	.tmu_data = {
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+	},
+	.tmu_count = 5,
+};
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index 9c1e2c8..87ab693 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -158,6 +158,13 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
 #define EXYNOS5250_TMU_DRV_DATA (NULL)
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
+#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
+#else
+#define EXYNOS5420_TMU_DRV_DATA (NULL)
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
 #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
-- 
1.7.10.4

Re: [PATCH 1/3 v6] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register

[Bartlomiej Zolnierkiewicz]

Hi Naveen,

On Thursday, October 17, 2013 08:41:13 AM Naveen Krishna Chatradhi wrote:
> On Exynos5250, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT registers and at an offset of
> 12 in INTCLEAR register.
> 
> On Exynos5420, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT and INTCLEAR registers.
> 
> On Exynos5440,
> the FALL_IRQEN bits are at an offset of 4
> and the RISE_IRQEN bits are at an offset of 0
> 
> This patch introduces a new bit field intclr_fall_shift to handle the
> offset for exyns5250 and exynos5440
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> Changes since v1:
> Changes since v2:
> Changes since v3:
>   None
> Changes since v4:
>  Correct the CLEAR_FALL_INT_SHIFT for Exynos5250/Exynos5440
> Changes since v5:
>  Modify the commit message

Thank you but v5 had more issues which are not fixed yet. Please see below.

>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
>  drivers/thermal/samsung/exynos_tmu.h      |    2 ++
>  drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
>  drivers/thermal/samsung/exynos_tmu_data.h |    4 +++-
>  4 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index 32f38b9..b2202fa 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -265,7 +265,7 @@ skip_calib_data:
>  				data->base + reg->threshold_th1);
>  
>  		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
> -			(reg->inten_fall_mask << reg->inten_fall_shift),
> +			(reg->inten_fall_mask << reg->intclr_fall_shift),
>  				data->base + reg->tmu_intclear);
>  
>  		/* if last threshold limit is also present */
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 3fb6554..5f4fe6c 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -136,6 +136,7 @@ enum soc_type {
>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
>   * @tmu_intstat: Register containing the interrupt status values.
>   * @tmu_intclear: Register for clearing the raised interrupt status.
> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
>   * @emul_con: TMU emulation controller register.
>   * @emul_temp_shift: shift bits of emulation temperature.
>   * @emul_time_shift: shift bits of emulation time.
> @@ -207,6 +208,7 @@ struct exynos_tmu_registers {
>  	u32	tmu_intstat;
>  
>  	u32	tmu_intclear;
> +	u32	intclr_fall_shift;
>  
>  	u32	emul_con;
>  	u32	emul_temp_shift;
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 073c292..09a8a27 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -123,6 +123,7 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
>  	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>  	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>  	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +	.intclr_fall_shift = EXYNOS5250_TMU_CLEAR_FALL_INT_SHIFT,
>  	.emul_con = EXYNOS_EMUL_CON,
>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>  	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> @@ -228,6 +229,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>  	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
>  	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
>  	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
> +	.intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
>  	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
>  	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> index a1ea19d..9c1e2c8 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> @@ -69,9 +69,11 @@
>  #define EXYNOS_TMU_RISE_INT_MASK	0x111
>  #define EXYNOS_TMU_RISE_INT_SHIFT	0
>  #define EXYNOS_TMU_FALL_INT_MASK	0x111
> -#define EXYNOS_TMU_FALL_INT_SHIFT	12
> +#define EXYNOS_TMU_FALL_INT_SHIFT	16
>  #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
>  #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
> +#define EXYNOS5250_TMU_CLEAR_FALL_INT_SHIFT	12

The better name would be EXYNOS_TMU_CLEAR_FALL_INT_SHIFT because it is
also used on EXYNOS4412.

Also in patch #3 you should define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT
instead of re-using EXYNOS_TMU_FALL_INT_SHIFT.

Finally please remove no longer used inten_fall_shift field and related
defines (EXYNOS_TMU_FALL_INT_MASK and EXYNOS5440_TMU_FALL_INT_MASK).

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

> +#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
>  #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
>  #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12

Re: [PATCH 1/3 v6] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register

[Naveen Krishna Ch]

Hello Bartlomiej,

My reply is very long delayed sorry.

On 17 October 2013 15:33, Bartlomiej Zolnierkiewicz
<b.zolnierkie@samsung.com> wrote:
>
> Hi Naveen,
>
> On Thursday, October 17, 2013 08:41:13 AM Naveen Krishna Chatradhi wrote:
>> On Exynos5250, the FALL interrupt related en, status and clear bits are
>> available at an offset of
>> 16 in INTEN, INTSTAT registers and at an offset of
>> 12 in INTCLEAR register.
>>
>> On Exynos5420, the FALL interrupt related en, status and clear bits are
>> available at an offset of
>> 16 in INTEN, INTSTAT and INTCLEAR registers.
>>
>> On Exynos5440,
>> the FALL_IRQEN bits are at an offset of 4
>> and the RISE_IRQEN bits are at an offset of 0
>>
>> This patch introduces a new bit field intclr_fall_shift to handle the
>> offset for exyns5250 and exynos5440
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> ---
>> Changes since v1:
>> Changes since v2:
>> Changes since v3:
>>   None
>> Changes since v4:
>>  Correct the CLEAR_FALL_INT_SHIFT for Exynos5250/Exynos5440
>> Changes since v5:
>>  Modify the commit message
>
> Thank you but v5 had more issues which are not fixed yet. Please see below.
>
>>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
>>  drivers/thermal/samsung/exynos_tmu.h      |    2 ++
>>  drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
>>  drivers/thermal/samsung/exynos_tmu_data.h |    4 +++-
>>  4 files changed, 8 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>> index 32f38b9..b2202fa 100644
>> --- a/drivers/thermal/samsung/exynos_tmu.c
>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>> @@ -265,7 +265,7 @@ skip_calib_data:
>>                               data->base + reg->threshold_th1);
>>
>>               writel((reg->inten_rise_mask << reg->inten_rise_shift) |
>> -                     (reg->inten_fall_mask << reg->inten_fall_shift),
>> +                     (reg->inten_fall_mask << reg->intclr_fall_shift),
>>                               data->base + reg->tmu_intclear);
>>
>>               /* if last threshold limit is also present */
>> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
>> index 3fb6554..5f4fe6c 100644
>> --- a/drivers/thermal/samsung/exynos_tmu.h
>> +++ b/drivers/thermal/samsung/exynos_tmu.h
>> @@ -136,6 +136,7 @@ enum soc_type {
>>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
>>   * @tmu_intstat: Register containing the interrupt status values.
>>   * @tmu_intclear: Register for clearing the raised interrupt status.
>> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
>>   * @emul_con: TMU emulation controller register.
>>   * @emul_temp_shift: shift bits of emulation temperature.
>>   * @emul_time_shift: shift bits of emulation time.
>> @@ -207,6 +208,7 @@ struct exynos_tmu_registers {
>>       u32     tmu_intstat;
>>
>>       u32     tmu_intclear;
>> +     u32     intclr_fall_shift;
>>
>>       u32     emul_con;
>>       u32     emul_temp_shift;
>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
>> index 073c292..09a8a27 100644
>> --- a/drivers/thermal/samsung/exynos_tmu_data.c
>> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
>> @@ -123,6 +123,7 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
>>       .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>>       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>>       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
>> +     .intclr_fall_shift = EXYNOS5250_TMU_CLEAR_FALL_INT_SHIFT,
>>       .emul_con = EXYNOS_EMUL_CON,
>>       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>>       .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
>> @@ -228,6 +229,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>>       .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
>>       .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
>>       .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
>> +     .intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
>>       .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
>>       .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
>>       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
>> index a1ea19d..9c1e2c8 100644
>> --- a/drivers/thermal/samsung/exynos_tmu_data.h
>> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
>> @@ -69,9 +69,11 @@
>>  #define EXYNOS_TMU_RISE_INT_MASK     0x111
>>  #define EXYNOS_TMU_RISE_INT_SHIFT    0
>>  #define EXYNOS_TMU_FALL_INT_MASK     0x111
>> -#define EXYNOS_TMU_FALL_INT_SHIFT    12
>> +#define EXYNOS_TMU_FALL_INT_SHIFT    16
>>  #define EXYNOS_TMU_CLEAR_RISE_INT    0x111
>>  #define EXYNOS_TMU_CLEAR_FALL_INT    (0x111 << 12)
>> +#define EXYNOS5250_TMU_CLEAR_FALL_INT_SHIFT  12
>
> The better name would be EXYNOS_TMU_CLEAR_FALL_INT_SHIFT because it is
> also used on EXYNOS4412.
Okey will do that,
>
> Also in patch #3 you should define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT
> instead of re-using EXYNOS_TMU_FALL_INT_SHIFT.
Exynos5440 has so will make for exynos5420 aswell
>
> Finally please remove no longer used inten_fall_shift field and related
inten_fall_shift is not used will remove
> defines (EXYNOS_TMU_FALL_INT_MASK and EXYNOS5440_TMU_FALL_INT_MASK).
These macros are used for inten_fall_shift which is used at
drivers/thermal/samsung/exynos_tmu.c:273:
(reg->inten_fall_mask << reg->intclr_fall_shift),

>
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
>
>> +#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT  4
>>  #define EXYNOS_TMU_TRIP_MODE_SHIFT   13
>>  #define EXYNOS_TMU_TRIP_MODE_MASK    0x7
>>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT       12
>
Will repost soon.



-- 
Shine bright,
(: Nav :)

[PATCH 1/3 v7] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register

[Naveen Krishna Chatradhi]

struct

On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT registers and at an offset of
12 in INTCLEAR register.

On Exynos5420, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT and INTCLEAR registers.

On Exynos5440,
the FALL_IRQEN bits are at an offset of 4
and the RISE_IRQEN bits are at an offset of 0

This patch introduces a new bit field intclr_fall_shift to handle the
offset for exyns5250 and exynos5440

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
Changes since v2:
Changes since v3:
  None
Changes since v4:
 Correct the CLEAR_FALL_INT_SHIFT for Exynos5250/Exynos5440
Changes since v5:
 Modify the commit message
Changes since v6:
 - Use EXYNOS_TMU_CLEAR_FALL_INT_SHIFT instead of EXYNOS5250_TMU_CLEAR_FALL_INT_SHIFT
 as the same is being used for Exynos4412

 drivers/thermal/samsung/exynos_tmu.c      |    2 +-
 drivers/thermal/samsung/exynos_tmu.h      |    2 ++
 drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
 drivers/thermal/samsung/exynos_tmu_data.h |    4 +++-
 4 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 32f38b9..b2202fa 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -265,7 +265,7 @@ skip_calib_data:
 				data->base + reg->threshold_th1);
 
 		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
-			(reg->inten_fall_mask << reg->inten_fall_shift),
+			(reg->inten_fall_mask << reg->intclr_fall_shift),
 				data->base + reg->tmu_intclear);
 
 		/* if last threshold limit is also present */
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 3fb6554..5f4fe6c 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -136,6 +136,7 @@ enum soc_type {
  * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
  * @tmu_intstat: Register containing the interrupt status values.
  * @tmu_intclear: Register for clearing the raised interrupt status.
+ * @intclr_fall_shift: shift bits for interrupt clear fall 0
  * @emul_con: TMU emulation controller register.
  * @emul_temp_shift: shift bits of emulation temperature.
  * @emul_time_shift: shift bits of emulation time.
@@ -207,6 +208,7 @@ struct exynos_tmu_registers {
 	u32	tmu_intstat;
 
 	u32	tmu_intclear;
+	u32	intclr_fall_shift;
 
 	u32	emul_con;
 	u32	emul_temp_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 073c292..c6e67e9 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -123,6 +123,7 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 	.emul_con = EXYNOS_EMUL_CON,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -228,6 +229,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
+	.intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
 	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index a1ea19d..bb412bb 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -69,9 +69,11 @@
 #define EXYNOS_TMU_RISE_INT_MASK	0x111
 #define EXYNOS_TMU_RISE_INT_SHIFT	0
 #define EXYNOS_TMU_FALL_INT_MASK	0x111
-#define EXYNOS_TMU_FALL_INT_SHIFT	12
+#define EXYNOS_TMU_FALL_INT_SHIFT	16
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
+#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
+#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
-- 
1.7.10.4

[PATCH 2/3 v7] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Chatradhi]

On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.

To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the "reg" property of the node.

As per Amit's suggestion, this patch changes the base_common
to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
 None
Changes since v2:
 Changed the flag name from SHARED_MEMORY to ADDRESS_MULTIPLE.
 https://lkml.org/lkml/2013/8/1/38
Changes since v3:
 None
Changes since v4:
 Corrected a compilation error, undeclared variable
Changes since v5:
 None
Changes since v6:
 None


 .../devicetree/bindings/thermal/exynos-thermal.txt       |    4 ++--
 drivers/thermal/samsung/exynos_tmu.c                     |   14 +++++++-------
 drivers/thermal/samsung/exynos_tmu.h                     |    4 ++--
 drivers/thermal/samsung/exynos_tmu_data.c                |    2 +-
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 284f530..116cca0 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -11,8 +11,8 @@
 - reg : Address range of the thermal registers. For soc's which has multiple
 	instances of TMU and some registers are shared across all TMU's like
 	interrupt related then 2 set of register has to supplied. First set
-	belongs	to each instance of TMU and second set belongs to common TMU
-	registers.
+	belongs	to each instance of TMU and second set belongs to second set
+	of common TMU registers.
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index b2202fa..ae80a87 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -41,7 +41,7 @@
  * @id: identifier of the one instance of the TMU controller.
  * @pdata: pointer to the tmu platform/configuration data
  * @base: base address of the single instance of the TMU controller.
- * @base_common: base address of the common registers of the TMU controller.
+ * @base_second: base address of the common registers of the TMU controller.
  * @irq: irq number of the TMU controller.
  * @soc: id of the SOC type.
  * @irq_work: pointer to the irq work structure.
@@ -56,7 +56,7 @@ struct exynos_tmu_data {
 	int id;
 	struct exynos_tmu_platform_data *pdata;
 	void __iomem *base;
-	void __iomem *base_common;
+	void __iomem *base_second;
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -297,7 +297,7 @@ skip_calib_data:
 	}
 	/*Clear the PMIN in the common TMU register*/
 	if (reg->tmu_pmin && !data->id)
-		writel(0, data->base_common + reg->tmu_pmin);
+		writel(0, data->base_second + reg->tmu_pmin);
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
@@ -454,7 +454,7 @@ static void exynos_tmu_work(struct work_struct *work)
 
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
-		val_type = readl(data->base_common + reg->tmu_irqstatus);
+		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
@@ -579,7 +579,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 	 * Check if the TMU shares some registers and then try to map the
 	 * memory of common registers.
 	 */
-	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
+	if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
 		return 0;
 
 	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
@@ -587,9 +587,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	data->base_common = devm_ioremap(&pdev->dev, res.start,
+	data->base_second = devm_ioremap(&pdev->dev, res.start,
 					resource_size(&res));
-	if (!data->base_common) {
+	if (!data->base_second) {
 		dev_err(&pdev->dev, "Failed to ioremap memory\n");
 		return -ENOMEM;
 	}
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 5f4fe6c..d79264f 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -60,7 +60,7 @@ enum soc_type {
  *			state(active/idle) can be checked.
  * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
  *			sample time.
- * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
+ * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
  *			sensors shares some common registers.
  * TMU_SUPPORT - macro to compare the above features with the supplied.
  */
@@ -70,7 +70,7 @@ enum soc_type {
 #define TMU_SUPPORT_FALLING_TRIP		BIT(3)
 #define TMU_SUPPORT_READY_STATUS		BIT(4)
 #define TMU_SUPPORT_EMUL_TIME			BIT(5)
-#define TMU_SUPPORT_SHARED_MEMORY		BIT(6)
+#define TMU_SUPPORT_ADDRESS_MULTIPLE		BIT(6)
 
 #define TMU_SUPPORTS(a, b)	(a->features & TMU_SUPPORT_ ## b)
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index c6e67e9..ad424ad 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -257,7 +257,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.type = SOC_ARCH_EXYNOS5440, \
 	.registers = &exynos5440_tmu_registers, \
 	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
-			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
+			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 
 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 	.tmu_data = {
-- 
1.7.10.4

[PATCH 3/3 v7] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Chatradhi]

This patch adds the neccessary register changes and arch information
to support Exynos5420 SoCs
Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU

Also updated the Documentation at
Documentation/devicetree/bindings/thermal/exynos-thermal.txt

Note: The platform data structure will be handled properly once the driver
 moves to complete device driver solution.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
1. modified the platform data structure in order to pass SHARED flag
   for channels that need sharing of address space.
2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
   As the changes are minimum and can be added here.
Changes since v3:
   a. Rearraged the code alphabetically, make exynso5420 come before exynso5440
   b. Reduce code duplication in passing platform data by introducing a common macro
      Bartlomiej Zolnierkiewicz Thanks for review and suggestions
Changes since v4:
 None
Changes since v5:
 None
Changes since v6:
 - removed the unsued field "inten_fall_shift"
 - defined EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT instead of using EXYNOS_TMU_FALL_INT_SHIFT
 
 .../devicetree/bindings/thermal/exynos-thermal.txt |   39 ++++++++
 drivers/thermal/samsung/exynos_tmu.c               |   12 ++-
 drivers/thermal/samsung/exynos_tmu.h               |    1 +
 drivers/thermal/samsung/exynos_tmu_data.c          |   99 ++++++++++++++++++++
 drivers/thermal/samsung/exynos_tmu_data.h          |    7 ++
 5 files changed, 157 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 116cca0..c5f9a74 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -6,6 +6,7 @@
 	       "samsung,exynos4412-tmu"
 	       "samsung,exynos4210-tmu"
 	       "samsung,exynos5250-tmu"
+	       "samsung,exynos5420-tmu"
 	       "samsung,exynos5440-tmu"
 - interrupt-parent : The phandle for the interrupt controller
 - reg : Address range of the thermal registers. For soc's which has multiple
@@ -13,6 +14,16 @@
 	interrupt related then 2 set of register has to supplied. First set
 	belongs	to each instance of TMU and second set belongs to second set
 	of common TMU registers.
+  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
+	channels 2, 3 and 4
+
+	TRIMINFO at 0x1006c000 contains data for TMU channel 3
+	TRIMINFO at 0x100a0000 contains data for TMU channel 4
+	TRIMINFO at 0x10068000 contains data for TMU channel 2
+
+	The misplaced register address is passed through devicetree as the
+	second base
+
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
@@ -43,6 +54,34 @@ Example 2):
 		clock-names = "tmu_apbif";
 	};
 
+Example 3): (In case of Exynos5420)
+	/* tmu for CPU2 */
+	tmu@10068000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+		interrupts = <0 184 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+	/* tmu for CPU3 */
+	tmu@1006c000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+		interrupts = <0 185 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+	/* tmu for GPU */
+	tmu@100a0000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
+		interrupts = <0 215 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
 Note: For multi-instance tmu each instance should have an alias correctly
 numbered in "aliases" node.
 
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index ae80a87..b54825a 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -186,7 +186,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
 		}
 	} else {
-		trim_info = readl(data->base + reg->triminfo_data);
+		/* On exynos5420 the triminfo register is in the shared space */
+		if (data->base_second && (data->soc == SOC_ARCH_EXYNOS5420))
+			trim_info = readl(data->base_second +
+							reg->triminfo_data);
+		else
+			trim_info = readl(data->base + reg->triminfo_data);
 	}
 	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
@@ -498,6 +503,10 @@ static const struct of_device_id exynos_tmu_match[] = {
 		.data = (void *)EXYNOS5250_TMU_DRV_DATA,
 	},
 	{
+		.compatible = "samsung,exynos5420-tmu",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
 		.compatible = "samsung,exynos5440-tmu",
 		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
 	},
@@ -635,6 +644,7 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 	if (pdata->type == SOC_ARCH_EXYNOS4210 ||
 	    pdata->type == SOC_ARCH_EXYNOS4412 ||
 	    pdata->type == SOC_ARCH_EXYNOS5250 ||
+	    pdata->type == SOC_ARCH_EXYNOS5420 ||
 	    pdata->type == SOC_ARCH_EXYNOS5440)
 		data->soc = pdata->type;
 	else {
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index d79264f..4b9be23 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -43,6 +43,7 @@ enum soc_type {
 	SOC_ARCH_EXYNOS4210 = 1,
 	SOC_ARCH_EXYNOS4412,
 	SOC_ARCH_EXYNOS5250,
+	SOC_ARCH_EXYNOS5420,
 	SOC_ARCH_EXYNOS5440,
 };
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index ad424ad..c876b1e 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -195,6 +195,105 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+static const struct exynos_tmu_registers exynos5420_tmu_registers = {
+	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+	.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+	.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+	.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+	.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+	.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+	.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+	.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+	.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+	.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+	.tmu_status = EXYNOS_TMU_REG_STATUS,
+	.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
+	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
+	.tmu_inten = EXYNOS_TMU_REG_INTEN,
+	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
+	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+	/* INTEN_RISE3 Not availble in exynos5420 */
+	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
+	.emul_con = EXYNOS_EMUL_CON,
+	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+	.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define __EXYNOS5420_TMU_DATA	\
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.type = SOC_ARCH_EXYNOS5420, \
+	.registers = &exynos5420_tmu_registers, \
+
+#define EXYNOS5420_TMU_DATA \
+	__EXYNOS5420_TMU_DATA \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME)
+
+#define EXYNOS5420_TMU_DATA_SHARED \
+	__EXYNOS5420_TMU_DATA \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
+
+struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
+	.tmu_data = {
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+	},
+	.tmu_count = 5,
+};
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index bb412bb..eb2cb92 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -158,6 +158,13 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
 #define EXYNOS5250_TMU_DRV_DATA (NULL)
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
+#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
+#else
+#define EXYNOS5420_TMU_DRV_DATA (NULL)
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
 #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
-- 
1.7.10.4

Re: [PATCH 1/3 v6] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register

[Bartlomiej Zolnierkiewicz]

Hi,

On Wednesday, November 06, 2013 06:47:56 PM Naveen Krishna Ch wrote:
> Hello Bartlomiej,
> 
> My reply is very long delayed sorry.
> 
> On 17 October 2013 15:33, Bartlomiej Zolnierkiewicz
> <b.zolnierkie@samsung.com> wrote:
> >
> > Hi Naveen,
> >
> > On Thursday, October 17, 2013 08:41:13 AM Naveen Krishna Chatradhi wrote:
> >> On Exynos5250, the FALL interrupt related en, status and clear bits are
> >> available at an offset of
> >> 16 in INTEN, INTSTAT registers and at an offset of
> >> 12 in INTCLEAR register.
> >>
> >> On Exynos5420, the FALL interrupt related en, status and clear bits are
> >> available at an offset of
> >> 16 in INTEN, INTSTAT and INTCLEAR registers.
> >>
> >> On Exynos5440,
> >> the FALL_IRQEN bits are at an offset of 4
> >> and the RISE_IRQEN bits are at an offset of 0
> >>
> >> This patch introduces a new bit field intclr_fall_shift to handle the
> >> offset for exyns5250 and exynos5440
> >>
> >> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> >> ---
> >> Changes since v1:
> >> Changes since v2:
> >> Changes since v3:
> >>   None
> >> Changes since v4:
> >>  Correct the CLEAR_FALL_INT_SHIFT for Exynos5250/Exynos5440
> >> Changes since v5:
> >>  Modify the commit message
> >
> > Thank you but v5 had more issues which are not fixed yet. Please see below.
> >
> >>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
> >>  drivers/thermal/samsung/exynos_tmu.h      |    2 ++
> >>  drivers/thermal/samsung/exynos_tmu_data.c |    2 ++
> >>  drivers/thermal/samsung/exynos_tmu_data.h |    4 +++-
> >>  4 files changed, 8 insertions(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> >> index 32f38b9..b2202fa 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu.c
> >> +++ b/drivers/thermal/samsung/exynos_tmu.c
> >> @@ -265,7 +265,7 @@ skip_calib_data:
> >>                               data->base + reg->threshold_th1);
> >>
> >>               writel((reg->inten_rise_mask << reg->inten_rise_shift) |
> >> -                     (reg->inten_fall_mask << reg->inten_fall_shift),
> >> +                     (reg->inten_fall_mask << reg->intclr_fall_shift),
> >>                               data->base + reg->tmu_intclear);
> >>
> >>               /* if last threshold limit is also present */
> >> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> >> index 3fb6554..5f4fe6c 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu.h
> >> +++ b/drivers/thermal/samsung/exynos_tmu.h
> >> @@ -136,6 +136,7 @@ enum soc_type {
> >>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
> >>   * @tmu_intstat: Register containing the interrupt status values.
> >>   * @tmu_intclear: Register for clearing the raised interrupt status.
> >> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
> >>   * @emul_con: TMU emulation controller register.
> >>   * @emul_temp_shift: shift bits of emulation temperature.
> >>   * @emul_time_shift: shift bits of emulation time.
> >> @@ -207,6 +208,7 @@ struct exynos_tmu_registers {
> >>       u32     tmu_intstat;
> >>
> >>       u32     tmu_intclear;
> >> +     u32     intclr_fall_shift;
> >>
> >>       u32     emul_con;
> >>       u32     emul_temp_shift;
> >> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> >> index 073c292..09a8a27 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> >> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> >> @@ -123,6 +123,7 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
> >>       .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
> >>       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
> >>       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> >> +     .intclr_fall_shift = EXYNOS5250_TMU_CLEAR_FALL_INT_SHIFT,
> >>       .emul_con = EXYNOS_EMUL_CON,
> >>       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> >>       .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> >> @@ -228,6 +229,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
> >>       .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
> >>       .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
> >>       .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
> >> +     .intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
> >>       .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
> >>       .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
> >>       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> >> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> >> index a1ea19d..9c1e2c8 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> >> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> >> @@ -69,9 +69,11 @@
> >>  #define EXYNOS_TMU_RISE_INT_MASK     0x111
> >>  #define EXYNOS_TMU_RISE_INT_SHIFT    0
> >>  #define EXYNOS_TMU_FALL_INT_MASK     0x111
> >> -#define EXYNOS_TMU_FALL_INT_SHIFT    12
> >> +#define EXYNOS_TMU_FALL_INT_SHIFT    16
> >>  #define EXYNOS_TMU_CLEAR_RISE_INT    0x111
> >>  #define EXYNOS_TMU_CLEAR_FALL_INT    (0x111 << 12)
> >> +#define EXYNOS5250_TMU_CLEAR_FALL_INT_SHIFT  12
> >
> > The better name would be EXYNOS_TMU_CLEAR_FALL_INT_SHIFT because it is
> > also used on EXYNOS4412.
> Okey will do that,
> >
> > Also in patch #3 you should define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT
> > instead of re-using EXYNOS_TMU_FALL_INT_SHIFT.
> Exynos5440 has so will make for exynos5420 aswell
> >
> > Finally please remove no longer used inten_fall_shift field and related
> inten_fall_shift is not used will remove
> > defines (EXYNOS_TMU_FALL_INT_MASK and EXYNOS5440_TMU_FALL_INT_MASK).
> These macros are used for inten_fall_shift which is used at
> drivers/thermal/samsung/exynos_tmu.c:273:
> (reg->inten_fall_mask << reg->intclr_fall_shift),

I meant EXYNOS_TMU_FALL_INT_SHIFT and EXYNOS5440_TMU_FALL_INT_SHIFT macros,
sorry about the confusion.

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Re: [PATCH 3/3 v7] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Bartlomiej Zolnierkiewicz]

On Wednesday, November 06, 2013 06:58:45 PM Naveen Krishna Chatradhi wrote:
> This patch adds the neccessary register changes and arch information
> to support Exynos5420 SoCs
> Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
> 
> Also updated the Documentation at
> Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> 
> Note: The platform data structure will be handled properly once the driver
>  moves to complete device driver solution.
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> Changes since v1:
> 1. modified the platform data structure in order to pass SHARED flag
>    for channels that need sharing of address space.
> 2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
>    As the changes are minimum and can be added here.
> Changes since v3:
>    a. Rearraged the code alphabetically, make exynso5420 come before exynso5440
>    b. Reduce code duplication in passing platform data by introducing a common macro
>       Bartlomiej Zolnierkiewicz Thanks for review and suggestions
> Changes since v4:
>  None
> Changes since v5:
>  None
> Changes since v6:
>  - removed the unsued field "inten_fall_shift"

I cannot find this change in the patch below, also
this should be done in patch #1/3 not in #3/3.

>  - defined EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT instead of using EXYNOS_TMU_FALL_INT_SHIFT

The code below still uses EXYNOS_TMU_FALL_INT_SHIFT and
EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT is not defined anywhere.

Have you posted the right patches?

>  .../devicetree/bindings/thermal/exynos-thermal.txt |   39 ++++++++
>  drivers/thermal/samsung/exynos_tmu.c               |   12 ++-
>  drivers/thermal/samsung/exynos_tmu.h               |    1 +
>  drivers/thermal/samsung/exynos_tmu_data.c          |   99 ++++++++++++++++++++
>  drivers/thermal/samsung/exynos_tmu_data.h          |    7 ++
>  5 files changed, 157 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 116cca0..c5f9a74 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -6,6 +6,7 @@
>  	       "samsung,exynos4412-tmu"
>  	       "samsung,exynos4210-tmu"
>  	       "samsung,exynos5250-tmu"
> +	       "samsung,exynos5420-tmu"
>  	       "samsung,exynos5440-tmu"
>  - interrupt-parent : The phandle for the interrupt controller
>  - reg : Address range of the thermal registers. For soc's which has multiple
> @@ -13,6 +14,16 @@
>  	interrupt related then 2 set of register has to supplied. First set
>  	belongs	to each instance of TMU and second set belongs to second set
>  	of common TMU registers.
> +  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
> +	channels 2, 3 and 4
> +
> +	TRIMINFO at 0x1006c000 contains data for TMU channel 3
> +	TRIMINFO at 0x100a0000 contains data for TMU channel 4
> +	TRIMINFO at 0x10068000 contains data for TMU channel 2
> +
> +	The misplaced register address is passed through devicetree as the
> +	second base
> +
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> @@ -43,6 +54,34 @@ Example 2):
>  		clock-names = "tmu_apbif";
>  	};
>  
> +Example 3): (In case of Exynos5420)
> +	/* tmu for CPU2 */
> +	tmu@10068000 {
> +		compatible = "samsung,exynos5420-tmu";
> +		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
> +		interrupts = <0 184 0>;
> +		clocks = <&clock 318>;
> +		clock-names = "tmu_apbif";
> +	};
> +
> +	/* tmu for CPU3 */
> +	tmu@1006c000 {
> +		compatible = "samsung,exynos5420-tmu";
> +		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
> +		interrupts = <0 185 0>;
> +		clocks = <&clock 318>;
> +		clock-names = "tmu_apbif";
> +	};
> +
> +	/* tmu for GPU */
> +	tmu@100a0000 {
> +		compatible = "samsung,exynos5420-tmu";
> +		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
> +		interrupts = <0 215 0>;
> +		clocks = <&clock 318>;
> +		clock-names = "tmu_apbif";
> +	};
> +
>  Note: For multi-instance tmu each instance should have an alias correctly
>  numbered in "aliases" node.
>  
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index ae80a87..b54825a 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -186,7 +186,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>  			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>  		}
>  	} else {
> -		trim_info = readl(data->base + reg->triminfo_data);
> +		/* On exynos5420 the triminfo register is in the shared space */
> +		if (data->base_second && (data->soc == SOC_ARCH_EXYNOS5420))
> +			trim_info = readl(data->base_second +
> +							reg->triminfo_data);
> +		else
> +			trim_info = readl(data->base + reg->triminfo_data);
>  	}
>  	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>  	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
> @@ -498,6 +503,10 @@ static const struct of_device_id exynos_tmu_match[] = {
>  		.data = (void *)EXYNOS5250_TMU_DRV_DATA,
>  	},
>  	{
> +		.compatible = "samsung,exynos5420-tmu",
> +		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
> +	},
> +	{
>  		.compatible = "samsung,exynos5440-tmu",
>  		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
>  	},
> @@ -635,6 +644,7 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>  	if (pdata->type == SOC_ARCH_EXYNOS4210 ||
>  	    pdata->type == SOC_ARCH_EXYNOS4412 ||
>  	    pdata->type == SOC_ARCH_EXYNOS5250 ||
> +	    pdata->type == SOC_ARCH_EXYNOS5420 ||
>  	    pdata->type == SOC_ARCH_EXYNOS5440)
>  		data->soc = pdata->type;
>  	else {
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index d79264f..4b9be23 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -43,6 +43,7 @@ enum soc_type {
>  	SOC_ARCH_EXYNOS4210 = 1,
>  	SOC_ARCH_EXYNOS4412,
>  	SOC_ARCH_EXYNOS5250,
> +	SOC_ARCH_EXYNOS5420,
>  	SOC_ARCH_EXYNOS5440,
>  };
>  
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index ad424ad..c876b1e 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -195,6 +195,105 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
>  };
>  #endif
>  
> +#if defined(CONFIG_SOC_EXYNOS5420)
> +static const struct exynos_tmu_registers exynos5420_tmu_registers = {
> +	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
> +	.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
> +	.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
> +	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
> +	.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
> +	.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
> +	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
> +	.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
> +	.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
> +	.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
> +	.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
> +	.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
> +	.tmu_status = EXYNOS_TMU_REG_STATUS,
> +	.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
> +	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
> +	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
> +	.tmu_inten = EXYNOS_TMU_REG_INTEN,
> +	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> +	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> +	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
> +	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
> +	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
> +	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
> +	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
> +	/* INTEN_RISE3 Not availble in exynos5420 */
> +	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
> +	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
> +	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
> +	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +	.intclr_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
> +	.emul_con = EXYNOS_EMUL_CON,
> +	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> +	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> +	.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
> +};
> +
> +#define __EXYNOS5420_TMU_DATA	\
> +	.threshold_falling = 10, \
> +	.trigger_levels[0] = 85, \
> +	.trigger_levels[1] = 103, \
> +	.trigger_levels[2] = 110, \
> +	.trigger_levels[3] = 120, \
> +	.trigger_enable[0] = true, \
> +	.trigger_enable[1] = true, \
> +	.trigger_enable[2] = true, \
> +	.trigger_enable[3] = false, \
> +	.trigger_type[0] = THROTTLE_ACTIVE, \
> +	.trigger_type[1] = THROTTLE_ACTIVE, \
> +	.trigger_type[2] = SW_TRIP, \
> +	.trigger_type[3] = HW_TRIP, \
> +	.max_trigger_level = 4, \
> +	.gain = 8, \
> +	.reference_voltage = 16, \
> +	.noise_cancel_mode = 4, \
> +	.cal_type = TYPE_ONE_POINT_TRIMMING, \
> +	.efuse_value = 55, \
> +	.min_efuse_value = 40, \
> +	.max_efuse_value = 100, \
> +	.first_point_trim = 25, \
> +	.second_point_trim = 85, \
> +	.default_temp_offset = 50, \
> +	.freq_tab[0] = { \
> +		.freq_clip_max = 800 * 1000, \
> +		.temp_level = 85, \
> +	}, \
> +	.freq_tab[1] = { \
> +		.freq_clip_max = 200 * 1000, \
> +		.temp_level = 103, \
> +	}, \
> +	.freq_tab_count = 2, \
> +	.type = SOC_ARCH_EXYNOS5420, \
> +	.registers = &exynos5420_tmu_registers, \
> +
> +#define EXYNOS5420_TMU_DATA \
> +	__EXYNOS5420_TMU_DATA \
> +	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +			TMU_SUPPORT_EMUL_TIME)
> +
> +#define EXYNOS5420_TMU_DATA_SHARED \
> +	__EXYNOS5420_TMU_DATA \
> +	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
> +
> +struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
> +	.tmu_data = {
> +		{ EXYNOS5420_TMU_DATA },
> +		{ EXYNOS5420_TMU_DATA },
> +		{ EXYNOS5420_TMU_DATA_SHARED },
> +		{ EXYNOS5420_TMU_DATA_SHARED },
> +		{ EXYNOS5420_TMU_DATA_SHARED },
> +	},
> +	.tmu_count = 5,
> +};
> +#endif
> +
>  #if defined(CONFIG_SOC_EXYNOS5440)
>  static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>  	.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> index bb412bb..eb2cb92 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> @@ -158,6 +158,13 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
>  #define EXYNOS5250_TMU_DRV_DATA (NULL)
>  #endif
>  
> +#if defined(CONFIG_SOC_EXYNOS5420)
> +extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
> +#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
> +#else
> +#define EXYNOS5420_TMU_DRV_DATA (NULL)
> +#endif
> +
>  #if defined(CONFIG_SOC_EXYNOS5440)
>  extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
>  #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

[PATCH 1/3 v8] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register struct

[Naveen Krishna Chatradhi]

On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT registers and at an offset of
12 in INTCLEAR register.

On Exynos5420, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT and INTCLEAR registers.

On Exynos5440,
the FALL_IRQEN bits are at an offset of 4
and the RISE_IRQEN bits are at an offset of 0

This patch introduces a new bit field intclr_fall_shift to handle the
offset for exyns5250 and exynos5440
Also removes the unused macros EXYNOS_TMU_FALL_INT_SHIFT and
EXYNOS5440_TMU_FALL_INT_SHIFT, inten_fall_shift field

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
Changes since v2:
Changes since v3:
  None
Changes since v4:
 Correct the CLEAR_FALL_INT_SHIFT for Exynos5250/Exynos5440
Changes since v5:
 Modify the commit message
Changes since v6:
 - Use EXYNOS_TMU_CLEAR_FALL_INT_SHIFT instead of EXYNOS5250_TMU_CLEAR_FALL_INT_SHIFT
 as the same is being used for Exynos4412
Changes since v7:
 - also removes the unused macros EXYNOS_TMU_FALL_INT_SHIFT and
 EXYNOS5440_TMU_FALL_INT_SHIFT, inten_fall_shift field

 
 drivers/thermal/samsung/exynos_tmu.c      |    2 +-
 drivers/thermal/samsung/exynos_tmu.h      |    4 ++--
 drivers/thermal/samsung/exynos_tmu_data.c |    4 ++--
 drivers/thermal/samsung/exynos_tmu_data.h |    4 ++--
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 32f38b9..b2202fa 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -265,7 +265,7 @@ skip_calib_data:
 				data->base + reg->threshold_th1);
 
 		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
-			(reg->inten_fall_mask << reg->inten_fall_shift),
+			(reg->inten_fall_mask << reg->intclr_fall_shift),
 				data->base + reg->tmu_intclear);
 
 		/* if last threshold limit is also present */
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 3fb6554..39fca47 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -124,7 +124,6 @@ enum soc_type {
 	enable bits.
  * @inten_rise_shift: shift bits of all rising interrupt bits.
  * @inten_rise_mask: mask bits of all rising interrupt bits.
- * @inten_fall_shift: shift bits of all rising interrupt bits.
  * @inten_fall_mask: mask bits of all rising interrupt bits.
  * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
  * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
@@ -136,6 +135,7 @@ enum soc_type {
  * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
  * @tmu_intstat: Register containing the interrupt status values.
  * @tmu_intclear: Register for clearing the raised interrupt status.
+ * @intclr_fall_shift: shift bits for interrupt clear fall 0
  * @emul_con: TMU emulation controller register.
  * @emul_temp_shift: shift bits of emulation temperature.
  * @emul_time_shift: shift bits of emulation time.
@@ -193,7 +193,6 @@ struct exynos_tmu_registers {
 	u32	tmu_inten;
 	u32	inten_rise_shift;
 	u32	inten_rise_mask;
-	u32	inten_fall_shift;
 	u32	inten_fall_mask;
 	u32	inten_rise0_shift;
 	u32	inten_rise1_shift;
@@ -207,6 +206,7 @@ struct exynos_tmu_registers {
 	u32	tmu_intstat;
 
 	u32	tmu_intclear;
+	u32	intclr_fall_shift;
 
 	u32	emul_con;
 	u32	emul_temp_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 073c292..70ad559 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -115,7 +115,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
 	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
 	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
-	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
 	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
@@ -123,6 +122,7 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
 	.emul_con = EXYNOS_EMUL_CON,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -220,7 +220,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
 	.inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
 	.inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
-	.inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
 	.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
@@ -228,6 +227,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
+	.intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
 	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index a1ea19d..d9495a4 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -69,9 +69,10 @@
 #define EXYNOS_TMU_RISE_INT_MASK	0x111
 #define EXYNOS_TMU_RISE_INT_SHIFT	0
 #define EXYNOS_TMU_FALL_INT_MASK	0x111
-#define EXYNOS_TMU_FALL_INT_SHIFT	12
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
+#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
+#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
@@ -119,7 +120,6 @@
 #define EXYNOS5440_TMU_RISE_INT_MASK		0xf
 #define EXYNOS5440_TMU_RISE_INT_SHIFT		0
 #define EXYNOS5440_TMU_FALL_INT_MASK		0xf
-#define EXYNOS5440_TMU_FALL_INT_SHIFT		4
 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT	0
 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT	1
 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT	2
-- 
1.7.10.4

[PATCH 2/3 v8] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Chatradhi]

On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.

To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the "reg" property of the node.

As per Amit's suggestion, this patch changes the base_common
to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
 None
Changes since v2:
 Changed the flag name from SHARED_MEMORY to ADDRESS_MULTIPLE.
 https://lkml.org/lkml/2013/8/1/38
Changes since v3:
 None
Changes since v4:
 Corrected a compilation error, undeclared variable
Changes since v5:
 None
Changes since v6:
 None
Changes since v7:
 None

 .../devicetree/bindings/thermal/exynos-thermal.txt       |    4 ++--
 drivers/thermal/samsung/exynos_tmu.c                     |   14 +++++++-------
 drivers/thermal/samsung/exynos_tmu.h                     |    4 ++--
 drivers/thermal/samsung/exynos_tmu_data.c                |    2 +-
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 284f530..116cca0 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -11,8 +11,8 @@
 - reg : Address range of the thermal registers. For soc's which has multiple
 	instances of TMU and some registers are shared across all TMU's like
 	interrupt related then 2 set of register has to supplied. First set
-	belongs	to each instance of TMU and second set belongs to common TMU
-	registers.
+	belongs	to each instance of TMU and second set belongs to second set
+	of common TMU registers.
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index b2202fa..ae80a87 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -41,7 +41,7 @@
  * @id: identifier of the one instance of the TMU controller.
  * @pdata: pointer to the tmu platform/configuration data
  * @base: base address of the single instance of the TMU controller.
- * @base_common: base address of the common registers of the TMU controller.
+ * @base_second: base address of the common registers of the TMU controller.
  * @irq: irq number of the TMU controller.
  * @soc: id of the SOC type.
  * @irq_work: pointer to the irq work structure.
@@ -56,7 +56,7 @@ struct exynos_tmu_data {
 	int id;
 	struct exynos_tmu_platform_data *pdata;
 	void __iomem *base;
-	void __iomem *base_common;
+	void __iomem *base_second;
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -297,7 +297,7 @@ skip_calib_data:
 	}
 	/*Clear the PMIN in the common TMU register*/
 	if (reg->tmu_pmin && !data->id)
-		writel(0, data->base_common + reg->tmu_pmin);
+		writel(0, data->base_second + reg->tmu_pmin);
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
@@ -454,7 +454,7 @@ static void exynos_tmu_work(struct work_struct *work)
 
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
-		val_type = readl(data->base_common + reg->tmu_irqstatus);
+		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
@@ -579,7 +579,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 	 * Check if the TMU shares some registers and then try to map the
 	 * memory of common registers.
 	 */
-	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
+	if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
 		return 0;
 
 	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
@@ -587,9 +587,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	data->base_common = devm_ioremap(&pdev->dev, res.start,
+	data->base_second = devm_ioremap(&pdev->dev, res.start,
 					resource_size(&res));
-	if (!data->base_common) {
+	if (!data->base_second) {
 		dev_err(&pdev->dev, "Failed to ioremap memory\n");
 		return -ENOMEM;
 	}
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 39fca47..0591089 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -60,7 +60,7 @@ enum soc_type {
  *			state(active/idle) can be checked.
  * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
  *			sample time.
- * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
+ * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
  *			sensors shares some common registers.
  * TMU_SUPPORT - macro to compare the above features with the supplied.
  */
@@ -70,7 +70,7 @@ enum soc_type {
 #define TMU_SUPPORT_FALLING_TRIP		BIT(3)
 #define TMU_SUPPORT_READY_STATUS		BIT(4)
 #define TMU_SUPPORT_EMUL_TIME			BIT(5)
-#define TMU_SUPPORT_SHARED_MEMORY		BIT(6)
+#define TMU_SUPPORT_ADDRESS_MULTIPLE		BIT(6)
 
 #define TMU_SUPPORTS(a, b)	(a->features & TMU_SUPPORT_ ## b)
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 70ad559..a09047a 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -255,7 +255,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.type = SOC_ARCH_EXYNOS5440, \
 	.registers = &exynos5440_tmu_registers, \
 	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
-			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
+			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 
 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 	.tmu_data = {
-- 
1.7.10.4

[PATCH 3/3 v8] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Chatradhi]

This patch adds the neccessary register changes and arch information
to support Exynos5420 SoCs
Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU

Also updated the Documentation at
Documentation/devicetree/bindings/thermal/exynos-thermal.txt

Note: The platform data structure will be handled properly once the driver
 moves to complete device driver solution.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v1:
1. modified the platform data structure in order to pass SHARED flag
   for channels that need sharing of address space.
2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
   As the changes are minimum and can be added here.
Changes since v3:
   a. Rearraged the code alphabetically, make exynso5420 come before exynso5440
   b. Reduce code duplication in passing platform data by introducing a common macro
      Bartlomiej Zolnierkiewicz Thanks for review and suggestions
Changes since v4:
 None
Changes since v5:
 None
Changes since v6:
 - removed the unsued field "inten_fall_shift"
 - defined EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT instead of using EXYNOS_TMU_FALL_INT_SHIFT
Changes since v7:
 - changes ins v6 were moved to the patch 1/3 of this patchset.
 - defined EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT instead of using EXYNOS_TMU_FALL_INT_SHIFT
 
 .../devicetree/bindings/thermal/exynos-thermal.txt |   39 ++++++++
 drivers/thermal/samsung/exynos_tmu.c               |   12 ++-
 drivers/thermal/samsung/exynos_tmu.h               |    1 +
 drivers/thermal/samsung/exynos_tmu_data.c          |   98 ++++++++++++++++++++
 drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
 5 files changed, 157 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 116cca0..c5f9a74 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -6,6 +6,7 @@
 	       "samsung,exynos4412-tmu"
 	       "samsung,exynos4210-tmu"
 	       "samsung,exynos5250-tmu"
+	       "samsung,exynos5420-tmu"
 	       "samsung,exynos5440-tmu"
 - interrupt-parent : The phandle for the interrupt controller
 - reg : Address range of the thermal registers. For soc's which has multiple
@@ -13,6 +14,16 @@
 	interrupt related then 2 set of register has to supplied. First set
 	belongs	to each instance of TMU and second set belongs to second set
 	of common TMU registers.
+  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
+	channels 2, 3 and 4
+
+	TRIMINFO at 0x1006c000 contains data for TMU channel 3
+	TRIMINFO at 0x100a0000 contains data for TMU channel 4
+	TRIMINFO at 0x10068000 contains data for TMU channel 2
+
+	The misplaced register address is passed through devicetree as the
+	second base
+
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
@@ -43,6 +54,34 @@ Example 2):
 		clock-names = "tmu_apbif";
 	};
 
+Example 3): (In case of Exynos5420)
+	/* tmu for CPU2 */
+	tmu@10068000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+		interrupts = <0 184 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+	/* tmu for CPU3 */
+	tmu@1006c000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+		interrupts = <0 185 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+	/* tmu for GPU */
+	tmu@100a0000 {
+		compatible = "samsung,exynos5420-tmu";
+		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
+		interrupts = <0 215 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
 Note: For multi-instance tmu each instance should have an alias correctly
 numbered in "aliases" node.
 
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index ae80a87..b54825a 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -186,7 +186,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
 		}
 	} else {
-		trim_info = readl(data->base + reg->triminfo_data);
+		/* On exynos5420 the triminfo register is in the shared space */
+		if (data->base_second && (data->soc == SOC_ARCH_EXYNOS5420))
+			trim_info = readl(data->base_second +
+							reg->triminfo_data);
+		else
+			trim_info = readl(data->base + reg->triminfo_data);
 	}
 	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
@@ -498,6 +503,10 @@ static const struct of_device_id exynos_tmu_match[] = {
 		.data = (void *)EXYNOS5250_TMU_DRV_DATA,
 	},
 	{
+		.compatible = "samsung,exynos5420-tmu",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
 		.compatible = "samsung,exynos5440-tmu",
 		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
 	},
@@ -635,6 +644,7 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 	if (pdata->type == SOC_ARCH_EXYNOS4210 ||
 	    pdata->type == SOC_ARCH_EXYNOS4412 ||
 	    pdata->type == SOC_ARCH_EXYNOS5250 ||
+	    pdata->type == SOC_ARCH_EXYNOS5420 ||
 	    pdata->type == SOC_ARCH_EXYNOS5440)
 		data->soc = pdata->type;
 	else {
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 0591089..62a6667 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -43,6 +43,7 @@ enum soc_type {
 	SOC_ARCH_EXYNOS4210 = 1,
 	SOC_ARCH_EXYNOS4412,
 	SOC_ARCH_EXYNOS5250,
+	SOC_ARCH_EXYNOS5420,
 	SOC_ARCH_EXYNOS5440,
 };
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index a09047a..088a5aa 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -194,6 +194,104 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+static const struct exynos_tmu_registers exynos5420_tmu_registers = {
+	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+	.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+	.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+	.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+	.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+	.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+	.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+	.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+	.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+	.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+	.tmu_status = EXYNOS_TMU_REG_STATUS,
+	.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
+	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
+	.tmu_inten = EXYNOS_TMU_REG_INTEN,
+	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+	/* INTEN_RISE3 Not availble in exynos5420 */
+	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
+	.emul_con = EXYNOS_EMUL_CON,
+	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+	.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define __EXYNOS5420_TMU_DATA	\
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.type = SOC_ARCH_EXYNOS5420, \
+	.registers = &exynos5420_tmu_registers, \
+
+#define EXYNOS5420_TMU_DATA \
+	__EXYNOS5420_TMU_DATA \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME)
+
+#define EXYNOS5420_TMU_DATA_SHARED \
+	__EXYNOS5420_TMU_DATA \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
+
+struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
+	.tmu_data = {
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+	},
+	.tmu_count = 5,
+};
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index d9495a4..41f06dc 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -72,6 +72,7 @@
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
 #define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
+#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT	16
 #define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
@@ -156,6 +157,13 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
 #define EXYNOS5250_TMU_DRV_DATA (NULL)
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
+#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
+#else
+#define EXYNOS5420_TMU_DRV_DATA (NULL)
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
 #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
-- 
1.7.10.4

Re: [PATCH 1/3 v8] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register struct

[Bartlomiej Zolnierkiewicz]

Hi,

On Thursday, November 07, 2013 11:22:42 AM Naveen Krishna Chatradhi wrote:
> On Exynos5250, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT registers and at an offset of
> 12 in INTCLEAR register.
> 
> On Exynos5420, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT and INTCLEAR registers.
> 
> On Exynos5440,
> the FALL_IRQEN bits are at an offset of 4
> and the RISE_IRQEN bits are at an offset of 0
> 
> This patch introduces a new bit field intclr_fall_shift to handle the
> offset for exyns5250 and exynos5440
> Also removes the unused macros EXYNOS_TMU_FALL_INT_SHIFT and
> EXYNOS5440_TMU_FALL_INT_SHIFT, inten_fall_shift field

Thanks for fixing this.  All three patches look good to me now.

Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

Re: [PATCH 1/3 v8] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register struct

[Naveen Krishna Ch]

Hi Bartlomiej,

On 7 November 2013 16:18, Bartlomiej Zolnierkiewicz
<b.zolnierkie@samsung.com> wrote:
>
> Hi,
>
> On Thursday, November 07, 2013 11:22:42 AM Naveen Krishna Chatradhi wrote:
>> On Exynos5250, the FALL interrupt related en, status and clear bits are
>> available at an offset of
>> 16 in INTEN, INTSTAT registers and at an offset of
>> 12 in INTCLEAR register.
>>
>> On Exynos5420, the FALL interrupt related en, status and clear bits are
>> available at an offset of
>> 16 in INTEN, INTSTAT and INTCLEAR registers.
>>
>> On Exynos5440,
>> the FALL_IRQEN bits are at an offset of 4
>> and the RISE_IRQEN bits are at an offset of 0
>>
>> This patch introduces a new bit field intclr_fall_shift to handle the
>> offset for exyns5250 and exynos5440
>> Also removes the unused macros EXYNOS_TMU_FALL_INT_SHIFT and
>> EXYNOS5440_TMU_FALL_INT_SHIFT, inten_fall_shift field
>
> Thanks for fixing this.  All three patches look good to me now.
>
> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>

Thanks for all the following up.
>
> Best regards,
> --
> Bartlomiej Zolnierkiewicz
> Samsung R&D Institute Poland
> Samsung Electronics
>



-- 
Shine bright,
(: Nav :)

Re: [PATCH 1/3 v8] thermal: samsung: add intclr_fall_shift bit in exynos_tmu_register struct

[Tomasz Figa]

Hi Naveen,

On Thursday 07 of November 2013 11:22:42 Naveen Krishna Chatradhi wrote:
> On Exynos5250, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT registers and at an offset of
> 12 in INTCLEAR register.
> 
> On Exynos5420, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT and INTCLEAR registers.
> 
> On Exynos5440,
> the FALL_IRQEN bits are at an offset of 4
> and the RISE_IRQEN bits are at an offset of 0
> 
> This patch introduces a new bit field intclr_fall_shift to handle the
> offset for exyns5250 and exynos5440
> Also removes the unused macros EXYNOS_TMU_FALL_INT_SHIFT and
> EXYNOS5440_TMU_FALL_INT_SHIFT, inten_fall_shift field

>From what I can see in this patch, the field intclr_fall_shift is not
really introduced, but rather inten_fall_shift is renamed to it. Please
match patch description with what the patch actually does.

I believe this patch is also touches code and data related to Exynos 4x12
SoCs, but the description only covers Exynos 5 SoCs.

In addition, if this patch does not introduce any functional changes,
but only refactors some code, the description should say so.

Also, please see my comment below.

> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> Changes since v1:
> Changes since v2:
> Changes since v3:
>   None
> Changes since v4:
>  Correct the CLEAR_FALL_INT_SHIFT for Exynos5250/Exynos5440
> Changes since v5:
>  Modify the commit message
> Changes since v6:
>  - Use EXYNOS_TMU_CLEAR_FALL_INT_SHIFT instead of EXYNOS5250_TMU_CLEAR_FALL_INT_SHIFT
>  as the same is being used for Exynos4412
> Changes since v7:
>  - also removes the unused macros EXYNOS_TMU_FALL_INT_SHIFT and
>  EXYNOS5440_TMU_FALL_INT_SHIFT, inten_fall_shift field
> 
>  
>  drivers/thermal/samsung/exynos_tmu.c      |    2 +-
>  drivers/thermal/samsung/exynos_tmu.h      |    4 ++--
>  drivers/thermal/samsung/exynos_tmu_data.c |    4 ++--
>  drivers/thermal/samsung/exynos_tmu_data.h |    4 ++--
>  4 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index 32f38b9..b2202fa 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -265,7 +265,7 @@ skip_calib_data:
>  				data->base + reg->threshold_th1);
>  
>  		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
> -			(reg->inten_fall_mask << reg->inten_fall_shift),
> +			(reg->inten_fall_mask << reg->intclr_fall_shift),

Shouldn't also the mask values be called intclr_*_mask? They seem to
be used only with tmu_intclear register. Same goes for inten_fall_shift,

Best regards,
Tomasz

Re: [PATCH 3/3 v8] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Tomasz Figa]

Hi Naveen,

On Thursday 07 of November 2013 11:23:32 Naveen Krishna Chatradhi wrote:
> This patch adds the neccessary register changes and arch information
> to support Exynos5420 SoCs
> Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
> 
> Also updated the Documentation at
> Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> 
> Note: The platform data structure will be handled properly once the driver
>  moves to complete device driver solution.

Huh? I'm not sure what do you mean here.

> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> Changes since v1:
> 1. modified the platform data structure in order to pass SHARED flag
>    for channels that need sharing of address space.
> 2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
>    As the changes are minimum and can be added here.
> Changes since v3:
>    a. Rearraged the code alphabetically, make exynso5420 come before exynso5440
>    b. Reduce code duplication in passing platform data by introducing a common macro
>       Bartlomiej Zolnierkiewicz Thanks for review and suggestions
> Changes since v4:
>  None
> Changes since v5:
>  None
> Changes since v6:
>  - removed the unsued field "inten_fall_shift"
>  - defined EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT instead of using EXYNOS_TMU_FALL_INT_SHIFT
> Changes since v7:
>  - changes ins v6 were moved to the patch 1/3 of this patchset.
>  - defined EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT instead of using EXYNOS_TMU_FALL_INT_SHIFT
>  
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   39 ++++++++
>  drivers/thermal/samsung/exynos_tmu.c               |   12 ++-
>  drivers/thermal/samsung/exynos_tmu.h               |    1 +
>  drivers/thermal/samsung/exynos_tmu_data.c          |   98 ++++++++++++++++++++
>  drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
>  5 files changed, 157 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 116cca0..c5f9a74 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -6,6 +6,7 @@
>  	       "samsung,exynos4412-tmu"
>  	       "samsung,exynos4210-tmu"
>  	       "samsung,exynos5250-tmu"
> +	       "samsung,exynos5420-tmu"

I would add a second compatible value here for TMU units that have
misplaced TRIMINFO data, e.g. "samsung,exynos5420-tmu-broken-triminfo"
and explicitly specify that second reg and clock-names entry is required
for this compatible value.

>  	       "samsung,exynos5440-tmu"
>  - interrupt-parent : The phandle for the interrupt controller
>  - reg : Address range of the thermal registers. For soc's which has multiple
> @@ -13,6 +14,16 @@
>  	interrupt related then 2 set of register has to supplied. First set
>  	belongs	to each instance of TMU and second set belongs to second set
>  	of common TMU registers.

nit: A blank line here would be nice.

> +  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
> +	channels 2, 3 and 4
> +
> +	TRIMINFO at 0x1006c000 contains data for TMU channel 3
> +	TRIMINFO at 0x100a0000 contains data for TMU channel 4
> +	TRIMINFO at 0x10068000 contains data for TMU channel 2
> +
> +	The misplaced register address is passed through devicetree as the
> +	second base
> +
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> @@ -43,6 +54,34 @@ Example 2):
>  		clock-names = "tmu_apbif";
>  	};
>  
> +Example 3): (In case of Exynos5420)

Maybe "in case of misplaced TRIMINFO register" would be better?

> +	/* tmu for CPU2 */
> +	tmu@10068000 {
> +		compatible = "samsung,exynos5420-tmu";
> +		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
> +		interrupts = <0 184 0>;
> +		clocks = <&clock 318>;
> +		clock-names = "tmu_apbif";
> +	};
> +

I believe that just a single example of a node for a TMU with misplaced
TRIMINFO register will be enough.

> +	/* tmu for CPU3 */
> +	tmu@1006c000 {
> +		compatible = "samsung,exynos5420-tmu";
> +		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
> +		interrupts = <0 185 0>;
> +		clocks = <&clock 318>;
> +		clock-names = "tmu_apbif";
> +	};
> +
> +	/* tmu for GPU */
> +	tmu@100a0000 {
> +		compatible = "samsung,exynos5420-tmu";
> +		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
> +		interrupts = <0 215 0>;
> +		clocks = <&clock 318>;
> +		clock-names = "tmu_apbif";
> +	};
> +
>  Note: For multi-instance tmu each instance should have an alias correctly
>  numbered in "aliases" node.
>  
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index ae80a87..b54825a 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -186,7 +186,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>  			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>  		}
>  	} else {
> -		trim_info = readl(data->base + reg->triminfo_data);
> +		/* On exynos5420 the triminfo register is in the shared space */
> +		if (data->base_second && (data->soc == SOC_ARCH_EXYNOS5420))

This is ugly. What about having a quirk based description, that would
allow to have code like this (just an example, not ready code):

	if (data->quirks & EXYNOS_TMU_MISPLACED_TRIMINFO)

> +			trim_info = readl(data->base_second +
> +							reg->triminfo_data);
> +		else
> +			trim_info = readl(data->base + reg->triminfo_data);
>  	}
>  	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>  	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
> @@ -498,6 +503,10 @@ static const struct of_device_id exynos_tmu_match[] = {
[snip]
> +#define EXYNOS5420_TMU_DATA \
> +	__EXYNOS5420_TMU_DATA \
> +	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +			TMU_SUPPORT_EMUL_TIME)
> +
> +#define EXYNOS5420_TMU_DATA_SHARED \
> +	__EXYNOS5420_TMU_DATA \
> +	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
> +
> +struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
> +	.tmu_data = {
> +		{ EXYNOS5420_TMU_DATA },
> +		{ EXYNOS5420_TMU_DATA },
> +		{ EXYNOS5420_TMU_DATA_SHARED },
> +		{ EXYNOS5420_TMU_DATA_SHARED },
> +		{ EXYNOS5420_TMU_DATA_SHARED },
> +	},
> +	.tmu_count = 5,
> +};

Is this, by any chance, matching by some kind of block index? If yes, this
is awfully broken, when all of them are separate IP blocks.

What if an SoC shows up with particular TMU channels compatible with
Exynos 5420, but ordered differently? (e.g. GPU, CPU0, CPU2, CPU1, CPU3)

Instead, such data as contained in exynos_tmu_init_data should be rather
determined by IP compatible value, just as I suggested earlier in this
post.

Best regards,
Tomasz

Re: [PATCH 3/3 v8] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Ch]

Hello Tomasz,

On 7 November 2013 20:39, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Naveen,
>
> On Thursday 07 of November 2013 11:23:32 Naveen Krishna Chatradhi wrote:
>> This patch adds the neccessary register changes and arch information
>> to support Exynos5420 SoCs
>> Exynos5420 has 5 TMU channels one for each CPU 0, 1, 2 and 3 and GPU
>>
>> Also updated the Documentation at
>> Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>
>> Note: The platform data structure will be handled properly once the driver
>>  moves to complete device driver solution.
>
> Huh? I'm not sure what do you mean here.
This driver is handling platform data from a predefined structs in driver files.
Platform data is better handled when sent via Device tree nodes.

Will take up the device tree migration once this set is done.
>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> ---
>> Changes since v1:
>> 1. modified the platform data structure in order to pass SHARED flag
>>    for channels that need sharing of address space.
>> 2. https://lkml.org/lkml/2013/8/1/38 is merged into this patch.
>>    As the changes are minimum and can be added here.
>> Changes since v3:
>>    a. Rearraged the code alphabetically, make exynso5420 come before exynso5440
>>    b. Reduce code duplication in passing platform data by introducing a common macro
>>       Bartlomiej Zolnierkiewicz Thanks for review and suggestions
>> Changes since v4:
>>  None
>> Changes since v5:
>>  None
>> Changes since v6:
>>  - removed the unsued field "inten_fall_shift"
>>  - defined EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT instead of using EXYNOS_TMU_FALL_INT_SHIFT
>> Changes since v7:
>>  - changes ins v6 were moved to the patch 1/3 of this patchset.
>>  - defined EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT instead of using EXYNOS_TMU_FALL_INT_SHIFT
>>
>>  .../devicetree/bindings/thermal/exynos-thermal.txt |   39 ++++++++
>>  drivers/thermal/samsung/exynos_tmu.c               |   12 ++-
>>  drivers/thermal/samsung/exynos_tmu.h               |    1 +
>>  drivers/thermal/samsung/exynos_tmu_data.c          |   98 ++++++++++++++++++++
>>  drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
>>  5 files changed, 157 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> index 116cca0..c5f9a74 100644
>> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> @@ -6,6 +6,7 @@
>>              "samsung,exynos4412-tmu"
>>              "samsung,exynos4210-tmu"
>>              "samsung,exynos5250-tmu"
>> +            "samsung,exynos5420-tmu"
>
> I would add a second compatible value here for TMU units that have
> misplaced TRIMINFO data, e.g. "samsung,exynos5420-tmu-broken-triminfo"
> and explicitly specify that second reg and clock-names entry is required
> for this compatible value.
Sure
>
>>              "samsung,exynos5440-tmu"
>>  - interrupt-parent : The phandle for the interrupt controller
>>  - reg : Address range of the thermal registers. For soc's which has multiple
>> @@ -13,6 +14,16 @@
>>       interrupt related then 2 set of register has to supplied. First set
>>       belongs to each instance of TMU and second set belongs to second set
>>       of common TMU registers.
>
> nit: A blank line here would be nice.
>
>> +  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
>> +     channels 2, 3 and 4
>> +
>> +     TRIMINFO at 0x1006c000 contains data for TMU channel 3
>> +     TRIMINFO at 0x100a0000 contains data for TMU channel 4
>> +     TRIMINFO at 0x10068000 contains data for TMU channel 2
>> +
>> +     The misplaced register address is passed through devicetree as the
>> +     second base
>> +
>>  - interrupts : Should contain interrupt for thermal system
>>  - clocks : The main clock for TMU device
>>  - clock-names : Thermal system clock name
>> @@ -43,6 +54,34 @@ Example 2):
>>               clock-names = "tmu_apbif";
>>       };
>>
>> +Example 3): (In case of Exynos5420)
>
> Maybe "in case of misplaced TRIMINFO register" would be better?
Sure
>
>> +     /* tmu for CPU2 */
>> +     tmu@10068000 {
>> +             compatible = "samsung,exynos5420-tmu";
>> +             reg = <0x10068000 0x100>, <0x1006c000 0x4>;
>> +             interrupts = <0 184 0>;
>> +             clocks = <&clock 318>;
>> +             clock-names = "tmu_apbif";
>> +     };
>> +
>
> I believe that just a single example of a node for a TMU with misplaced
> TRIMINFO register will be enough.
right
>
>> +     /* tmu for CPU3 */
>> +     tmu@1006c000 {
>> +             compatible = "samsung,exynos5420-tmu";
>> +             reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
>> +             interrupts = <0 185 0>;
>> +             clocks = <&clock 318>;
>> +             clock-names = "tmu_apbif";
>> +     };
>> +
>> +     /* tmu for GPU */
>> +     tmu@100a0000 {
>> +             compatible = "samsung,exynos5420-tmu";
>> +             reg = <0x100a0000 0x100>, <0x10068000 0x4>;
>> +             interrupts = <0 215 0>;
>> +             clocks = <&clock 318>;
>> +             clock-names = "tmu_apbif";
>> +     };
>> +
>>  Note: For multi-instance tmu each instance should have an alias correctly
>>  numbered in "aliases" node.
>>
>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>> index ae80a87..b54825a 100644
>> --- a/drivers/thermal/samsung/exynos_tmu.c
>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>> @@ -186,7 +186,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>>                       EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>>               }
>>       } else {
>> -             trim_info = readl(data->base + reg->triminfo_data);
>> +             /* On exynos5420 the triminfo register is in the shared space */
>> +             if (data->base_second && (data->soc == SOC_ARCH_EXYNOS5420))
>
> This is ugly. What about having a quirk based description, that would
> allow to have code like this (just an example, not ready code):
Right now the driverdata is a struct containing the register bases and
various operation
values for TMU, along with the soc specific details.
Will implement quirks, along with proper device tree migration of platform data
>
>         if (data->quirks & EXYNOS_TMU_MISPLACED_TRIMINFO)
>
>> +                     trim_info = readl(data->base_second +
>> +                                                     reg->triminfo_data);
>> +             else
>> +                     trim_info = readl(data->base + reg->triminfo_data);
>>       }
>>       data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>>       data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
>> @@ -498,6 +503,10 @@ static const struct of_device_id exynos_tmu_match[] = {
> [snip]
>> +#define EXYNOS5420_TMU_DATA \
>> +     __EXYNOS5420_TMU_DATA \
>> +     .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
>> +                     TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
>> +                     TMU_SUPPORT_EMUL_TIME)
>> +
>> +#define EXYNOS5420_TMU_DATA_SHARED \
>> +     __EXYNOS5420_TMU_DATA \
>> +     .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
>> +                     TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
>> +                     TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
>> +
>> +struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
>> +     .tmu_data = {
>> +             { EXYNOS5420_TMU_DATA },
>> +             { EXYNOS5420_TMU_DATA },
>> +             { EXYNOS5420_TMU_DATA_SHARED },
>> +             { EXYNOS5420_TMU_DATA_SHARED },
>> +             { EXYNOS5420_TMU_DATA_SHARED },
>> +     },
>> +     .tmu_count = 5,
>> +};
>
> Is this, by any chance, matching by some kind of block index? If yes, this
> is awfully broken, when all of them are separate IP blocks.
I guess not.
>
> What if an SoC shows up with particular TMU channels compatible with
> Exynos 5420, but ordered differently? (e.g. GPU, CPU0, CPU2, CPU1, CPU3)
>
> Instead, such data as contained in exynos_tmu_init_data should be rather
> determined by IP compatible value, just as I suggested earlier in this
> post.
Right, will handling this along with device tree migration of platform data
>
> Best regards,
> Tomasz
>



-- 
Shine bright,
(: Nav :)

[PATCH 0/3] thermal: samsung: Clean up and add support for Exynos5420

[Naveen Krishna Chatradhi]

This patchset does a little clean up of the existing code
1.  [v9] thermal: samsung: replace inten_ bit fields with intclr_
2.  [v9] thermal: samsung: change base_common to more meaningful base_second

adds support for Exynos5420 in the driver and
3.  [v9] thermal: samsung: Add TMU support for Exynos5420 SoCs
also adds the device tree nodes for the same to exynos5420.dtsi (linux-samsung.git)
4.  [v3] ARM: dts: Exynos5420: Add device nodes for TMU blocks

Naveen Krishna Chatradhi (3):
  thermal: samsung: replace inten_ bit fields with intclr_
  thermal: samsung: change base_common to more meaningful base_second
  thermal: samsung: Add TMU support for Exynos5420 SoCs
  ARM: dts: Exynos5420: Add device nodes for TMU blocks

 .../devicetree/bindings/thermal/exynos-thermal.txt |   49 +++++++-
 drivers/thermal/samsung/exynos_tmu.c               |   78 +++++++++---
 drivers/thermal/samsung/exynos_tmu.h               |   22 ++--
 drivers/thermal/samsung/exynos_tmu_data.c          |  126 ++++++++++++++++++--
 drivers/thermal/samsung/exynos_tmu_data.h          |   12 +-
 5 files changed, 249 insertions(+), 38 deletions(-)

-- 
1.7.10.4

[PATCH 1/4 v9] thermal: samsung: replace inten_ bit fields with intclr_

[Naveen Krishna Chatradhi]

This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only used
to configure intclr related registers.

Description of H/W:
The offset for the bits in the CLEAR register are not consistent across TMU
modules in Exynso5250, 5420 and 5440.

On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT registers and at an offset of
12 in INTCLEAR register.

On Exynos5420, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT and INTCLEAR registers.

On Exynos5440,
the FALL_IRQEN bits are at an offset of 4
and the RISE_IRQEN bits are at an offset of 0

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v8:
1. Modified the patch description,
2. replaces the inten_rise/fall_shift/mask with intclr_rise/fall_shift/mask

 drivers/thermal/samsung/exynos_tmu.c      |    6 +++---
 drivers/thermal/samsung/exynos_tmu.h      |   16 ++++++++--------
 drivers/thermal/samsung/exynos_tmu_data.c |   18 +++++++++---------
 drivers/thermal/samsung/exynos_tmu_data.h |    4 ++--
 4 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 32f38b9..c493245 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -237,7 +237,7 @@ skip_calib_data:
 			writeb(pdata->trigger_levels[i], data->base +
 			reg->threshold_th0 + i * sizeof(reg->threshold_th0));
 
-		writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
+		writel(reg->intclr_rise_mask, data->base + reg->tmu_intclear);
 	} else {
 		/* Write temperature code for rising and falling threshold */
 		for (i = 0;
@@ -264,8 +264,8 @@ skip_calib_data:
 		writel(falling_threshold,
 				data->base + reg->threshold_th1);
 
-		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
-			(reg->inten_fall_mask << reg->inten_fall_shift),
+		writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |
+			(reg->intclr_fall_mask << reg->intclr_fall_shift),
 				data->base + reg->tmu_intclear);
 
 		/* if last threshold limit is also present */
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 3fb6554..980859a 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -122,10 +122,6 @@ enum soc_type {
  * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
  * @tmu_inten: register containing the different threshold interrupt
 	enable bits.
- * @inten_rise_shift: shift bits of all rising interrupt bits.
- * @inten_rise_mask: mask bits of all rising interrupt bits.
- * @inten_fall_shift: shift bits of all rising interrupt bits.
- * @inten_fall_mask: mask bits of all rising interrupt bits.
  * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
  * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
  * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
@@ -136,6 +132,10 @@ enum soc_type {
  * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
  * @tmu_intstat: Register containing the interrupt status values.
  * @tmu_intclear: Register for clearing the raised interrupt status.
+ * @intclr_fall_shift: shift bits for interrupt clear fall 0
+ * @intclr_rise_shift: shift bits of all rising interrupt bits.
+ * @intclr_rise_mask: mask bits of all rising interrupt bits.
+ * @intclr_fall_mask: mask bits of all rising interrupt bits.
  * @emul_con: TMU emulation controller register.
  * @emul_temp_shift: shift bits of emulation temperature.
  * @emul_time_shift: shift bits of emulation time.
@@ -191,10 +191,6 @@ struct exynos_tmu_registers {
 	u32	threshold_th3_l0_shift;
 
 	u32	tmu_inten;
-	u32	inten_rise_shift;
-	u32	inten_rise_mask;
-	u32	inten_fall_shift;
-	u32	inten_fall_mask;
 	u32	inten_rise0_shift;
 	u32	inten_rise1_shift;
 	u32	inten_rise2_shift;
@@ -207,6 +203,10 @@ struct exynos_tmu_registers {
 	u32	tmu_intstat;
 
 	u32	tmu_intclear;
+	u32	intclr_fall_shift;
+	u32	intclr_rise_shift;
+	u32	intclr_fall_mask;
+	u32	intclr_rise_mask;
 
 	u32	emul_con;
 	u32	emul_temp_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 073c292..7cdb04e 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -40,13 +40,13 @@ static const struct exynos_tmu_registers exynos4210_tmu_registers = {
 	.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
 	.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
 	.tmu_inten = EXYNOS_TMU_REG_INTEN,
-	.inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
 	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
 };
 
 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
@@ -112,10 +112,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
 	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
 	.tmu_inten = EXYNOS_TMU_REG_INTEN,
-	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
-	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
-	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
-	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
 	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
@@ -123,6 +119,10 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
+	.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 	.emul_con = EXYNOS_EMUL_CON,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -217,10 +217,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
 	.threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
 	.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
-	.inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
-	.inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
-	.inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
-	.inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
 	.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
@@ -228,6 +224,10 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
+	.intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
+	.intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
+	.intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
+	.intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
 	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index a1ea19d..d9495a4 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -69,9 +69,10 @@
 #define EXYNOS_TMU_RISE_INT_MASK	0x111
 #define EXYNOS_TMU_RISE_INT_SHIFT	0
 #define EXYNOS_TMU_FALL_INT_MASK	0x111
-#define EXYNOS_TMU_FALL_INT_SHIFT	12
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
+#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
+#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
@@ -119,7 +120,6 @@
 #define EXYNOS5440_TMU_RISE_INT_MASK		0xf
 #define EXYNOS5440_TMU_RISE_INT_SHIFT		0
 #define EXYNOS5440_TMU_FALL_INT_MASK		0xf
-#define EXYNOS5440_TMU_FALL_INT_SHIFT		4
 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT	0
 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT	1
 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT	2
-- 
1.7.10.4

[PATCH 2/4 v9] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Chatradhi]

On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.

To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the "reg" property of the node.

As per Amit's suggestion, this patch changes the base_common
to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
---
Changes since v8:
 None
 .../devicetree/bindings/thermal/exynos-thermal.txt       |    4 ++--
 drivers/thermal/samsung/exynos_tmu.c                     |   14 +++++++-------
 drivers/thermal/samsung/exynos_tmu.h                     |    4 ++--
 drivers/thermal/samsung/exynos_tmu_data.c                |    2 +-
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 284f530..116cca0 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -11,8 +11,8 @@
 - reg : Address range of the thermal registers. For soc's which has multiple
 	instances of TMU and some registers are shared across all TMU's like
 	interrupt related then 2 set of register has to supplied. First set
-	belongs	to each instance of TMU and second set belongs to common TMU
-	registers.
+	belongs	to each instance of TMU and second set belongs to second set
+	of common TMU registers.
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index c493245..bbd0fc3 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -41,7 +41,7 @@
  * @id: identifier of the one instance of the TMU controller.
  * @pdata: pointer to the tmu platform/configuration data
  * @base: base address of the single instance of the TMU controller.
- * @base_common: base address of the common registers of the TMU controller.
+ * @base_second: base address of the common registers of the TMU controller.
  * @irq: irq number of the TMU controller.
  * @soc: id of the SOC type.
  * @irq_work: pointer to the irq work structure.
@@ -56,7 +56,7 @@ struct exynos_tmu_data {
 	int id;
 	struct exynos_tmu_platform_data *pdata;
 	void __iomem *base;
-	void __iomem *base_common;
+	void __iomem *base_second;
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -297,7 +297,7 @@ skip_calib_data:
 	}
 	/*Clear the PMIN in the common TMU register*/
 	if (reg->tmu_pmin && !data->id)
-		writel(0, data->base_common + reg->tmu_pmin);
+		writel(0, data->base_second + reg->tmu_pmin);
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
@@ -454,7 +454,7 @@ static void exynos_tmu_work(struct work_struct *work)
 
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
-		val_type = readl(data->base_common + reg->tmu_irqstatus);
+		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
@@ -579,7 +579,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 	 * Check if the TMU shares some registers and then try to map the
 	 * memory of common registers.
 	 */
-	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
+	if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
 		return 0;
 
 	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
@@ -587,9 +587,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	data->base_common = devm_ioremap(&pdev->dev, res.start,
+	data->base_second = devm_ioremap(&pdev->dev, res.start,
 					resource_size(&res));
-	if (!data->base_common) {
+	if (!data->base_second) {
 		dev_err(&pdev->dev, "Failed to ioremap memory\n");
 		return -ENOMEM;
 	}
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 980859a..0d6b32f 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -60,7 +60,7 @@ enum soc_type {
  *			state(active/idle) can be checked.
  * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
  *			sample time.
- * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
+ * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
  *			sensors shares some common registers.
  * TMU_SUPPORT - macro to compare the above features with the supplied.
  */
@@ -70,7 +70,7 @@ enum soc_type {
 #define TMU_SUPPORT_FALLING_TRIP		BIT(3)
 #define TMU_SUPPORT_READY_STATUS		BIT(4)
 #define TMU_SUPPORT_EMUL_TIME			BIT(5)
-#define TMU_SUPPORT_SHARED_MEMORY		BIT(6)
+#define TMU_SUPPORT_ADDRESS_MULTIPLE		BIT(6)
 
 #define TMU_SUPPORTS(a, b)	(a->features & TMU_SUPPORT_ ## b)
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 7cdb04e..1d27069 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -255,7 +255,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.type = SOC_ARCH_EXYNOS5440, \
 	.registers = &exynos5440_tmu_registers, \
 	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
-			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
+			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 
 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 	.tmu_data = {
-- 
1.7.10.4

[PATCH 3/4 v9] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Chatradhi]

Exynos5420 has 5 TMU channels, the TRIMINFO register is
misplaced for TMU channels 2, 3 and 4
TRIMINFO at 0x1006c000 contains data for TMU channel 3
TRIMINFO at 0x100a0000 contains data for TMU channel 4
TRIMINFO at 0x10068000 contains data for TMU channel 2

This patch
1 Adds the neccessary register changes and arch information
   to support Exynos5420 SoCs.
2. Handles the gate clock for misplaced TRIMINFO register
3. Updates the Documentation at
   Documentation/devicetree/bindings/thermal/exynos-thermal.txt

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
---
Changes since v8:
1. rewrote the Documentation for device tree bindings
2. Merged the https://lkml.org/lkml/2013/11/7/262 (as this is a fix)
3. introduces "samsung,exynos5420-tmu-triminfo" and 
   "samsung,exynos5420-tmu-triminfo-clk" to handle the TMU channels on
   Exynos5420 more appropriately

 .../devicetree/bindings/thermal/exynos-thermal.txt |   45 +++++++++
 drivers/thermal/samsung/exynos_tmu.c               |   58 ++++++++++-
 drivers/thermal/samsung/exynos_tmu.h               |    2 +
 drivers/thermal/samsung/exynos_tmu_data.c          |  106 ++++++++++++++++++++
 drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
 5 files changed, 215 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 116cca0..5055b31 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -6,6 +6,11 @@
 	       "samsung,exynos4412-tmu"
 	       "samsung,exynos4210-tmu"
 	       "samsung,exynos5250-tmu"
+	       "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
+	       "samsung,exynos5420-tmu-triminfo" for TMU channel 2 Exynos5420
+			(Must pass triminfo base)
+	       "samsung,exynos5420-tmu-triminfo-clk" for TMU channel 3 and 4
+			Exynos5420 (Must pass triminfo base and triminfo clock)
 	       "samsung,exynos5440-tmu"
 - interrupt-parent : The phandle for the interrupt controller
 - reg : Address range of the thermal registers. For soc's which has multiple
@@ -13,6 +18,18 @@
 	interrupt related then 2 set of register has to supplied. First set
 	belongs	to each instance of TMU and second set belongs to second set
 	of common TMU registers.
+
+  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
+	channels 2, 3 and 4
+	Use "samsung,exynos5420-tmu-triminfo" in cases, there is a misplaced
+	register but no need of another clock to access that base.
+	Use "samsung,exynos5420-tmu-triminfo-clk" in cases where there is a misplaced
+	register and we need another clock to access that base.
+
+	TRIMINFO at 0x1006c000 contains data for TMU channel 3
+	TRIMINFO at 0x100a0000 contains data for TMU channel 4
+	TRIMINFO at 0x10068000 contains data for TMU channel 2
+
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
@@ -43,6 +60,34 @@ Example 2):
 		clock-names = "tmu_apbif";
 	};
 
+Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
+	/* tmu for CPU2 */
+	tmu@10068000 {
+		compatible = "samsung,exynos5420-tmu-triminfo";
+		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+		interrupts = <0 184 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+	/* tmu for CPU3 */
+	tmu@1006c000 {
+		compatible = "samsung,exynos5420-tmu-triminfo-clk";
+		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+		interrupts = <0 185 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+	};
+
+	/* tmu for GPU */
+	tmu@100a0000 {
+		compatible = "samsung,exynos5420-tmu-triminfo-clk";
+		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
+		interrupts = <0 215 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+	};
+
 Note: For multi-instance tmu each instance should have an alias correctly
 numbered in "aliases" node.
 
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index bbd0fc3..826647c 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -47,6 +47,7 @@
  * @irq_work: pointer to the irq work structure.
  * @lock: lock to implement synchronization.
  * @clk: pointer to the clock structure.
+ * @clk_sec: pointer to the clock structure for accessing the base_second.
  * @temp_error1: fused value of the first point trim.
  * @temp_error2: fused value of the second point trim.
  * @regulator: pointer to the TMU regulator structure.
@@ -61,7 +62,7 @@ struct exynos_tmu_data {
 	enum soc_type soc;
 	struct work_struct irq_work;
 	struct mutex lock;
-	struct clk *clk;
+	struct clk *clk, *clk_sec;
 	u8 temp_error1, temp_error2;
 	struct regulator *regulator;
 	struct thermal_sensor_conf *reg_conf;
@@ -152,6 +153,8 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 
 	mutex_lock(&data->lock);
 	clk_enable(data->clk);
+	if (!IS_ERR(data->clk_sec))
+		clk_enable(data->clk_sec);
 
 	if (TMU_SUPPORTS(pdata, READY_STATUS)) {
 		status = readb(data->base + reg->tmu_status);
@@ -186,7 +189,13 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
 		}
 	} else {
-		trim_info = readl(data->base + reg->triminfo_data);
+		/* On exynos5420 the triminfo register is in the shared space */
+		if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO ||
+			data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO_CLK)
+			trim_info = readl(data->base_second +
+							reg->triminfo_data);
+		else
+			trim_info = readl(data->base + reg->triminfo_data);
 	}
 	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
@@ -301,6 +310,8 @@ skip_calib_data:
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
+	if (!IS_ERR(data->clk_sec))
+		clk_disable(data->clk_sec);
 
 	return ret;
 }
@@ -452,12 +463,16 @@ static void exynos_tmu_work(struct work_struct *work)
 	const struct exynos_tmu_registers *reg = pdata->registers;
 	unsigned int val_irq, val_type;
 
+	if (!IS_ERR(data->clk_sec))
+		clk_enable(data->clk_sec);
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
 		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
+	if (!IS_ERR(data->clk_sec))
+		clk_disable(data->clk_sec);
 
 	exynos_report_trigger(data->reg_conf);
 	mutex_lock(&data->lock);
@@ -498,6 +513,18 @@ static const struct of_device_id exynos_tmu_match[] = {
 		.data = (void *)EXYNOS5250_TMU_DRV_DATA,
 	},
 	{
+		.compatible = "samsung,exynos5420-tmu",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
+		.compatible = "samsung,exynos5420-tmu-triminfo",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
+		.compatible = "samsung,exynos5420-tmu-triminfo-clk",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
 		.compatible = "samsung,exynos5440-tmu",
 		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
 	},
@@ -628,13 +655,31 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 		return  PTR_ERR(data->clk);
 	}
 
+	data->clk_sec = devm_clk_get(&pdev->dev, "tmu_apbif_triminfo");
+	if (IS_ERR(data->clk_sec)) {
+		if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO_CLK) {
+			dev_err(&pdev->dev, "Failed to get triminfo clock\n");
+			return PTR_ERR(data->clk_sec);
+		}
+	} else {
+		ret = clk_prepare(data->clk_sec);
+		if (ret) {
+			dev_err(&pdev->dev, "Failed to get clock\n");
+			return ret;
+		}
+	}
+
 	ret = clk_prepare(data->clk);
-	if (ret)
-		return ret;
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to get clock\n");
+		goto err_clk_sec;
+	}
 
 	if (pdata->type == SOC_ARCH_EXYNOS4210 ||
 	    pdata->type == SOC_ARCH_EXYNOS4412 ||
 	    pdata->type == SOC_ARCH_EXYNOS5250 ||
+	    pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
+	    pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO_CLK ||
 	    pdata->type == SOC_ARCH_EXYNOS5440)
 		data->soc = pdata->type;
 	else {
@@ -703,6 +748,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 	return 0;
 err_clk:
 	clk_unprepare(data->clk);
+err_clk_sec:
+	if (!IS_ERR(data->clk_sec))
+		clk_unprepare(data->clk_sec);
 	return ret;
 }
 
@@ -715,6 +763,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
 	exynos_unregister_thermal(data->reg_conf);
 
 	clk_unprepare(data->clk);
+	if (!IS_ERR(data->clk_sec))
+		clk_unprepare(data->clk_sec);
 
 	if (!IS_ERR(data->regulator))
 		regulator_disable(data->regulator);
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 0d6b32f..f2eb3ac 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -43,6 +43,8 @@ enum soc_type {
 	SOC_ARCH_EXYNOS4210 = 1,
 	SOC_ARCH_EXYNOS4412,
 	SOC_ARCH_EXYNOS5250,
+	SOC_ARCH_EXYNOS5420_TRIMINFO,
+	SOC_ARCH_EXYNOS5420_TRIMINFO_CLK,
 	SOC_ARCH_EXYNOS5440,
 };
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 1d27069..ff79c9a 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -194,6 +194,112 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+static const struct exynos_tmu_registers exynos5420_tmu_registers = {
+	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+	.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+	.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+	.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+	.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+	.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+	.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+	.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+	.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+	.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+	.tmu_status = EXYNOS_TMU_REG_STATUS,
+	.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
+	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
+	.tmu_inten = EXYNOS_TMU_REG_INTEN,
+	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+	/* INTEN_RISE3 Not availble in exynos5420 */
+	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
+	.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+	.emul_con = EXYNOS_EMUL_CON,
+	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+	.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define __EXYNOS5420_TMU_DATA	\
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.registers = &exynos5420_tmu_registers, \
+
+#define EXYNOS5420_TMU_DATA \
+	__EXYNOS5420_TMU_DATA \
+	.type = SOC_ARCH_EXYNOS5250, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME)
+
+#define EXYNOS5420_TMU_DATA_SHARED \
+	__EXYNOS5420_TMU_DATA \
+	.type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
+
+#define EXYNOS5420_TMU_DATA_SHARED_CLK \
+	__EXYNOS5420_TMU_DATA \
+	.type = SOC_ARCH_EXYNOS5420_TRIMINFO_CLK, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
+
+struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
+	.tmu_data = {
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED_CLK },
+		{ EXYNOS5420_TMU_DATA_SHARED_CLK },
+	},
+	.tmu_count = 5,
+};
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index d9495a4..41f06dc 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -72,6 +72,7 @@
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
 #define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
+#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT	16
 #define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
@@ -156,6 +157,13 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
 #define EXYNOS5250_TMU_DRV_DATA (NULL)
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
+#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
+#else
+#define EXYNOS5420_TMU_DRV_DATA (NULL)
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
 #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
-- 
1.7.10.4

Re: [PATCH 3/4 v9] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Ch]

Hello All,

On 12 November 2013 12:07, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> Exynos5420 has 5 TMU channels, the TRIMINFO register is
> misplaced for TMU channels 2, 3 and 4
> TRIMINFO at 0x1006c000 contains data for TMU channel 3
> TRIMINFO at 0x100a0000 contains data for TMU channel 4
> TRIMINFO at 0x10068000 contains data for TMU channel 2
>
> This patch
> 1 Adds the neccessary register changes and arch information
>    to support Exynos5420 SoCs.
> 2. Handles the gate clock for misplaced TRIMINFO register
> 3. Updates the Documentation at
>    Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> ---
> Changes since v8:
> 1. rewrote the Documentation for device tree bindings
> 2. Merged the https://lkml.org/lkml/2013/11/7/262 (as this is a fix)
> 3. introduces "samsung,exynos5420-tmu-triminfo" and
>    "samsung,exynos5420-tmu-triminfo-clk" to handle the TMU channels on
>    Exynos5420 more appropriately
>
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   45 +++++++++
>  drivers/thermal/samsung/exynos_tmu.c               |   58 ++++++++++-
>  drivers/thermal/samsung/exynos_tmu.h               |    2 +
>  drivers/thermal/samsung/exynos_tmu_data.c          |  106 ++++++++++++++++++++
>  drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
>  5 files changed, 215 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 116cca0..5055b31 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -6,6 +6,11 @@
>                "samsung,exynos4412-tmu"
>                "samsung,exynos4210-tmu"
>                "samsung,exynos5250-tmu"
> +              "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
> +              "samsung,exynos5420-tmu-triminfo" for TMU channel 2 Exynos5420
> +                       (Must pass triminfo base)
> +              "samsung,exynos5420-tmu-triminfo-clk" for TMU channel 3 and 4
> +                       Exynos5420 (Must pass triminfo base and triminfo clock)
>                "samsung,exynos5440-tmu"
>  - interrupt-parent : The phandle for the interrupt controller
>  - reg : Address range of the thermal registers. For soc's which has multiple
> @@ -13,6 +18,18 @@
>         interrupt related then 2 set of register has to supplied. First set
>         belongs to each instance of TMU and second set belongs to second set
>         of common TMU registers.
> +
> +  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
> +       channels 2, 3 and 4
> +       Use "samsung,exynos5420-tmu-triminfo" in cases, there is a misplaced
> +       register but no need of another clock to access that base.
> +       Use "samsung,exynos5420-tmu-triminfo-clk" in cases where there is a misplaced
> +       register and we need another clock to access that base.
> +
> +       TRIMINFO at 0x1006c000 contains data for TMU channel 3
> +       TRIMINFO at 0x100a0000 contains data for TMU channel 4
> +       TRIMINFO at 0x10068000 contains data for TMU channel 2
> +
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> @@ -43,6 +60,34 @@ Example 2):
>                 clock-names = "tmu_apbif";
>         };
>
> +Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
> +       /* tmu for CPU2 */
> +       tmu@10068000 {
> +               compatible = "samsung,exynos5420-tmu-triminfo";
> +               reg = <0x10068000 0x100>, <0x1006c000 0x4>;
> +               interrupts = <0 184 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif";
> +       };
> +
> +       /* tmu for CPU3 */
> +       tmu@1006c000 {
> +               compatible = "samsung,exynos5420-tmu-triminfo-clk";
> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
> +               interrupts = <0 185 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif", "tmu_triminfo_apbif";
> +       };
> +
> +       /* tmu for GPU */
> +       tmu@100a0000 {
> +               compatible = "samsung,exynos5420-tmu-triminfo-clk";
> +               reg = <0x100a0000 0x100>, <0x10068000 0x4>;
> +               interrupts = <0 215 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif", "tmu_triminfo_apbif";
> +       };
> +
>  Note: For multi-instance tmu each instance should have an alias correctly
>  numbered in "aliases" node.
>
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index bbd0fc3..826647c 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -47,6 +47,7 @@
>   * @irq_work: pointer to the irq work structure.
>   * @lock: lock to implement synchronization.
>   * @clk: pointer to the clock structure.
> + * @clk_sec: pointer to the clock structure for accessing the base_second.
>   * @temp_error1: fused value of the first point trim.
>   * @temp_error2: fused value of the second point trim.
>   * @regulator: pointer to the TMU regulator structure.
> @@ -61,7 +62,7 @@ struct exynos_tmu_data {
>         enum soc_type soc;
>         struct work_struct irq_work;
>         struct mutex lock;
> -       struct clk *clk;
> +       struct clk *clk, *clk_sec;
>         u8 temp_error1, temp_error2;
>         struct regulator *regulator;
>         struct thermal_sensor_conf *reg_conf;
> @@ -152,6 +153,8 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>
>         mutex_lock(&data->lock);
>         clk_enable(data->clk);
> +       if (!IS_ERR(data->clk_sec))
> +               clk_enable(data->clk_sec);
>
>         if (TMU_SUPPORTS(pdata, READY_STATUS)) {
>                 status = readb(data->base + reg->tmu_status);
> @@ -186,7 +189,13 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>                 }
>         } else {
> -               trim_info = readl(data->base + reg->triminfo_data);
> +               /* On exynos5420 the triminfo register is in the shared space */
> +               if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO ||
> +                       data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO_CLK)
> +                       trim_info = readl(data->base_second +
> +                                                       reg->triminfo_data);
> +               else
> +                       trim_info = readl(data->base + reg->triminfo_data);
>         }
>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
> @@ -301,6 +310,8 @@ skip_calib_data:
>  out:
>         clk_disable(data->clk);
>         mutex_unlock(&data->lock);
> +       if (!IS_ERR(data->clk_sec))
> +               clk_disable(data->clk_sec);
>
>         return ret;
>  }
> @@ -452,12 +463,16 @@ static void exynos_tmu_work(struct work_struct *work)
>         const struct exynos_tmu_registers *reg = pdata->registers;
>         unsigned int val_irq, val_type;
>
> +       if (!IS_ERR(data->clk_sec))
> +               clk_enable(data->clk_sec);
>         /* Find which sensor generated this interrupt */
>         if (reg->tmu_irqstatus) {
>                 val_type = readl(data->base_second + reg->tmu_irqstatus);
>                 if (!((val_type >> data->id) & 0x1))
>                         goto out;
>         }
> +       if (!IS_ERR(data->clk_sec))
> +               clk_disable(data->clk_sec);
>
>         exynos_report_trigger(data->reg_conf);
>         mutex_lock(&data->lock);
> @@ -498,6 +513,18 @@ static const struct of_device_id exynos_tmu_match[] = {
>                 .data = (void *)EXYNOS5250_TMU_DRV_DATA,
>         },
>         {
> +               .compatible = "samsung,exynos5420-tmu",
> +               .data = (void *)EXYNOS5420_TMU_DRV_DATA,
> +       },
> +       {
> +               .compatible = "samsung,exynos5420-tmu-triminfo",
> +               .data = (void *)EXYNOS5420_TMU_DRV_DATA,
> +       },
> +       {
> +               .compatible = "samsung,exynos5420-tmu-triminfo-clk",
> +               .data = (void *)EXYNOS5420_TMU_DRV_DATA,
> +       },
> +       {
>                 .compatible = "samsung,exynos5440-tmu",
>                 .data = (void *)EXYNOS5440_TMU_DRV_DATA,
>         },
> @@ -628,13 +655,31 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>                 return  PTR_ERR(data->clk);
>         }
>
> +       data->clk_sec = devm_clk_get(&pdev->dev, "tmu_apbif_triminfo");
> +       if (IS_ERR(data->clk_sec)) {
> +               if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO_CLK) {
> +                       dev_err(&pdev->dev, "Failed to get triminfo clock\n");
> +                       return PTR_ERR(data->clk_sec);
> +               }
> +       } else {
> +               ret = clk_prepare(data->clk_sec);
> +               if (ret) {
> +                       dev_err(&pdev->dev, "Failed to get clock\n");
> +                       return ret;
> +               }
> +       }
> +
>         ret = clk_prepare(data->clk);
> -       if (ret)
> -               return ret;
> +       if (ret) {
> +               dev_err(&pdev->dev, "Failed to get clock\n");
> +               goto err_clk_sec;
> +       }
>
>         if (pdata->type == SOC_ARCH_EXYNOS4210 ||
>             pdata->type == SOC_ARCH_EXYNOS4412 ||
>             pdata->type == SOC_ARCH_EXYNOS5250 ||
> +           pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
> +           pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO_CLK ||
>             pdata->type == SOC_ARCH_EXYNOS5440)
>                 data->soc = pdata->type;
>         else {
> @@ -703,6 +748,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>         return 0;
>  err_clk:
>         clk_unprepare(data->clk);
> +err_clk_sec:
> +       if (!IS_ERR(data->clk_sec))
> +               clk_unprepare(data->clk_sec);
>         return ret;
>  }
>
> @@ -715,6 +763,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>         exynos_unregister_thermal(data->reg_conf);
>
>         clk_unprepare(data->clk);
> +       if (!IS_ERR(data->clk_sec))
> +               clk_unprepare(data->clk_sec);
>
>         if (!IS_ERR(data->regulator))
>                 regulator_disable(data->regulator);
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 0d6b32f..f2eb3ac 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -43,6 +43,8 @@ enum soc_type {
>         SOC_ARCH_EXYNOS4210 = 1,
>         SOC_ARCH_EXYNOS4412,
>         SOC_ARCH_EXYNOS5250,
> +       SOC_ARCH_EXYNOS5420_TRIMINFO,
> +       SOC_ARCH_EXYNOS5420_TRIMINFO_CLK,
>         SOC_ARCH_EXYNOS5440,
>  };
>
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 1d27069..ff79c9a 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -194,6 +194,112 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
>  };
>  #endif
>
> +#if defined(CONFIG_SOC_EXYNOS5420)
> +static const struct exynos_tmu_registers exynos5420_tmu_registers = {
> +       .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
> +       .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
> +       .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
> +       .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
> +       .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
> +       .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
> +       .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
> +       .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
> +       .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
> +       .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
> +       .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
> +       .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
> +       .tmu_status = EXYNOS_TMU_REG_STATUS,
> +       .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
> +       .threshold_th0 = EXYNOS_THD_TEMP_RISE,
> +       .threshold_th1 = EXYNOS_THD_TEMP_FALL,
> +       .tmu_inten = EXYNOS_TMU_REG_INTEN,
> +       .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
> +       .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
> +       .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
> +       /* INTEN_RISE3 Not availble in exynos5420 */
> +       .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
> +       .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
> +       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
> +       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +       .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
> +       .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> +       .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> +       .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
> +       .emul_con = EXYNOS_EMUL_CON,
> +       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> +       .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> +       .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
> +};
> +
> +#define __EXYNOS5420_TMU_DATA  \
> +       .threshold_falling = 10, \
> +       .trigger_levels[0] = 85, \
> +       .trigger_levels[1] = 103, \
> +       .trigger_levels[2] = 110, \
> +       .trigger_levels[3] = 120, \
> +       .trigger_enable[0] = true, \
> +       .trigger_enable[1] = true, \
> +       .trigger_enable[2] = true, \
> +       .trigger_enable[3] = false, \
> +       .trigger_type[0] = THROTTLE_ACTIVE, \
> +       .trigger_type[1] = THROTTLE_ACTIVE, \
> +       .trigger_type[2] = SW_TRIP, \
> +       .trigger_type[3] = HW_TRIP, \
> +       .max_trigger_level = 4, \
> +       .gain = 8, \
> +       .reference_voltage = 16, \
> +       .noise_cancel_mode = 4, \
> +       .cal_type = TYPE_ONE_POINT_TRIMMING, \
> +       .efuse_value = 55, \
> +       .min_efuse_value = 40, \
> +       .max_efuse_value = 100, \
> +       .first_point_trim = 25, \
> +       .second_point_trim = 85, \
> +       .default_temp_offset = 50, \
> +       .freq_tab[0] = { \
> +               .freq_clip_max = 800 * 1000, \
> +               .temp_level = 85, \
> +       }, \
> +       .freq_tab[1] = { \
> +               .freq_clip_max = 200 * 1000, \
> +               .temp_level = 103, \
> +       }, \
> +       .freq_tab_count = 2, \
> +       .registers = &exynos5420_tmu_registers, \
> +
> +#define EXYNOS5420_TMU_DATA \
> +       __EXYNOS5420_TMU_DATA \
> +       .type = SOC_ARCH_EXYNOS5250, \
> +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +                       TMU_SUPPORT_EMUL_TIME)
> +
> +#define EXYNOS5420_TMU_DATA_SHARED \
> +       __EXYNOS5420_TMU_DATA \
> +       .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
> +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +                       TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
> +
> +#define EXYNOS5420_TMU_DATA_SHARED_CLK \
> +       __EXYNOS5420_TMU_DATA \
> +       .type = SOC_ARCH_EXYNOS5420_TRIMINFO_CLK, \
> +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +                       TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
> +
> +struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
> +       .tmu_data = {
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA_SHARED },
> +               { EXYNOS5420_TMU_DATA_SHARED_CLK },
> +               { EXYNOS5420_TMU_DATA_SHARED_CLK },
> +       },
> +       .tmu_count = 5,
> +};
> +#endif
> +
>  #if defined(CONFIG_SOC_EXYNOS5440)
>  static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> index d9495a4..41f06dc 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> @@ -72,6 +72,7 @@
>  #define EXYNOS_TMU_CLEAR_RISE_INT      0x111
>  #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 12)
>  #define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT        12
> +#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT    16
>  #define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT    4
>  #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
>  #define EXYNOS_TMU_TRIP_MODE_MASK      0x7
> @@ -156,6 +157,13 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
>  #define EXYNOS5250_TMU_DRV_DATA (NULL)
>  #endif
>
> +#if defined(CONFIG_SOC_EXYNOS5420)
> +extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
> +#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
> +#else
> +#define EXYNOS5420_TMU_DRV_DATA (NULL)
> +#endif
> +
>  #if defined(CONFIG_SOC_EXYNOS5440)
>  extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
>  #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
> --
> 1.7.10.4
Any comments on this patch
>



-- 
Shine bright,
(: Nav :)

Re: [PATCH 2/4 v9] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Ch]

Hello All,

On 12 November 2013 12:06, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> On Exynos5440 and Exynos5420 there are registers common
> across the TMU channels.
>
> To support that, we introduced a ADDRESS_MULTIPLE flag in the
> driver and the 2nd set of register base and size are provided
> in the "reg" property of the node.
>
> As per Amit's suggestion, this patch changes the base_common
> to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> Changes since v8:
>  None
>  .../devicetree/bindings/thermal/exynos-thermal.txt       |    4 ++--
>  drivers/thermal/samsung/exynos_tmu.c                     |   14 +++++++-------
>  drivers/thermal/samsung/exynos_tmu.h                     |    4 ++--
>  drivers/thermal/samsung/exynos_tmu_data.c                |    2 +-
>  4 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 284f530..116cca0 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -11,8 +11,8 @@
>  - reg : Address range of the thermal registers. For soc's which has multiple
>         instances of TMU and some registers are shared across all TMU's like
>         interrupt related then 2 set of register has to supplied. First set
> -       belongs to each instance of TMU and second set belongs to common TMU
> -       registers.
> +       belongs to each instance of TMU and second set belongs to second set
> +       of common TMU registers.
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index c493245..bbd0fc3 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -41,7 +41,7 @@
>   * @id: identifier of the one instance of the TMU controller.
>   * @pdata: pointer to the tmu platform/configuration data
>   * @base: base address of the single instance of the TMU controller.
> - * @base_common: base address of the common registers of the TMU controller.
> + * @base_second: base address of the common registers of the TMU controller.
>   * @irq: irq number of the TMU controller.
>   * @soc: id of the SOC type.
>   * @irq_work: pointer to the irq work structure.
> @@ -56,7 +56,7 @@ struct exynos_tmu_data {
>         int id;
>         struct exynos_tmu_platform_data *pdata;
>         void __iomem *base;
> -       void __iomem *base_common;
> +       void __iomem *base_second;
>         int irq;
>         enum soc_type soc;
>         struct work_struct irq_work;
> @@ -297,7 +297,7 @@ skip_calib_data:
>         }
>         /*Clear the PMIN in the common TMU register*/
>         if (reg->tmu_pmin && !data->id)
> -               writel(0, data->base_common + reg->tmu_pmin);
> +               writel(0, data->base_second + reg->tmu_pmin);
>  out:
>         clk_disable(data->clk);
>         mutex_unlock(&data->lock);
> @@ -454,7 +454,7 @@ static void exynos_tmu_work(struct work_struct *work)
>
>         /* Find which sensor generated this interrupt */
>         if (reg->tmu_irqstatus) {
> -               val_type = readl(data->base_common + reg->tmu_irqstatus);
> +               val_type = readl(data->base_second + reg->tmu_irqstatus);
>                 if (!((val_type >> data->id) & 0x1))
>                         goto out;
>         }
> @@ -579,7 +579,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>          * Check if the TMU shares some registers and then try to map the
>          * memory of common registers.
>          */
> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
> +       if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
>                 return 0;
>
>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
> @@ -587,9 +587,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>                 return -ENODEV;
>         }
>
> -       data->base_common = devm_ioremap(&pdev->dev, res.start,
> +       data->base_second = devm_ioremap(&pdev->dev, res.start,
>                                         resource_size(&res));
> -       if (!data->base_common) {
> +       if (!data->base_second) {
>                 dev_err(&pdev->dev, "Failed to ioremap memory\n");
>                 return -ENOMEM;
>         }
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 980859a..0d6b32f 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -60,7 +60,7 @@ enum soc_type {
>   *                     state(active/idle) can be checked.
>   * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
>   *                     sample time.
> - * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
> + * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
>   *                     sensors shares some common registers.
>   * TMU_SUPPORT - macro to compare the above features with the supplied.
>   */
> @@ -70,7 +70,7 @@ enum soc_type {
>  #define TMU_SUPPORT_FALLING_TRIP               BIT(3)
>  #define TMU_SUPPORT_READY_STATUS               BIT(4)
>  #define TMU_SUPPORT_EMUL_TIME                  BIT(5)
> -#define TMU_SUPPORT_SHARED_MEMORY              BIT(6)
> +#define TMU_SUPPORT_ADDRESS_MULTIPLE           BIT(6)
>
>  #define TMU_SUPPORTS(a, b)     (a->features & TMU_SUPPORT_ ## b)
>
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 7cdb04e..1d27069 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -255,7 +255,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .type = SOC_ARCH_EXYNOS5440, \
>         .registers = &exynos5440_tmu_registers, \
>         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
> -                       TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
> +                       TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
>
>  struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
>         .tmu_data = {
> --
> 1.7.10.4
Any comments on this patch

>



-- 
Shine bright,
(: Nav :)

Re: [PATCH 1/4 v9] thermal: samsung: replace inten_ bit fields with intclr_

[Naveen Krishna Ch]

Hello All,

On 12 November 2013 12:06, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
> with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
> Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only used
> to configure intclr related registers.
>
> Description of H/W:
> The offset for the bits in the CLEAR register are not consistent across TMU
> modules in Exynso5250, 5420 and 5440.
>
> On Exynos5250, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT registers and at an offset of
> 12 in INTCLEAR register.
>
> On Exynos5420, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT and INTCLEAR registers.
>
> On Exynos5440,
> the FALL_IRQEN bits are at an offset of 4
> and the RISE_IRQEN bits are at an offset of 0
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> ---
> Changes since v8:
> 1. Modified the patch description,
> 2. replaces the inten_rise/fall_shift/mask with intclr_rise/fall_shift/mask
>
>  drivers/thermal/samsung/exynos_tmu.c      |    6 +++---
>  drivers/thermal/samsung/exynos_tmu.h      |   16 ++++++++--------
>  drivers/thermal/samsung/exynos_tmu_data.c |   18 +++++++++---------
>  drivers/thermal/samsung/exynos_tmu_data.h |    4 ++--
>  4 files changed, 22 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index 32f38b9..c493245 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -237,7 +237,7 @@ skip_calib_data:
>                         writeb(pdata->trigger_levels[i], data->base +
>                         reg->threshold_th0 + i * sizeof(reg->threshold_th0));
>
> -               writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
> +               writel(reg->intclr_rise_mask, data->base + reg->tmu_intclear);
>         } else {
>                 /* Write temperature code for rising and falling threshold */
>                 for (i = 0;
> @@ -264,8 +264,8 @@ skip_calib_data:
>                 writel(falling_threshold,
>                                 data->base + reg->threshold_th1);
>
> -               writel((reg->inten_rise_mask << reg->inten_rise_shift) |
> -                       (reg->inten_fall_mask << reg->inten_fall_shift),
> +               writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |
> +                       (reg->intclr_fall_mask << reg->intclr_fall_shift),
>                                 data->base + reg->tmu_intclear);
>
>                 /* if last threshold limit is also present */
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 3fb6554..980859a 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -122,10 +122,6 @@ enum soc_type {
>   * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
>   * @tmu_inten: register containing the different threshold interrupt
>         enable bits.
> - * @inten_rise_shift: shift bits of all rising interrupt bits.
> - * @inten_rise_mask: mask bits of all rising interrupt bits.
> - * @inten_fall_shift: shift bits of all rising interrupt bits.
> - * @inten_fall_mask: mask bits of all rising interrupt bits.
>   * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
>   * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
>   * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
> @@ -136,6 +132,10 @@ enum soc_type {
>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
>   * @tmu_intstat: Register containing the interrupt status values.
>   * @tmu_intclear: Register for clearing the raised interrupt status.
> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
> + * @intclr_rise_shift: shift bits of all rising interrupt bits.
> + * @intclr_rise_mask: mask bits of all rising interrupt bits.
> + * @intclr_fall_mask: mask bits of all rising interrupt bits.
>   * @emul_con: TMU emulation controller register.
>   * @emul_temp_shift: shift bits of emulation temperature.
>   * @emul_time_shift: shift bits of emulation time.
> @@ -191,10 +191,6 @@ struct exynos_tmu_registers {
>         u32     threshold_th3_l0_shift;
>
>         u32     tmu_inten;
> -       u32     inten_rise_shift;
> -       u32     inten_rise_mask;
> -       u32     inten_fall_shift;
> -       u32     inten_fall_mask;
>         u32     inten_rise0_shift;
>         u32     inten_rise1_shift;
>         u32     inten_rise2_shift;
> @@ -207,6 +203,10 @@ struct exynos_tmu_registers {
>         u32     tmu_intstat;
>
>         u32     tmu_intclear;
> +       u32     intclr_fall_shift;
> +       u32     intclr_rise_shift;
> +       u32     intclr_fall_mask;
> +       u32     intclr_rise_mask;
>
>         u32     emul_con;
>         u32     emul_temp_shift;
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 073c292..7cdb04e 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -40,13 +40,13 @@ static const struct exynos_tmu_registers exynos4210_tmu_registers = {
>         .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
>         .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
>         .tmu_inten = EXYNOS_TMU_REG_INTEN,
> -       .inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
>         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
>         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
>         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
>         .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
>         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +       .intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
>  };
>
>  struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
> @@ -112,10 +112,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
>         .threshold_th0 = EXYNOS_THD_TEMP_RISE,
>         .threshold_th1 = EXYNOS_THD_TEMP_FALL,
>         .tmu_inten = EXYNOS_TMU_REG_INTEN,
> -       .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> -       .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> -       .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
> -       .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
>         .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
>         .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
>         .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
> @@ -123,6 +119,10 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
>         .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>         .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>         .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +       .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
> +       .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> +       .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> +       .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
>         .emul_con = EXYNOS_EMUL_CON,
>         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>         .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> @@ -217,10 +217,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
>         .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
>         .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
> -       .inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
> -       .inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
> -       .inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
> -       .inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
>         .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
>         .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
>         .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
> @@ -228,6 +224,10 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
>         .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
>         .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
> +       .intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
> +       .intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
> +       .intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
> +       .intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
>         .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
>         .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
>         .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> index a1ea19d..d9495a4 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> @@ -69,9 +69,10 @@
>  #define EXYNOS_TMU_RISE_INT_MASK       0x111
>  #define EXYNOS_TMU_RISE_INT_SHIFT      0
>  #define EXYNOS_TMU_FALL_INT_MASK       0x111
> -#define EXYNOS_TMU_FALL_INT_SHIFT      12
>  #define EXYNOS_TMU_CLEAR_RISE_INT      0x111
>  #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 12)
> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT        12
> +#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT    4
>  #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
>  #define EXYNOS_TMU_TRIP_MODE_MASK      0x7
>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
> @@ -119,7 +120,6 @@
>  #define EXYNOS5440_TMU_RISE_INT_MASK           0xf
>  #define EXYNOS5440_TMU_RISE_INT_SHIFT          0
>  #define EXYNOS5440_TMU_FALL_INT_MASK           0xf
> -#define EXYNOS5440_TMU_FALL_INT_SHIFT          4
>  #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT       0
>  #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT       1
>  #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT       2
> --
> 1.7.10.4
Any comments on this patch
>



-- 
Shine bright,
(: Nav :)

Re: [PATCH 0/3] thermal: samsung: Clean up and add support for Exynos5420

[Naveen Krishna Ch]

Hello All,

On 12 November 2013 12:05, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> This patchset does a little clean up of the existing code
> 1.  [v9] thermal: samsung: replace inten_ bit fields with intclr_
> 2.  [v9] thermal: samsung: change base_common to more meaningful base_second
>
> adds support for Exynos5420 in the driver and
> 3.  [v9] thermal: samsung: Add TMU support for Exynos5420 SoCs
> also adds the device tree nodes for the same to exynos5420.dtsi (linux-samsung.git)
> 4.  [v3] ARM: dts: Exynos5420: Add device nodes for TMU blocks
>
> Naveen Krishna Chatradhi (3):
>   thermal: samsung: replace inten_ bit fields with intclr_
>   thermal: samsung: change base_common to more meaningful base_second
>   thermal: samsung: Add TMU support for Exynos5420 SoCs
>   ARM: dts: Exynos5420: Add device nodes for TMU blocks
>
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   49 +++++++-
>  drivers/thermal/samsung/exynos_tmu.c               |   78 +++++++++---
>  drivers/thermal/samsung/exynos_tmu.h               |   22 ++--
>  drivers/thermal/samsung/exynos_tmu_data.c          |  126 ++++++++++++++++++--
>  drivers/thermal/samsung/exynos_tmu_data.h          |   12 +-
>  5 files changed, 249 insertions(+), 38 deletions(-)
>
> --
> 1.7.10.4
Any comments on this patch set please.
>



-- 
Shine bright,
(: Nav :)

Re: [PATCH 3/4 v9] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Mark Rutland]

On Mon, Nov 18, 2013 at 03:22:57AM +0000, Naveen Krishna Ch wrote:
> Hello All,
> 
> On 12 November 2013 12:07, Naveen Krishna Chatradhi
> <ch.naveen@samsung.com> wrote:
> > Exynos5420 has 5 TMU channels, the TRIMINFO register is
> > misplaced for TMU channels 2, 3 and 4
> > TRIMINFO at 0x1006c000 contains data for TMU channel 3
> > TRIMINFO at 0x100a0000 contains data for TMU channel 4
> > TRIMINFO at 0x10068000 contains data for TMU channel 2
> >
> > This patch
> > 1 Adds the neccessary register changes and arch information
> >    to support Exynos5420 SoCs.
> > 2. Handles the gate clock for misplaced TRIMINFO register
> > 3. Updates the Documentation at
> >    Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> >
> > Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> > Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> > ---
> > Changes since v8:
> > 1. rewrote the Documentation for device tree bindings
> > 2. Merged the https://lkml.org/lkml/2013/11/7/262 (as this is a fix)
> > 3. introduces "samsung,exynos5420-tmu-triminfo" and
> >    "samsung,exynos5420-tmu-triminfo-clk" to handle the TMU channels on
> >    Exynos5420 more appropriately
> >
> >  .../devicetree/bindings/thermal/exynos-thermal.txt |   45 +++++++++
> >  drivers/thermal/samsung/exynos_tmu.c               |   58 ++++++++++-
> >  drivers/thermal/samsung/exynos_tmu.h               |    2 +
> >  drivers/thermal/samsung/exynos_tmu_data.c          |  106 ++++++++++++++++++++
> >  drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
> >  5 files changed, 215 insertions(+), 4 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> > index 116cca0..5055b31 100644
> > --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> > +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> > @@ -6,6 +6,11 @@
> >                "samsung,exynos4412-tmu"
> >                "samsung,exynos4210-tmu"
> >                "samsung,exynos5250-tmu"
> > +              "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
> > +              "samsung,exynos5420-tmu-triminfo" for TMU channel 2 Exynos5420
> > +                       (Must pass triminfo base)
> > +              "samsung,exynos5420-tmu-triminfo-clk" for TMU channel 3 and 4
> > +                       Exynos5420 (Must pass triminfo base and triminfo clock)

While this mentions what the differences the binding expects to, what is
fundamentally different about these blocks?

> >                "samsung,exynos5440-tmu"
> >  - interrupt-parent : The phandle for the interrupt controller
> >  - reg : Address range of the thermal registers. For soc's which has multiple
> > @@ -13,6 +18,18 @@
> >         interrupt related then 2 set of register has to supplied. First set
> >         belongs to each instance of TMU and second set belongs to second set
> >         of common TMU registers.
> > +
> > +  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
> > +       channels 2, 3 and 4
> > +       Use "samsung,exynos5420-tmu-triminfo" in cases, there is a misplaced
> > +       register but no need of another clock to access that base.
> > +       Use "samsung,exynos5420-tmu-triminfo-clk" in cases where there is a misplaced
> > +       register and we need another clock to access that base.

This would have made more sense to have next to the compatible strings.

Instead of this, you could have a boolean property
("samsung,misplaced-triminfo") to describe the misplaced triminfo
register(s), and the presence of an additional clock would imlpy that
it's required for accessing triminfo register(s).

> > +
> > +       TRIMINFO at 0x1006c000 contains data for TMU channel 3
> > +       TRIMINFO at 0x100a0000 contains data for TMU channel 4
> > +       TRIMINFO at 0x10068000 contains data for TMU channel 2
> > +
> >  - interrupts : Should contain interrupt for thermal system
> >  - clocks : The main clock for TMU device
> >  - clock-names : Thermal system clock name
> > @@ -43,6 +60,34 @@ Example 2):
> >                 clock-names = "tmu_apbif";
> >         };

I'd have expected the clock-names to have an addition. The names of the
clock inputs are presumably well known, or you should be able to come up
with some sensible names...

> >
> > +Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
> > +       /* tmu for CPU2 */
> > +       tmu@10068000 {
> > +               compatible = "samsung,exynos5420-tmu-triminfo";
> > +               reg = <0x10068000 0x100>, <0x1006c000 0x4>;
> > +               interrupts = <0 184 0>;
> > +               clocks = <&clock 318>;
> > +               clock-names = "tmu_apbif";
> > +       };
> > +
> > +       /* tmu for CPU3 */
> > +       tmu@1006c000 {
> > +               compatible = "samsung,exynos5420-tmu-triminfo-clk";
> > +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
> > +               interrupts = <0 185 0>;
> > +               clocks = <&clock 318>;
> > +               clock-names = "tmu_apbif", "tmu_triminfo_apbif";

Each clock-names entry should correspond to an entry in clocks. The
"tmu_triminfo_apbif" entry here doesn't correspond to anything. I assume
a copy-paste error?

The "tmu_triminfo_apbif" clock name should be documented in the binding.

> > +       };
> > +
> > +       /* tmu for GPU */
> > +       tmu@100a0000 {
> > +               compatible = "samsung,exynos5420-tmu-triminfo-clk";
> > +               reg = <0x100a0000 0x100>, <0x10068000 0x4>;
> > +               interrupts = <0 215 0>;
> > +               clocks = <&clock 318>;
> > +               clock-names = "tmu_apbif", "tmu_triminfo_apbif";

Similarly here...

Thanks,
Mark.

[PATCH 1/4 v10] thermal: samsung: replace inten_ bit fields with intclr_

[Naveen Krishna Chatradhi]

This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only used
to configure intclr related registers.

Description of H/W:
The offset for the bits in the CLEAR register are not consistent across TMU
modules in Exynso5250, 5420 and 5440.

On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT registers and at an offset of
12 in INTCLEAR register.

On Exynos5420, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT and INTCLEAR registers.

On Exynos5440,
the FALL_IRQEN bits are at an offset of 4
and the RISE_IRQEN bits are at an offset of 0

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
Changes since v9:
Just respinning

Changes since v8:
1. Modified the patch description,
2. replaces the inten_rise/fall_shift/mask with intclr_rise/fall_shift/mask

 drivers/thermal/samsung/exynos_tmu.c      |    6 +++---
 drivers/thermal/samsung/exynos_tmu.h      |   16 ++++++++--------
 drivers/thermal/samsung/exynos_tmu_data.c |   18 +++++++++---------
 drivers/thermal/samsung/exynos_tmu_data.h |    4 ++--
 4 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 32f38b9..c493245 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -237,7 +237,7 @@ skip_calib_data:
 			writeb(pdata->trigger_levels[i], data->base +
 			reg->threshold_th0 + i * sizeof(reg->threshold_th0));
 
-		writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
+		writel(reg->intclr_rise_mask, data->base + reg->tmu_intclear);
 	} else {
 		/* Write temperature code for rising and falling threshold */
 		for (i = 0;
@@ -264,8 +264,8 @@ skip_calib_data:
 		writel(falling_threshold,
 				data->base + reg->threshold_th1);
 
-		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
-			(reg->inten_fall_mask << reg->inten_fall_shift),
+		writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |
+			(reg->intclr_fall_mask << reg->intclr_fall_shift),
 				data->base + reg->tmu_intclear);
 
 		/* if last threshold limit is also present */
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 3fb6554..980859a 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -122,10 +122,6 @@ enum soc_type {
  * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
  * @tmu_inten: register containing the different threshold interrupt
 	enable bits.
- * @inten_rise_shift: shift bits of all rising interrupt bits.
- * @inten_rise_mask: mask bits of all rising interrupt bits.
- * @inten_fall_shift: shift bits of all rising interrupt bits.
- * @inten_fall_mask: mask bits of all rising interrupt bits.
  * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
  * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
  * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
@@ -136,6 +132,10 @@ enum soc_type {
  * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
  * @tmu_intstat: Register containing the interrupt status values.
  * @tmu_intclear: Register for clearing the raised interrupt status.
+ * @intclr_fall_shift: shift bits for interrupt clear fall 0
+ * @intclr_rise_shift: shift bits of all rising interrupt bits.
+ * @intclr_rise_mask: mask bits of all rising interrupt bits.
+ * @intclr_fall_mask: mask bits of all rising interrupt bits.
  * @emul_con: TMU emulation controller register.
  * @emul_temp_shift: shift bits of emulation temperature.
  * @emul_time_shift: shift bits of emulation time.
@@ -191,10 +191,6 @@ struct exynos_tmu_registers {
 	u32	threshold_th3_l0_shift;
 
 	u32	tmu_inten;
-	u32	inten_rise_shift;
-	u32	inten_rise_mask;
-	u32	inten_fall_shift;
-	u32	inten_fall_mask;
 	u32	inten_rise0_shift;
 	u32	inten_rise1_shift;
 	u32	inten_rise2_shift;
@@ -207,6 +203,10 @@ struct exynos_tmu_registers {
 	u32	tmu_intstat;
 
 	u32	tmu_intclear;
+	u32	intclr_fall_shift;
+	u32	intclr_rise_shift;
+	u32	intclr_fall_mask;
+	u32	intclr_rise_mask;
 
 	u32	emul_con;
 	u32	emul_temp_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 073c292..7cdb04e 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -40,13 +40,13 @@ static const struct exynos_tmu_registers exynos4210_tmu_registers = {
 	.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
 	.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
 	.tmu_inten = EXYNOS_TMU_REG_INTEN,
-	.inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
 	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
 };
 
 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
@@ -112,10 +112,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
 	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
 	.tmu_inten = EXYNOS_TMU_REG_INTEN,
-	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
-	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
-	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
-	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
 	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
@@ -123,6 +119,10 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
+	.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 	.emul_con = EXYNOS_EMUL_CON,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -217,10 +217,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
 	.threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
 	.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
-	.inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
-	.inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
-	.inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
-	.inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
 	.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
@@ -228,6 +224,10 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
+	.intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
+	.intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
+	.intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
+	.intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
 	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index a1ea19d..d9495a4 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -69,9 +69,10 @@
 #define EXYNOS_TMU_RISE_INT_MASK	0x111
 #define EXYNOS_TMU_RISE_INT_SHIFT	0
 #define EXYNOS_TMU_FALL_INT_MASK	0x111
-#define EXYNOS_TMU_FALL_INT_SHIFT	12
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
+#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
+#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
@@ -119,7 +120,6 @@
 #define EXYNOS5440_TMU_RISE_INT_MASK		0xf
 #define EXYNOS5440_TMU_RISE_INT_SHIFT		0
 #define EXYNOS5440_TMU_FALL_INT_MASK		0xf
-#define EXYNOS5440_TMU_FALL_INT_SHIFT		4
 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT	0
 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT	1
 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT	2
-- 
1.7.10.4

[PATCH 2/4 v10] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Chatradhi]

On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.

To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the "reg" property of the node.

As per Amit's suggestion, this patch changes the base_common
to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
Changes since v9:
Just respinning

Changes since v8:
 None
 .../devicetree/bindings/thermal/exynos-thermal.txt       |    4 ++--
 drivers/thermal/samsung/exynos_tmu.c                     |   14 +++++++-------
 drivers/thermal/samsung/exynos_tmu.h                     |    4 ++--
 drivers/thermal/samsung/exynos_tmu_data.c                |    2 +-
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 284f530..116cca0 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -11,8 +11,8 @@
 - reg : Address range of the thermal registers. For soc's which has multiple
 	instances of TMU and some registers are shared across all TMU's like
 	interrupt related then 2 set of register has to supplied. First set
-	belongs	to each instance of TMU and second set belongs to common TMU
-	registers.
+	belongs	to each instance of TMU and second set belongs to second set
+	of common TMU registers.
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index c493245..bbd0fc3 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -41,7 +41,7 @@
  * @id: identifier of the one instance of the TMU controller.
  * @pdata: pointer to the tmu platform/configuration data
  * @base: base address of the single instance of the TMU controller.
- * @base_common: base address of the common registers of the TMU controller.
+ * @base_second: base address of the common registers of the TMU controller.
  * @irq: irq number of the TMU controller.
  * @soc: id of the SOC type.
  * @irq_work: pointer to the irq work structure.
@@ -56,7 +56,7 @@ struct exynos_tmu_data {
 	int id;
 	struct exynos_tmu_platform_data *pdata;
 	void __iomem *base;
-	void __iomem *base_common;
+	void __iomem *base_second;
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -297,7 +297,7 @@ skip_calib_data:
 	}
 	/*Clear the PMIN in the common TMU register*/
 	if (reg->tmu_pmin && !data->id)
-		writel(0, data->base_common + reg->tmu_pmin);
+		writel(0, data->base_second + reg->tmu_pmin);
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
@@ -454,7 +454,7 @@ static void exynos_tmu_work(struct work_struct *work)
 
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
-		val_type = readl(data->base_common + reg->tmu_irqstatus);
+		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
@@ -579,7 +579,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 	 * Check if the TMU shares some registers and then try to map the
 	 * memory of common registers.
 	 */
-	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
+	if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
 		return 0;
 
 	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
@@ -587,9 +587,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	data->base_common = devm_ioremap(&pdev->dev, res.start,
+	data->base_second = devm_ioremap(&pdev->dev, res.start,
 					resource_size(&res));
-	if (!data->base_common) {
+	if (!data->base_second) {
 		dev_err(&pdev->dev, "Failed to ioremap memory\n");
 		return -ENOMEM;
 	}
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 980859a..0d6b32f 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -60,7 +60,7 @@ enum soc_type {
  *			state(active/idle) can be checked.
  * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
  *			sample time.
- * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
+ * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
  *			sensors shares some common registers.
  * TMU_SUPPORT - macro to compare the above features with the supplied.
  */
@@ -70,7 +70,7 @@ enum soc_type {
 #define TMU_SUPPORT_FALLING_TRIP		BIT(3)
 #define TMU_SUPPORT_READY_STATUS		BIT(4)
 #define TMU_SUPPORT_EMUL_TIME			BIT(5)
-#define TMU_SUPPORT_SHARED_MEMORY		BIT(6)
+#define TMU_SUPPORT_ADDRESS_MULTIPLE		BIT(6)
 
 #define TMU_SUPPORTS(a, b)	(a->features & TMU_SUPPORT_ ## b)
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 7cdb04e..1d27069 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -255,7 +255,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.type = SOC_ARCH_EXYNOS5440, \
 	.registers = &exynos5440_tmu_registers, \
 	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
-			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
+			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 
 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 	.tmu_data = {
-- 
1.7.10.4

[PATCH 3/4 v10] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Chatradhi]

Exynos5420 has 5 TMU channels, the TRIMINFO register is
misplaced for TMU channels 2, 3 and 4
TRIMINFO at 0x1006c000 contains data for TMU channel 3
TRIMINFO at 0x100a0000 contains data for TMU channel 4
TRIMINFO at 0x10068000 contains data for TMU channel 2

This patch
1 Adds the neccessary register changes and arch information
   to support Exynos5420 SoCs.
2. Handles the gate clock for misplaced TRIMINFO register
3. Updates the Documentation at
   Documentation/devicetree/bindings/thermal/exynos-thermal.txt

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
Changes since v9:
Just respinning

Changes since v8:
1. rewrote the Documentation for device tree bindings
2. Merged the https://lkml.org/lkml/2013/11/7/262 (as this is a fix)
3. introduces "samsung,exynos5420-tmu-triminfo" and 
   "samsung,exynos5420-tmu-triminfo-clk" to handle the TMU channels on
   Exynos5420 more appropriately

 .../devicetree/bindings/thermal/exynos-thermal.txt |   45 +++++++++
 drivers/thermal/samsung/exynos_tmu.c               |   58 ++++++++++-
 drivers/thermal/samsung/exynos_tmu.h               |    2 +
 drivers/thermal/samsung/exynos_tmu_data.c          |  106 ++++++++++++++++++++
 drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
 5 files changed, 215 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 116cca0..5055b31 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -6,6 +6,11 @@
 	       "samsung,exynos4412-tmu"
 	       "samsung,exynos4210-tmu"
 	       "samsung,exynos5250-tmu"
+	       "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
+	       "samsung,exynos5420-tmu-triminfo" for TMU channel 2 Exynos5420
+			(Must pass triminfo base)
+	       "samsung,exynos5420-tmu-triminfo-clk" for TMU channel 3 and 4
+			Exynos5420 (Must pass triminfo base and triminfo clock)
 	       "samsung,exynos5440-tmu"
 - interrupt-parent : The phandle for the interrupt controller
 - reg : Address range of the thermal registers. For soc's which has multiple
@@ -13,6 +18,18 @@
 	interrupt related then 2 set of register has to supplied. First set
 	belongs	to each instance of TMU and second set belongs to second set
 	of common TMU registers.
+
+  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
+	channels 2, 3 and 4
+	Use "samsung,exynos5420-tmu-triminfo" in cases, there is a misplaced
+	register but no need of another clock to access that base.
+	Use "samsung,exynos5420-tmu-triminfo-clk" in cases where there is a misplaced
+	register and we need another clock to access that base.
+
+	TRIMINFO at 0x1006c000 contains data for TMU channel 3
+	TRIMINFO at 0x100a0000 contains data for TMU channel 4
+	TRIMINFO at 0x10068000 contains data for TMU channel 2
+
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
@@ -43,6 +60,34 @@ Example 2):
 		clock-names = "tmu_apbif";
 	};
 
+Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
+	/* tmu for CPU2 */
+	tmu@10068000 {
+		compatible = "samsung,exynos5420-tmu-triminfo";
+		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+		interrupts = <0 184 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif";
+	};
+
+	/* tmu for CPU3 */
+	tmu@1006c000 {
+		compatible = "samsung,exynos5420-tmu-triminfo-clk";
+		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+		interrupts = <0 185 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+	};
+
+	/* tmu for GPU */
+	tmu@100a0000 {
+		compatible = "samsung,exynos5420-tmu-triminfo-clk";
+		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
+		interrupts = <0 215 0>;
+		clocks = <&clock 318>;
+		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+	};
+
 Note: For multi-instance tmu each instance should have an alias correctly
 numbered in "aliases" node.
 
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index bbd0fc3..826647c 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -47,6 +47,7 @@
  * @irq_work: pointer to the irq work structure.
  * @lock: lock to implement synchronization.
  * @clk: pointer to the clock structure.
+ * @clk_sec: pointer to the clock structure for accessing the base_second.
  * @temp_error1: fused value of the first point trim.
  * @temp_error2: fused value of the second point trim.
  * @regulator: pointer to the TMU regulator structure.
@@ -61,7 +62,7 @@ struct exynos_tmu_data {
 	enum soc_type soc;
 	struct work_struct irq_work;
 	struct mutex lock;
-	struct clk *clk;
+	struct clk *clk, *clk_sec;
 	u8 temp_error1, temp_error2;
 	struct regulator *regulator;
 	struct thermal_sensor_conf *reg_conf;
@@ -152,6 +153,8 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 
 	mutex_lock(&data->lock);
 	clk_enable(data->clk);
+	if (!IS_ERR(data->clk_sec))
+		clk_enable(data->clk_sec);
 
 	if (TMU_SUPPORTS(pdata, READY_STATUS)) {
 		status = readb(data->base + reg->tmu_status);
@@ -186,7 +189,13 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
 		}
 	} else {
-		trim_info = readl(data->base + reg->triminfo_data);
+		/* On exynos5420 the triminfo register is in the shared space */
+		if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO ||
+			data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO_CLK)
+			trim_info = readl(data->base_second +
+							reg->triminfo_data);
+		else
+			trim_info = readl(data->base + reg->triminfo_data);
 	}
 	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
@@ -301,6 +310,8 @@ skip_calib_data:
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
+	if (!IS_ERR(data->clk_sec))
+		clk_disable(data->clk_sec);
 
 	return ret;
 }
@@ -452,12 +463,16 @@ static void exynos_tmu_work(struct work_struct *work)
 	const struct exynos_tmu_registers *reg = pdata->registers;
 	unsigned int val_irq, val_type;
 
+	if (!IS_ERR(data->clk_sec))
+		clk_enable(data->clk_sec);
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
 		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
+	if (!IS_ERR(data->clk_sec))
+		clk_disable(data->clk_sec);
 
 	exynos_report_trigger(data->reg_conf);
 	mutex_lock(&data->lock);
@@ -498,6 +513,18 @@ static const struct of_device_id exynos_tmu_match[] = {
 		.data = (void *)EXYNOS5250_TMU_DRV_DATA,
 	},
 	{
+		.compatible = "samsung,exynos5420-tmu",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
+		.compatible = "samsung,exynos5420-tmu-triminfo",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
+		.compatible = "samsung,exynos5420-tmu-triminfo-clk",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
 		.compatible = "samsung,exynos5440-tmu",
 		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
 	},
@@ -628,13 +655,31 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 		return  PTR_ERR(data->clk);
 	}
 
+	data->clk_sec = devm_clk_get(&pdev->dev, "tmu_apbif_triminfo");
+	if (IS_ERR(data->clk_sec)) {
+		if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO_CLK) {
+			dev_err(&pdev->dev, "Failed to get triminfo clock\n");
+			return PTR_ERR(data->clk_sec);
+		}
+	} else {
+		ret = clk_prepare(data->clk_sec);
+		if (ret) {
+			dev_err(&pdev->dev, "Failed to get clock\n");
+			return ret;
+		}
+	}
+
 	ret = clk_prepare(data->clk);
-	if (ret)
-		return ret;
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to get clock\n");
+		goto err_clk_sec;
+	}
 
 	if (pdata->type == SOC_ARCH_EXYNOS4210 ||
 	    pdata->type == SOC_ARCH_EXYNOS4412 ||
 	    pdata->type == SOC_ARCH_EXYNOS5250 ||
+	    pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
+	    pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO_CLK ||
 	    pdata->type == SOC_ARCH_EXYNOS5440)
 		data->soc = pdata->type;
 	else {
@@ -703,6 +748,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 	return 0;
 err_clk:
 	clk_unprepare(data->clk);
+err_clk_sec:
+	if (!IS_ERR(data->clk_sec))
+		clk_unprepare(data->clk_sec);
 	return ret;
 }
 
@@ -715,6 +763,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
 	exynos_unregister_thermal(data->reg_conf);
 
 	clk_unprepare(data->clk);
+	if (!IS_ERR(data->clk_sec))
+		clk_unprepare(data->clk_sec);
 
 	if (!IS_ERR(data->regulator))
 		regulator_disable(data->regulator);
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 0d6b32f..f2eb3ac 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -43,6 +43,8 @@ enum soc_type {
 	SOC_ARCH_EXYNOS4210 = 1,
 	SOC_ARCH_EXYNOS4412,
 	SOC_ARCH_EXYNOS5250,
+	SOC_ARCH_EXYNOS5420_TRIMINFO,
+	SOC_ARCH_EXYNOS5420_TRIMINFO_CLK,
 	SOC_ARCH_EXYNOS5440,
 };
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 1d27069..ff79c9a 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -194,6 +194,112 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+static const struct exynos_tmu_registers exynos5420_tmu_registers = {
+	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+	.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+	.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+	.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+	.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+	.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+	.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+	.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+	.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+	.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+	.tmu_status = EXYNOS_TMU_REG_STATUS,
+	.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
+	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
+	.tmu_inten = EXYNOS_TMU_REG_INTEN,
+	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+	/* INTEN_RISE3 Not availble in exynos5420 */
+	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
+	.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+	.emul_con = EXYNOS_EMUL_CON,
+	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+	.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define __EXYNOS5420_TMU_DATA	\
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.registers = &exynos5420_tmu_registers, \
+
+#define EXYNOS5420_TMU_DATA \
+	__EXYNOS5420_TMU_DATA \
+	.type = SOC_ARCH_EXYNOS5250, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME)
+
+#define EXYNOS5420_TMU_DATA_SHARED \
+	__EXYNOS5420_TMU_DATA \
+	.type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
+
+#define EXYNOS5420_TMU_DATA_SHARED_CLK \
+	__EXYNOS5420_TMU_DATA \
+	.type = SOC_ARCH_EXYNOS5420_TRIMINFO_CLK, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
+
+struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
+	.tmu_data = {
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED_CLK },
+		{ EXYNOS5420_TMU_DATA_SHARED_CLK },
+	},
+	.tmu_count = 5,
+};
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index d9495a4..41f06dc 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -72,6 +72,7 @@
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
 #define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
+#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT	16
 #define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
@@ -156,6 +157,13 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
 #define EXYNOS5250_TMU_DRV_DATA (NULL)
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
+#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
+#else
+#define EXYNOS5420_TMU_DRV_DATA (NULL)
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
 #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
-- 
1.7.10.4

Re: [PATCH 3/4 v10] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Ch]

Hello All,

On 19 November 2013 18:35, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> Exynos5420 has 5 TMU channels, the TRIMINFO register is
> misplaced for TMU channels 2, 3 and 4
> TRIMINFO at 0x1006c000 contains data for TMU channel 3
> TRIMINFO at 0x100a0000 contains data for TMU channel 4
> TRIMINFO at 0x10068000 contains data for TMU channel 2
>
> This patch
> 1 Adds the neccessary register changes and arch information
>    to support Exynos5420 SoCs.
> 2. Handles the gate clock for misplaced TRIMINFO register
> 3. Updates the Documentation at
>    Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
> Changes since v9:
> Just respinning
>
> Changes since v8:
> 1. rewrote the Documentation for device tree bindings
> 2. Merged the https://lkml.org/lkml/2013/11/7/262 (as this is a fix)
> 3. introduces "samsung,exynos5420-tmu-triminfo" and
>    "samsung,exynos5420-tmu-triminfo-clk" to handle the TMU channels on
>    Exynos5420 more appropriately
>
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   45 +++++++++
>  drivers/thermal/samsung/exynos_tmu.c               |   58 ++++++++++-
>  drivers/thermal/samsung/exynos_tmu.h               |    2 +
>  drivers/thermal/samsung/exynos_tmu_data.c          |  106 ++++++++++++++++++++
>  drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
>  5 files changed, 215 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 116cca0..5055b31 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -6,6 +6,11 @@
>                "samsung,exynos4412-tmu"
>                "samsung,exynos4210-tmu"
>                "samsung,exynos5250-tmu"
> +              "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
> +              "samsung,exynos5420-tmu-triminfo" for TMU channel 2 Exynos5420
> +                       (Must pass triminfo base)
> +              "samsung,exynos5420-tmu-triminfo-clk" for TMU channel 3 and 4
> +                       Exynos5420 (Must pass triminfo base and triminfo clock)
>                "samsung,exynos5440-tmu"
>  - interrupt-parent : The phandle for the interrupt controller
>  - reg : Address range of the thermal registers. For soc's which has multiple
> @@ -13,6 +18,18 @@
>         interrupt related then 2 set of register has to supplied. First set
>         belongs to each instance of TMU and second set belongs to second set
>         of common TMU registers.
> +
> +  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
> +       channels 2, 3 and 4
> +       Use "samsung,exynos5420-tmu-triminfo" in cases, there is a misplaced
> +       register but no need of another clock to access that base.
> +       Use "samsung,exynos5420-tmu-triminfo-clk" in cases where there is a misplaced
> +       register and we need another clock to access that base.
> +
> +       TRIMINFO at 0x1006c000 contains data for TMU channel 3
> +       TRIMINFO at 0x100a0000 contains data for TMU channel 4
> +       TRIMINFO at 0x10068000 contains data for TMU channel 2
> +
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> @@ -43,6 +60,34 @@ Example 2):
>                 clock-names = "tmu_apbif";
>         };
>
> +Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
> +       /* tmu for CPU2 */
> +       tmu@10068000 {
> +               compatible = "samsung,exynos5420-tmu-triminfo";
> +               reg = <0x10068000 0x100>, <0x1006c000 0x4>;
> +               interrupts = <0 184 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif";
> +       };
> +
> +       /* tmu for CPU3 */
> +       tmu@1006c000 {
> +               compatible = "samsung,exynos5420-tmu-triminfo-clk";
> +               reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
> +               interrupts = <0 185 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif", "tmu_triminfo_apbif";
> +       };
> +
> +       /* tmu for GPU */
> +       tmu@100a0000 {
> +               compatible = "samsung,exynos5420-tmu-triminfo-clk";
> +               reg = <0x100a0000 0x100>, <0x10068000 0x4>;
> +               interrupts = <0 215 0>;
> +               clocks = <&clock 318>;
> +               clock-names = "tmu_apbif", "tmu_triminfo_apbif";
> +       };
> +
>  Note: For multi-instance tmu each instance should have an alias correctly
>  numbered in "aliases" node.
>
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index bbd0fc3..826647c 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -47,6 +47,7 @@
>   * @irq_work: pointer to the irq work structure.
>   * @lock: lock to implement synchronization.
>   * @clk: pointer to the clock structure.
> + * @clk_sec: pointer to the clock structure for accessing the base_second.
>   * @temp_error1: fused value of the first point trim.
>   * @temp_error2: fused value of the second point trim.
>   * @regulator: pointer to the TMU regulator structure.
> @@ -61,7 +62,7 @@ struct exynos_tmu_data {
>         enum soc_type soc;
>         struct work_struct irq_work;
>         struct mutex lock;
> -       struct clk *clk;
> +       struct clk *clk, *clk_sec;
>         u8 temp_error1, temp_error2;
>         struct regulator *regulator;
>         struct thermal_sensor_conf *reg_conf;
> @@ -152,6 +153,8 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>
>         mutex_lock(&data->lock);
>         clk_enable(data->clk);
> +       if (!IS_ERR(data->clk_sec))
> +               clk_enable(data->clk_sec);
>
>         if (TMU_SUPPORTS(pdata, READY_STATUS)) {
>                 status = readb(data->base + reg->tmu_status);
> @@ -186,7 +189,13 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
>                         EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
>                 }
>         } else {
> -               trim_info = readl(data->base + reg->triminfo_data);
> +               /* On exynos5420 the triminfo register is in the shared space */
> +               if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO ||
> +                       data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO_CLK)
> +                       trim_info = readl(data->base_second +
> +                                                       reg->triminfo_data);
> +               else
> +                       trim_info = readl(data->base + reg->triminfo_data);
>         }
>         data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
>         data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
> @@ -301,6 +310,8 @@ skip_calib_data:
>  out:
>         clk_disable(data->clk);
>         mutex_unlock(&data->lock);
> +       if (!IS_ERR(data->clk_sec))
> +               clk_disable(data->clk_sec);
>
>         return ret;
>  }
> @@ -452,12 +463,16 @@ static void exynos_tmu_work(struct work_struct *work)
>         const struct exynos_tmu_registers *reg = pdata->registers;
>         unsigned int val_irq, val_type;
>
> +       if (!IS_ERR(data->clk_sec))
> +               clk_enable(data->clk_sec);
>         /* Find which sensor generated this interrupt */
>         if (reg->tmu_irqstatus) {
>                 val_type = readl(data->base_second + reg->tmu_irqstatus);
>                 if (!((val_type >> data->id) & 0x1))
>                         goto out;
>         }
> +       if (!IS_ERR(data->clk_sec))
> +               clk_disable(data->clk_sec);
>
>         exynos_report_trigger(data->reg_conf);
>         mutex_lock(&data->lock);
> @@ -498,6 +513,18 @@ static const struct of_device_id exynos_tmu_match[] = {
>                 .data = (void *)EXYNOS5250_TMU_DRV_DATA,
>         },
>         {
> +               .compatible = "samsung,exynos5420-tmu",
> +               .data = (void *)EXYNOS5420_TMU_DRV_DATA,
> +       },
> +       {
> +               .compatible = "samsung,exynos5420-tmu-triminfo",
> +               .data = (void *)EXYNOS5420_TMU_DRV_DATA,
> +       },
> +       {
> +               .compatible = "samsung,exynos5420-tmu-triminfo-clk",
> +               .data = (void *)EXYNOS5420_TMU_DRV_DATA,
> +       },
> +       {
>                 .compatible = "samsung,exynos5440-tmu",
>                 .data = (void *)EXYNOS5440_TMU_DRV_DATA,
>         },
> @@ -628,13 +655,31 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>                 return  PTR_ERR(data->clk);
>         }
>
> +       data->clk_sec = devm_clk_get(&pdev->dev, "tmu_apbif_triminfo");
> +       if (IS_ERR(data->clk_sec)) {
> +               if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO_CLK) {
> +                       dev_err(&pdev->dev, "Failed to get triminfo clock\n");
> +                       return PTR_ERR(data->clk_sec);
> +               }
> +       } else {
> +               ret = clk_prepare(data->clk_sec);
> +               if (ret) {
> +                       dev_err(&pdev->dev, "Failed to get clock\n");
> +                       return ret;
> +               }
> +       }
> +
>         ret = clk_prepare(data->clk);
> -       if (ret)
> -               return ret;
> +       if (ret) {
> +               dev_err(&pdev->dev, "Failed to get clock\n");
> +               goto err_clk_sec;
> +       }
>
>         if (pdata->type == SOC_ARCH_EXYNOS4210 ||
>             pdata->type == SOC_ARCH_EXYNOS4412 ||
>             pdata->type == SOC_ARCH_EXYNOS5250 ||
> +           pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
> +           pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO_CLK ||
>             pdata->type == SOC_ARCH_EXYNOS5440)
>                 data->soc = pdata->type;
>         else {
> @@ -703,6 +748,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>         return 0;
>  err_clk:
>         clk_unprepare(data->clk);
> +err_clk_sec:
> +       if (!IS_ERR(data->clk_sec))
> +               clk_unprepare(data->clk_sec);
>         return ret;
>  }
>
> @@ -715,6 +763,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>         exynos_unregister_thermal(data->reg_conf);
>
>         clk_unprepare(data->clk);
> +       if (!IS_ERR(data->clk_sec))
> +               clk_unprepare(data->clk_sec);
>
>         if (!IS_ERR(data->regulator))
>                 regulator_disable(data->regulator);
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 0d6b32f..f2eb3ac 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -43,6 +43,8 @@ enum soc_type {
>         SOC_ARCH_EXYNOS4210 = 1,
>         SOC_ARCH_EXYNOS4412,
>         SOC_ARCH_EXYNOS5250,
> +       SOC_ARCH_EXYNOS5420_TRIMINFO,
> +       SOC_ARCH_EXYNOS5420_TRIMINFO_CLK,
>         SOC_ARCH_EXYNOS5440,
>  };
>
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 1d27069..ff79c9a 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -194,6 +194,112 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
>  };
>  #endif
>
> +#if defined(CONFIG_SOC_EXYNOS5420)
> +static const struct exynos_tmu_registers exynos5420_tmu_registers = {
> +       .triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
> +       .triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
> +       .triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
> +       .tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
> +       .buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
> +       .buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
> +       .therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
> +       .therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
> +       .therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
> +       .buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
> +       .buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
> +       .core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
> +       .tmu_status = EXYNOS_TMU_REG_STATUS,
> +       .tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
> +       .threshold_th0 = EXYNOS_THD_TEMP_RISE,
> +       .threshold_th1 = EXYNOS_THD_TEMP_FALL,
> +       .tmu_inten = EXYNOS_TMU_REG_INTEN,
> +       .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
> +       .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
> +       .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
> +       /* INTEN_RISE3 Not availble in exynos5420 */
> +       .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
> +       .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
> +       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
> +       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +       .intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
> +       .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> +       .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> +       .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
> +       .emul_con = EXYNOS_EMUL_CON,
> +       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> +       .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> +       .emul_time_mask = EXYNOS_EMUL_TIME_MASK,
> +};
> +
> +#define __EXYNOS5420_TMU_DATA  \
> +       .threshold_falling = 10, \
> +       .trigger_levels[0] = 85, \
> +       .trigger_levels[1] = 103, \
> +       .trigger_levels[2] = 110, \
> +       .trigger_levels[3] = 120, \
> +       .trigger_enable[0] = true, \
> +       .trigger_enable[1] = true, \
> +       .trigger_enable[2] = true, \
> +       .trigger_enable[3] = false, \
> +       .trigger_type[0] = THROTTLE_ACTIVE, \
> +       .trigger_type[1] = THROTTLE_ACTIVE, \
> +       .trigger_type[2] = SW_TRIP, \
> +       .trigger_type[3] = HW_TRIP, \
> +       .max_trigger_level = 4, \
> +       .gain = 8, \
> +       .reference_voltage = 16, \
> +       .noise_cancel_mode = 4, \
> +       .cal_type = TYPE_ONE_POINT_TRIMMING, \
> +       .efuse_value = 55, \
> +       .min_efuse_value = 40, \
> +       .max_efuse_value = 100, \
> +       .first_point_trim = 25, \
> +       .second_point_trim = 85, \
> +       .default_temp_offset = 50, \
> +       .freq_tab[0] = { \
> +               .freq_clip_max = 800 * 1000, \
> +               .temp_level = 85, \
> +       }, \
> +       .freq_tab[1] = { \
> +               .freq_clip_max = 200 * 1000, \
> +               .temp_level = 103, \
> +       }, \
> +       .freq_tab_count = 2, \
> +       .registers = &exynos5420_tmu_registers, \
> +
> +#define EXYNOS5420_TMU_DATA \
> +       __EXYNOS5420_TMU_DATA \
> +       .type = SOC_ARCH_EXYNOS5250, \
> +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +                       TMU_SUPPORT_EMUL_TIME)
> +
> +#define EXYNOS5420_TMU_DATA_SHARED \
> +       __EXYNOS5420_TMU_DATA \
> +       .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
> +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +                       TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
> +
> +#define EXYNOS5420_TMU_DATA_SHARED_CLK \
> +       __EXYNOS5420_TMU_DATA \
> +       .type = SOC_ARCH_EXYNOS5420_TRIMINFO_CLK, \
> +       .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +                       TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +                       TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
> +
> +struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
> +       .tmu_data = {
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA },
> +               { EXYNOS5420_TMU_DATA_SHARED },
> +               { EXYNOS5420_TMU_DATA_SHARED_CLK },
> +               { EXYNOS5420_TMU_DATA_SHARED_CLK },
> +       },
> +       .tmu_count = 5,
> +};
> +#endif
> +
>  #if defined(CONFIG_SOC_EXYNOS5440)
>  static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> index d9495a4..41f06dc 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> @@ -72,6 +72,7 @@
>  #define EXYNOS_TMU_CLEAR_RISE_INT      0x111
>  #define EXYNOS_TMU_CLEAR_FALL_INT      (0x111 << 12)
>  #define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT        12
> +#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT    16
>  #define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT    4
>  #define EXYNOS_TMU_TRIP_MODE_SHIFT     13
>  #define EXYNOS_TMU_TRIP_MODE_MASK      0x7
> @@ -156,6 +157,13 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
>  #define EXYNOS5250_TMU_DRV_DATA (NULL)
>  #endif
>
> +#if defined(CONFIG_SOC_EXYNOS5420)
> +extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
> +#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
> +#else
> +#define EXYNOS5420_TMU_DRV_DATA (NULL)
> +#endif
> +
>  #if defined(CONFIG_SOC_EXYNOS5440)
>  extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
>  #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
> --
> 1.7.10.4
>
Any update on this patch set, its been
Acked by Amit and Reviewed-by Bartlomiej Zolnierkiewicz


-- 
Shine bright,
(: Nav :)

Re: [PATCH 2/4 v10] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Ch]

Hello All,

On 19 November 2013 18:34, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> On Exynos5440 and Exynos5420 there are registers common
> across the TMU channels.
>
> To support that, we introduced a ADDRESS_MULTIPLE flag in the
> driver and the 2nd set of register base and size are provided
> in the "reg" property of the node.
>
> As per Amit's suggestion, this patch changes the base_common
> to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
> Changes since v9:
> Just respinning
>
> Changes since v8:
>  None
>  .../devicetree/bindings/thermal/exynos-thermal.txt       |    4 ++--
>  drivers/thermal/samsung/exynos_tmu.c                     |   14 +++++++-------
>  drivers/thermal/samsung/exynos_tmu.h                     |    4 ++--
>  drivers/thermal/samsung/exynos_tmu_data.c                |    2 +-
>  4 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 284f530..116cca0 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -11,8 +11,8 @@
>  - reg : Address range of the thermal registers. For soc's which has multiple
>         instances of TMU and some registers are shared across all TMU's like
>         interrupt related then 2 set of register has to supplied. First set
> -       belongs to each instance of TMU and second set belongs to common TMU
> -       registers.
> +       belongs to each instance of TMU and second set belongs to second set
> +       of common TMU registers.
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index c493245..bbd0fc3 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -41,7 +41,7 @@
>   * @id: identifier of the one instance of the TMU controller.
>   * @pdata: pointer to the tmu platform/configuration data
>   * @base: base address of the single instance of the TMU controller.
> - * @base_common: base address of the common registers of the TMU controller.
> + * @base_second: base address of the common registers of the TMU controller.
>   * @irq: irq number of the TMU controller.
>   * @soc: id of the SOC type.
>   * @irq_work: pointer to the irq work structure.
> @@ -56,7 +56,7 @@ struct exynos_tmu_data {
>         int id;
>         struct exynos_tmu_platform_data *pdata;
>         void __iomem *base;
> -       void __iomem *base_common;
> +       void __iomem *base_second;
>         int irq;
>         enum soc_type soc;
>         struct work_struct irq_work;
> @@ -297,7 +297,7 @@ skip_calib_data:
>         }
>         /*Clear the PMIN in the common TMU register*/
>         if (reg->tmu_pmin && !data->id)
> -               writel(0, data->base_common + reg->tmu_pmin);
> +               writel(0, data->base_second + reg->tmu_pmin);
>  out:
>         clk_disable(data->clk);
>         mutex_unlock(&data->lock);
> @@ -454,7 +454,7 @@ static void exynos_tmu_work(struct work_struct *work)
>
>         /* Find which sensor generated this interrupt */
>         if (reg->tmu_irqstatus) {
> -               val_type = readl(data->base_common + reg->tmu_irqstatus);
> +               val_type = readl(data->base_second + reg->tmu_irqstatus);
>                 if (!((val_type >> data->id) & 0x1))
>                         goto out;
>         }
> @@ -579,7 +579,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>          * Check if the TMU shares some registers and then try to map the
>          * memory of common registers.
>          */
> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
> +       if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
>                 return 0;
>
>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
> @@ -587,9 +587,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>                 return -ENODEV;
>         }
>
> -       data->base_common = devm_ioremap(&pdev->dev, res.start,
> +       data->base_second = devm_ioremap(&pdev->dev, res.start,
>                                         resource_size(&res));
> -       if (!data->base_common) {
> +       if (!data->base_second) {
>                 dev_err(&pdev->dev, "Failed to ioremap memory\n");
>                 return -ENOMEM;
>         }
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 980859a..0d6b32f 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -60,7 +60,7 @@ enum soc_type {
>   *                     state(active/idle) can be checked.
>   * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
>   *                     sample time.
> - * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
> + * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
>   *                     sensors shares some common registers.
>   * TMU_SUPPORT - macro to compare the above features with the supplied.
>   */
> @@ -70,7 +70,7 @@ enum soc_type {
>  #define TMU_SUPPORT_FALLING_TRIP               BIT(3)
>  #define TMU_SUPPORT_READY_STATUS               BIT(4)
>  #define TMU_SUPPORT_EMUL_TIME                  BIT(5)
> -#define TMU_SUPPORT_SHARED_MEMORY              BIT(6)
> +#define TMU_SUPPORT_ADDRESS_MULTIPLE           BIT(6)
>
>  #define TMU_SUPPORTS(a, b)     (a->features & TMU_SUPPORT_ ## b)
>
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 7cdb04e..1d27069 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -255,7 +255,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .type = SOC_ARCH_EXYNOS5440, \
>         .registers = &exynos5440_tmu_registers, \
>         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
> -                       TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
> +                       TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
>
>  struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
>         .tmu_data = {
> --
> 1.7.10.4
>
Any update on this patch set, its been
Acked by Amit and Reviewed-by Bartlomiej Zolnierkiewicz


-- 
Shine bright,
(: Nav :)

Re: [PATCH 3/4 v9] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Tomasz Figa]

Hi Naveen, Andrew,

Please see my comments inline.

On Tuesday 12 of November 2013 12:07:05 Naveen Krishna Chatradhi wrote:
> Exynos5420 has 5 TMU channels, the TRIMINFO register is
> misplaced for TMU channels 2, 3 and 4
> TRIMINFO at 0x1006c000 contains data for TMU channel 3
> TRIMINFO at 0x100a0000 contains data for TMU channel 4
> TRIMINFO at 0x10068000 contains data for TMU channel 2
> 
> This patch
> 1 Adds the neccessary register changes and arch information
>    to support Exynos5420 SoCs.
> 2. Handles the gate clock for misplaced TRIMINFO register
> 3. Updates the Documentation at
>    Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> ---
> Changes since v8:
> 1. rewrote the Documentation for device tree bindings
> 2. Merged the https://lkml.org/lkml/2013/11/7/262 (as this is a fix)
> 3. introduces "samsung,exynos5420-tmu-triminfo" and 
>    "samsung,exynos5420-tmu-triminfo-clk" to handle the TMU channels on
>    Exynos5420 more appropriately
> 
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   45 +++++++++
>  drivers/thermal/samsung/exynos_tmu.c               |   58 ++++++++++-
>  drivers/thermal/samsung/exynos_tmu.h               |    2 +
>  drivers/thermal/samsung/exynos_tmu_data.c          |  106 ++++++++++++++++++++
>  drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
>  5 files changed, 215 insertions(+), 4 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 116cca0..5055b31 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -6,6 +6,11 @@
>  	       "samsung,exynos4412-tmu"
>  	       "samsung,exynos4210-tmu"
>  	       "samsung,exynos5250-tmu"
> +	       "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
> +	       "samsung,exynos5420-tmu-triminfo" for TMU channel 2 Exynos5420
> +			(Must pass triminfo base)
> +	       "samsung,exynos5420-tmu-triminfo-clk" for TMU channel 3 and 4
> +			Exynos5420 (Must pass triminfo base and triminfo clock)

I don't think you need those two separate compatible values. Instead you
can keep only the one that requires clock and specify the same base clock
as triminfo clock. Also IMHO "samsung,exynos5420-tmu-ext-triminfo" would
be a better name, as it describes the hardware better (TMU with external
triminfo block, as opposed to normal TMU that has it internally).

Otherwise the patch looks fine.

Best regards,
Tomasz

Re: [PATCH 3/4 v10] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Tomasz Figa]

Hi Naveen,

On Tuesday 19 of November 2013 18:35:25 Naveen Krishna Chatradhi wrote:
> Exynos5420 has 5 TMU channels, the TRIMINFO register is
> misplaced for TMU channels 2, 3 and 4
> TRIMINFO at 0x1006c000 contains data for TMU channel 3
> TRIMINFO at 0x100a0000 contains data for TMU channel 4
> TRIMINFO at 0x10068000 contains data for TMU channel 2
> 
> This patch
> 1 Adds the neccessary register changes and arch information
>    to support Exynos5420 SoCs.
> 2. Handles the gate clock for misplaced TRIMINFO register
> 3. Updates the Documentation at
>    Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
> Changes since v9:
> Just respinning
> 
> Changes since v8:
> 1. rewrote the Documentation for device tree bindings
> 2. Merged the https://lkml.org/lkml/2013/11/7/262 (as this is a fix)
> 3. introduces "samsung,exynos5420-tmu-triminfo" and 
>    "samsung,exynos5420-tmu-triminfo-clk" to handle the TMU channels on
>    Exynos5420 more appropriately
> 
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   45 +++++++++
>  drivers/thermal/samsung/exynos_tmu.c               |   58 ++++++++++-
>  drivers/thermal/samsung/exynos_tmu.h               |    2 +
>  drivers/thermal/samsung/exynos_tmu_data.c          |  106 ++++++++++++++++++++
>  drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
>  5 files changed, 215 insertions(+), 4 deletions(-)

I have replied to previous version by mistake, but since this is just
a respin, same comments apply.

Best regards,
Tomasz

Re: [PATCH 2/4 v10] thermal: samsung: change base_common to more meaningful base_second

[Tomasz Figa]

Hi Naveen,

On Tuesday 19 of November 2013 18:34:51 Naveen Krishna Chatradhi wrote:
> On Exynos5440 and Exynos5420 there are registers common
> across the TMU channels.
> 
> To support that, we introduced a ADDRESS_MULTIPLE flag in the
> driver and the 2nd set of register base and size are provided
> in the "reg" property of the node.
> 
> As per Amit's suggestion, this patch changes the base_common
> to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
> Changes since v9:
> Just respinning
> 
> Changes since v8:
>  None
>  .../devicetree/bindings/thermal/exynos-thermal.txt       |    4 ++--
>  drivers/thermal/samsung/exynos_tmu.c                     |   14 +++++++-------
>  drivers/thermal/samsung/exynos_tmu.h                     |    4 ++--
>  drivers/thermal/samsung/exynos_tmu_data.c                |    2 +-
>  4 files changed, 12 insertions(+), 12 deletions(-)

Please see my comments inline.

> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 284f530..116cca0 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -11,8 +11,8 @@
>  - reg : Address range of the thermal registers. For soc's which has multiple
>  	instances of TMU and some registers are shared across all TMU's like
>  	interrupt related then 2 set of register has to supplied. First set
> -	belongs	to each instance of TMU and second set belongs to common TMU
> -	registers.
> +	belongs	to each instance of TMU and second set belongs to second set
> +	of common TMU registers.

Just a wording issue, I think: If this is "second set of common TMU
registers", then where is the first set of common TMU registers?

Otherwise the patch looks fine.

Best regards,
Tomasz

Re: [PATCH 1/4 v10] thermal: samsung: replace inten_ bit fields with intclr_

[Tomasz Figa]

Hi Naveen,

On Tuesday 19 of November 2013 18:34:19 Naveen Krishna Chatradhi wrote:
> This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
> with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
> Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only used
> to configure intclr related registers.
> 
> Description of H/W:
> The offset for the bits in the CLEAR register are not consistent across TMU
> modules in Exynso5250, 5420 and 5440.
> 
> On Exynos5250, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT registers and at an offset of
> 12 in INTCLEAR register.
> 
> On Exynos5420, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT and INTCLEAR registers.
> 
> On Exynos5440,
> the FALL_IRQEN bits are at an offset of 4
> and the RISE_IRQEN bits are at an offset of 0
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
> Changes since v9:
> Just respinning
> 
> Changes since v8:
> 1. Modified the patch description,
> 2. replaces the inten_rise/fall_shift/mask with intclr_rise/fall_shift/mask
> 
>  drivers/thermal/samsung/exynos_tmu.c      |    6 +++---
>  drivers/thermal/samsung/exynos_tmu.h      |   16 ++++++++--------
>  drivers/thermal/samsung/exynos_tmu_data.c |   18 +++++++++---------
>  drivers/thermal/samsung/exynos_tmu_data.h |    4 ++--
>  4 files changed, 22 insertions(+), 22 deletions(-)

Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

[PATCH v11 0/4] thermal: samsung: Clean up and add support for Exynos5420

[Naveen Krishna Chatradhi]

This patchset does a little clean up of the existing code (linux-soc-thermal)
1.  [v11] thermal: samsung: replace inten_ bit fields with intclr_
2.  [v11] thermal: samsung: change base_common to more meaningful base_second

adds support for Exynos5420 in the driver and (linux-soc-thermal)
3.  [v11] thermal: samsung: Add TMU support for Exynos5420 SoCs
also adds the device tree nodes for the same to exynos5420.dtsi (linux-samsung.git)
4.  [v11] ARM: dts: Exynos5420: Add device nodes for TMU blocks

(linux-soc-thermal)
Naveen Krishna Chatradhi (3):
  thermal: samsung: replace inten_ bit fields with intclr_
  thermal: samsung: change base_common to more meaningful base_second
  thermal: samsung: Add TMU support for Exynos5420 SoCs

 .../devicetree/bindings/thermal/exynos-thermal.txt |   42 ++++++-
 drivers/thermal/samsung/exynos_tmu.c               |   72 +++++++++---
 drivers/thermal/samsung/exynos_tmu.h               |   21 ++--
 drivers/thermal/samsung/exynos_tmu_data.c          |  119 ++++++++++++++++++--
 drivers/thermal/samsung/exynos_tmu_data.h          |   12 +-
 5 files changed, 228 insertions(+), 38 deletions(-)

(linux-samsung.git)
Naveen Krishna Chatradhi (1):
  ARM: dts: Exynos5420: Add device nodes for TMU blocks

 arch/arm/boot/dts/exynos5420.dtsi |   40 +++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)
-- 
1.7.10.4

[PATCH v11 1/4] thermal: samsung: replace inten_ bit fields with intclr_

[Naveen Krishna Chatradhi]

This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only used
to configure intclr related registers.

Description of H/W:
The offset for the bits in the CLEAR register are not consistent across TMU
modules in Exynso5250, 5420 and 5440.

On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT registers and at an offset of
12 in INTCLEAR register.

On Exynos5420, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT and INTCLEAR registers.

On Exynos5440,
the FALL_IRQEN bits are at an offset of 4
and the RISE_IRQEN bits are at an offset of 0

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
Changes since v10:
None

 drivers/thermal/samsung/exynos_tmu.c      |    6 +++---
 drivers/thermal/samsung/exynos_tmu.h      |   16 ++++++++--------
 drivers/thermal/samsung/exynos_tmu_data.c |   18 +++++++++---------
 drivers/thermal/samsung/exynos_tmu_data.h |    4 ++--
 4 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 32f38b9..c493245 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -237,7 +237,7 @@ skip_calib_data:
 			writeb(pdata->trigger_levels[i], data->base +
 			reg->threshold_th0 + i * sizeof(reg->threshold_th0));
 
-		writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
+		writel(reg->intclr_rise_mask, data->base + reg->tmu_intclear);
 	} else {
 		/* Write temperature code for rising and falling threshold */
 		for (i = 0;
@@ -264,8 +264,8 @@ skip_calib_data:
 		writel(falling_threshold,
 				data->base + reg->threshold_th1);
 
-		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
-			(reg->inten_fall_mask << reg->inten_fall_shift),
+		writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |
+			(reg->intclr_fall_mask << reg->intclr_fall_shift),
 				data->base + reg->tmu_intclear);
 
 		/* if last threshold limit is also present */
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 3fb6554..980859a 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -122,10 +122,6 @@ enum soc_type {
  * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
  * @tmu_inten: register containing the different threshold interrupt
 	enable bits.
- * @inten_rise_shift: shift bits of all rising interrupt bits.
- * @inten_rise_mask: mask bits of all rising interrupt bits.
- * @inten_fall_shift: shift bits of all rising interrupt bits.
- * @inten_fall_mask: mask bits of all rising interrupt bits.
  * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
  * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
  * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
@@ -136,6 +132,10 @@ enum soc_type {
  * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
  * @tmu_intstat: Register containing the interrupt status values.
  * @tmu_intclear: Register for clearing the raised interrupt status.
+ * @intclr_fall_shift: shift bits for interrupt clear fall 0
+ * @intclr_rise_shift: shift bits of all rising interrupt bits.
+ * @intclr_rise_mask: mask bits of all rising interrupt bits.
+ * @intclr_fall_mask: mask bits of all rising interrupt bits.
  * @emul_con: TMU emulation controller register.
  * @emul_temp_shift: shift bits of emulation temperature.
  * @emul_time_shift: shift bits of emulation time.
@@ -191,10 +191,6 @@ struct exynos_tmu_registers {
 	u32	threshold_th3_l0_shift;
 
 	u32	tmu_inten;
-	u32	inten_rise_shift;
-	u32	inten_rise_mask;
-	u32	inten_fall_shift;
-	u32	inten_fall_mask;
 	u32	inten_rise0_shift;
 	u32	inten_rise1_shift;
 	u32	inten_rise2_shift;
@@ -207,6 +203,10 @@ struct exynos_tmu_registers {
 	u32	tmu_intstat;
 
 	u32	tmu_intclear;
+	u32	intclr_fall_shift;
+	u32	intclr_rise_shift;
+	u32	intclr_fall_mask;
+	u32	intclr_rise_mask;
 
 	u32	emul_con;
 	u32	emul_temp_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 073c292..7cdb04e 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -40,13 +40,13 @@ static const struct exynos_tmu_registers exynos4210_tmu_registers = {
 	.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
 	.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
 	.tmu_inten = EXYNOS_TMU_REG_INTEN,
-	.inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
 	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
 };
 
 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
@@ -112,10 +112,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
 	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
 	.tmu_inten = EXYNOS_TMU_REG_INTEN,
-	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
-	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
-	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
-	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
 	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
@@ -123,6 +119,10 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
+	.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 	.emul_con = EXYNOS_EMUL_CON,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -217,10 +217,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
 	.threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
 	.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
-	.inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
-	.inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
-	.inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
-	.inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
 	.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
@@ -228,6 +224,10 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
+	.intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
+	.intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
+	.intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
+	.intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
 	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index a1ea19d..d9495a4 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -69,9 +69,10 @@
 #define EXYNOS_TMU_RISE_INT_MASK	0x111
 #define EXYNOS_TMU_RISE_INT_SHIFT	0
 #define EXYNOS_TMU_FALL_INT_MASK	0x111
-#define EXYNOS_TMU_FALL_INT_SHIFT	12
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
+#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
+#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
@@ -119,7 +120,6 @@
 #define EXYNOS5440_TMU_RISE_INT_MASK		0xf
 #define EXYNOS5440_TMU_RISE_INT_SHIFT		0
 #define EXYNOS5440_TMU_FALL_INT_MASK		0xf
-#define EXYNOS5440_TMU_FALL_INT_SHIFT		4
 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT	0
 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT	1
 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT	2
-- 
1.7.10.4

[PATCH v11 2/4] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Chatradhi]

On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.

To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the "reg" property of the node.

As per Amit's suggestion, this patch changes the base_common
to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
Changes since v10:
Documentation rephrased as per comments from Tomasz Figa

 .../devicetree/bindings/thermal/exynos-thermal.txt       |    4 ++--
 drivers/thermal/samsung/exynos_tmu.c                     |   14 +++++++-------
 drivers/thermal/samsung/exynos_tmu.h                     |    4 ++--
 drivers/thermal/samsung/exynos_tmu_data.c                |    2 +-
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 284f530..a1aa602 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -11,8 +11,8 @@
 - reg : Address range of the thermal registers. For soc's which has multiple
 	instances of TMU and some registers are shared across all TMU's like
 	interrupt related then 2 set of register has to supplied. First set
-	belongs	to each instance of TMU and second set belongs to common TMU
-	registers.
+	belongs	to register set of TMU instance and second set belongs to
+	registers shared with the TMU instance.
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index c493245..bbd0fc3 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -41,7 +41,7 @@
  * @id: identifier of the one instance of the TMU controller.
  * @pdata: pointer to the tmu platform/configuration data
  * @base: base address of the single instance of the TMU controller.
- * @base_common: base address of the common registers of the TMU controller.
+ * @base_second: base address of the common registers of the TMU controller.
  * @irq: irq number of the TMU controller.
  * @soc: id of the SOC type.
  * @irq_work: pointer to the irq work structure.
@@ -56,7 +56,7 @@ struct exynos_tmu_data {
 	int id;
 	struct exynos_tmu_platform_data *pdata;
 	void __iomem *base;
-	void __iomem *base_common;
+	void __iomem *base_second;
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -297,7 +297,7 @@ skip_calib_data:
 	}
 	/*Clear the PMIN in the common TMU register*/
 	if (reg->tmu_pmin && !data->id)
-		writel(0, data->base_common + reg->tmu_pmin);
+		writel(0, data->base_second + reg->tmu_pmin);
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
@@ -454,7 +454,7 @@ static void exynos_tmu_work(struct work_struct *work)
 
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
-		val_type = readl(data->base_common + reg->tmu_irqstatus);
+		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
@@ -579,7 +579,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 	 * Check if the TMU shares some registers and then try to map the
 	 * memory of common registers.
 	 */
-	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
+	if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
 		return 0;
 
 	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
@@ -587,9 +587,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	data->base_common = devm_ioremap(&pdev->dev, res.start,
+	data->base_second = devm_ioremap(&pdev->dev, res.start,
 					resource_size(&res));
-	if (!data->base_common) {
+	if (!data->base_second) {
 		dev_err(&pdev->dev, "Failed to ioremap memory\n");
 		return -ENOMEM;
 	}
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 980859a..0d6b32f 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -60,7 +60,7 @@ enum soc_type {
  *			state(active/idle) can be checked.
  * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
  *			sample time.
- * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
+ * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
  *			sensors shares some common registers.
  * TMU_SUPPORT - macro to compare the above features with the supplied.
  */
@@ -70,7 +70,7 @@ enum soc_type {
 #define TMU_SUPPORT_FALLING_TRIP		BIT(3)
 #define TMU_SUPPORT_READY_STATUS		BIT(4)
 #define TMU_SUPPORT_EMUL_TIME			BIT(5)
-#define TMU_SUPPORT_SHARED_MEMORY		BIT(6)
+#define TMU_SUPPORT_ADDRESS_MULTIPLE		BIT(6)
 
 #define TMU_SUPPORTS(a, b)	(a->features & TMU_SUPPORT_ ## b)
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 7cdb04e..1d27069 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -255,7 +255,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.type = SOC_ARCH_EXYNOS5440, \
 	.registers = &exynos5440_tmu_registers, \
 	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
-			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
+			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 
 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 	.tmu_data = {
-- 
1.7.10.4

[PATCH v11 3/4] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Chatradhi]

Exynos5420 has 5 TMU channels, the TRIMINFO register is
misplaced for TMU channels 2, 3 and 4
TRIMINFO at 0x1006c000 contains data for TMU channel 3
TRIMINFO at 0x100a0000 contains data for TMU channel 4
TRIMINFO at 0x10068000 contains data for TMU channel 2

This patch
1 Adds the neccessary register changes and arch information
   to support Exynos5420 SoCs.
2. Handles the gate clock for misplaced TRIMINFO register
3. Updates the Documentation at
   Documentation/devicetree/bindings/thermal/exynos-thermal.txt

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
Changes since v10:
1. using renamed compatible "samsung,exynos5420-tmu-ext-triminfo"
   and passing same clock as triminfo_apbif clock for channel 2
2. removed the "exynos5420-tmu-triminfo-clk" compatible

 .../devicetree/bindings/thermal/exynos-thermal.txt |   38 ++++++++
 drivers/thermal/samsung/exynos_tmu.c               |   52 +++++++++-
 drivers/thermal/samsung/exynos_tmu.h               |    1 +
 drivers/thermal/samsung/exynos_tmu_data.c          |   99 ++++++++++++++++++++
 drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
 5 files changed, 194 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index a1aa602..a3e78c0 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -6,6 +6,9 @@
 	       "samsung,exynos4412-tmu"
 	       "samsung,exynos4210-tmu"
 	       "samsung,exynos5250-tmu"
+	       "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
+	       "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
+			Exynos5420 (Must pass triminfo base and triminfo clock)
 	       "samsung,exynos5440-tmu"
 - interrupt-parent : The phandle for the interrupt controller
 - reg : Address range of the thermal registers. For soc's which has multiple
@@ -13,6 +16,16 @@
 	interrupt related then 2 set of register has to supplied. First set
 	belongs	to register set of TMU instance and second set belongs to
 	registers shared with the TMU instance.
+
+  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
+	channels 2, 3 and 4
+	Use "samsung,exynos5420-tmu-ext-triminfo" in cases, there is a misplaced
+	register, also provide clock to access that base.
+
+	TRIMINFO at 0x1006c000 contains data for TMU channel 3
+	TRIMINFO at 0x100a0000 contains data for TMU channel 4
+	TRIMINFO at 0x10068000 contains data for TMU channel 2
+
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
@@ -43,6 +56,31 @@ Example 2):
 		clock-names = "tmu_apbif";
 	};
 
+Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
+	tmu_cpu2: tmu@10068000 {
+		compatible = "samsung,exynos5420-tmu-ext-triminfo";
+		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+		interrupts = <0 184 0>;
+		clocks = <&clock 318>, <&clock 318>;
+		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+	};
+
+	tmu_cpu3: tmu@1006c000 {
+		compatible = "samsung,exynos5420-tmu-ext-triminfo";
+		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+		interrupts = <0 185 0>;
+		clocks = <&clock 318>, <&clock 319>;
+		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+	};
+
+	tmu_gpu: tmu@100a0000 {
+		compatible = "samsung,exynos5420-tmu-ext-triminfo";
+		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
+		interrupts = <0 215 0>;
+		clocks = <&clock 319>, <&clock 318>;
+		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+	};
+
 Note: For multi-instance tmu each instance should have an alias correctly
 numbered in "aliases" node.
 
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index bbd0fc3..6f40c91 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -47,6 +47,7 @@
  * @irq_work: pointer to the irq work structure.
  * @lock: lock to implement synchronization.
  * @clk: pointer to the clock structure.
+ * @clk_sec: pointer to the clock structure for accessing the base_second.
  * @temp_error1: fused value of the first point trim.
  * @temp_error2: fused value of the second point trim.
  * @regulator: pointer to the TMU regulator structure.
@@ -61,7 +62,7 @@ struct exynos_tmu_data {
 	enum soc_type soc;
 	struct work_struct irq_work;
 	struct mutex lock;
-	struct clk *clk;
+	struct clk *clk, *clk_sec;
 	u8 temp_error1, temp_error2;
 	struct regulator *regulator;
 	struct thermal_sensor_conf *reg_conf;
@@ -152,6 +153,8 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 
 	mutex_lock(&data->lock);
 	clk_enable(data->clk);
+	if (!IS_ERR(data->clk_sec))
+		clk_enable(data->clk_sec);
 
 	if (TMU_SUPPORTS(pdata, READY_STATUS)) {
 		status = readb(data->base + reg->tmu_status);
@@ -186,7 +189,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
 		}
 	} else {
-		trim_info = readl(data->base + reg->triminfo_data);
+		/* On exynos5420 the triminfo register is in the shared space */
+		if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
+			trim_info = readl(data->base_second +
+							reg->triminfo_data);
+		else
+			trim_info = readl(data->base + reg->triminfo_data);
 	}
 	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
@@ -301,6 +309,8 @@ skip_calib_data:
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
+	if (!IS_ERR(data->clk_sec))
+		clk_disable(data->clk_sec);
 
 	return ret;
 }
@@ -452,12 +462,16 @@ static void exynos_tmu_work(struct work_struct *work)
 	const struct exynos_tmu_registers *reg = pdata->registers;
 	unsigned int val_irq, val_type;
 
+	if (!IS_ERR(data->clk_sec))
+		clk_enable(data->clk_sec);
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
 		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
+	if (!IS_ERR(data->clk_sec))
+		clk_disable(data->clk_sec);
 
 	exynos_report_trigger(data->reg_conf);
 	mutex_lock(&data->lock);
@@ -498,6 +512,14 @@ static const struct of_device_id exynos_tmu_match[] = {
 		.data = (void *)EXYNOS5250_TMU_DRV_DATA,
 	},
 	{
+		.compatible = "samsung,exynos5420-tmu",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
+		.compatible = "samsung,exynos5420-tmu-ext-triminfo",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
 		.compatible = "samsung,exynos5440-tmu",
 		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
 	},
@@ -628,13 +650,30 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 		return  PTR_ERR(data->clk);
 	}
 
+	data->clk_sec = devm_clk_get(&pdev->dev, "tmu_apbif_triminfo");
+	if (IS_ERR(data->clk_sec)) {
+		if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
+			dev_err(&pdev->dev, "Failed to get triminfo clock\n");
+			return PTR_ERR(data->clk_sec);
+		}
+	} else {
+		ret = clk_prepare(data->clk_sec);
+		if (ret) {
+			dev_err(&pdev->dev, "Failed to get clock\n");
+			return ret;
+		}
+	}
+
 	ret = clk_prepare(data->clk);
-	if (ret)
-		return ret;
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to get clock\n");
+		goto err_clk_sec;
+	}
 
 	if (pdata->type == SOC_ARCH_EXYNOS4210 ||
 	    pdata->type == SOC_ARCH_EXYNOS4412 ||
 	    pdata->type == SOC_ARCH_EXYNOS5250 ||
+	    pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
 	    pdata->type == SOC_ARCH_EXYNOS5440)
 		data->soc = pdata->type;
 	else {
@@ -703,6 +742,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 	return 0;
 err_clk:
 	clk_unprepare(data->clk);
+err_clk_sec:
+	if (!IS_ERR(data->clk_sec))
+		clk_unprepare(data->clk_sec);
 	return ret;
 }
 
@@ -715,6 +757,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
 	exynos_unregister_thermal(data->reg_conf);
 
 	clk_unprepare(data->clk);
+	if (!IS_ERR(data->clk_sec))
+		clk_unprepare(data->clk_sec);
 
 	if (!IS_ERR(data->regulator))
 		regulator_disable(data->regulator);
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 0d6b32f..60cce28 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -43,6 +43,7 @@ enum soc_type {
 	SOC_ARCH_EXYNOS4210 = 1,
 	SOC_ARCH_EXYNOS4412,
 	SOC_ARCH_EXYNOS5250,
+	SOC_ARCH_EXYNOS5420_TRIMINFO,
 	SOC_ARCH_EXYNOS5440,
 };
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 1d27069..2670cbe 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -194,6 +194,105 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+static const struct exynos_tmu_registers exynos5420_tmu_registers = {
+	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+	.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+	.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+	.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+	.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+	.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+	.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+	.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+	.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+	.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+	.tmu_status = EXYNOS_TMU_REG_STATUS,
+	.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
+	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
+	.tmu_inten = EXYNOS_TMU_REG_INTEN,
+	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+	/* INTEN_RISE3 Not availble in exynos5420 */
+	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
+	.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+	.emul_con = EXYNOS_EMUL_CON,
+	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+	.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define __EXYNOS5420_TMU_DATA	\
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.registers = &exynos5420_tmu_registers, \
+
+#define EXYNOS5420_TMU_DATA \
+	__EXYNOS5420_TMU_DATA \
+	.type = SOC_ARCH_EXYNOS5250, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME)
+
+#define EXYNOS5420_TMU_DATA_SHARED \
+	__EXYNOS5420_TMU_DATA \
+	.type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
+
+struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
+	.tmu_data = {
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+	},
+	.tmu_count = 5,
+};
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index d9495a4..41f06dc 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -72,6 +72,7 @@
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
 #define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
+#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT	16
 #define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
@@ -156,6 +157,13 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
 #define EXYNOS5250_TMU_DRV_DATA (NULL)
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
+#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
+#else
+#define EXYNOS5420_TMU_DRV_DATA (NULL)
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
 #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
-- 
1.7.10.4

Re: [PATCH v11 3/4] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Tomasz Figa]

Hi Naveen,

On Tuesday 10 of December 2013 12:12:25 Naveen Krishna Chatradhi wrote:
> Exynos5420 has 5 TMU channels, the TRIMINFO register is
> misplaced for TMU channels 2, 3 and 4
> TRIMINFO at 0x1006c000 contains data for TMU channel 3
> TRIMINFO at 0x100a0000 contains data for TMU channel 4
> TRIMINFO at 0x10068000 contains data for TMU channel 2
[snip]
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index a1aa602..a3e78c0 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -6,6 +6,9 @@
>  	       "samsung,exynos4412-tmu"
>  	       "samsung,exynos4210-tmu"
>  	       "samsung,exynos5250-tmu"
> +	       "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
> +	       "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
> +			Exynos5420 (Must pass triminfo base and triminfo clock)

Exact clock names must be specified in description of clock-names property.

>  	       "samsung,exynos5440-tmu"
>  - interrupt-parent : The phandle for the interrupt controller
>  - reg : Address range of the thermal registers. For soc's which has multiple
> @@ -13,6 +16,16 @@
>  	interrupt related then 2 set of register has to supplied. First set
>  	belongs	to register set of TMU instance and second set belongs to
>  	registers shared with the TMU instance.
> +
> +  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
> +	channels 2, 3 and 4
> +	Use "samsung,exynos5420-tmu-ext-triminfo" in cases, there is a misplaced
> +	register, also provide clock to access that base.
> +
> +	TRIMINFO at 0x1006c000 contains data for TMU channel 3
> +	TRIMINFO at 0x100a0000 contains data for TMU channel 4
> +	TRIMINFO at 0x10068000 contains data for TMU channel 2
> +
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> @@ -43,6 +56,31 @@ Example 2):
>  		clock-names = "tmu_apbif";
>  	};
>  
> +Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
> +	tmu_cpu2: tmu@10068000 {
> +		compatible = "samsung,exynos5420-tmu-ext-triminfo";
> +		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
> +		interrupts = <0 184 0>;
> +		clocks = <&clock 318>, <&clock 318>;
> +		clock-names = "tmu_apbif", "tmu_triminfo_apbif";

Here you have "tmu_triminfo_apbif" clock, but in the driver you call
clk_get() with "tmu_apbif_triminfo".

> +	};
> +
[snip]
>  
> +	data->clk_sec = devm_clk_get(&pdev->dev, "tmu_apbif_triminfo");

Here you try to get "tmu_apbif_triminfo" clock, but in binding
documentation you have "tmu_triminfo_apbif" in example.

> +	if (IS_ERR(data->clk_sec)) {
> +		if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
> +			dev_err(&pdev->dev, "Failed to get triminfo clock\n");
> +			return PTR_ERR(data->clk_sec);
> +		}
> +	} else {
> +		ret = clk_prepare(data->clk_sec);
> +		if (ret) {
> +			dev_err(&pdev->dev, "Failed to get clock\n");
> +			return ret;
> +		}
> +	}
> +
>  	ret = clk_prepare(data->clk);
> -	if (ret)
> -		return ret;
> +	if (ret) {
> +		dev_err(&pdev->dev, "Failed to get clock\n");
> +		goto err_clk_sec;
> +	}
>  
>  	if (pdata->type == SOC_ARCH_EXYNOS4210 ||
>  	    pdata->type == SOC_ARCH_EXYNOS4412 ||
>  	    pdata->type == SOC_ARCH_EXYNOS5250 ||
> +	    pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||

Don't you also need SOC_ARCH_EXYNOS5420 here?

>  	    pdata->type == SOC_ARCH_EXYNOS5440)
>  		data->soc = pdata->type;
>  	else {
> @@ -703,6 +742,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>  	return 0;
>  err_clk:
>  	clk_unprepare(data->clk);
> +err_clk_sec:
> +	if (!IS_ERR(data->clk_sec))
> +		clk_unprepare(data->clk_sec);
>  	return ret;
>  }
>  
> @@ -715,6 +757,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>  	exynos_unregister_thermal(data->reg_conf);
>  
>  	clk_unprepare(data->clk);
> +	if (!IS_ERR(data->clk_sec))
> +		clk_unprepare(data->clk_sec);
>  
>  	if (!IS_ERR(data->regulator))
>  		regulator_disable(data->regulator);
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 0d6b32f..60cce28 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -43,6 +43,7 @@ enum soc_type {
>  	SOC_ARCH_EXYNOS4210 = 1,
>  	SOC_ARCH_EXYNOS4412,
>  	SOC_ARCH_EXYNOS5250,
> +	SOC_ARCH_EXYNOS5420_TRIMINFO,

Here as well.

>  	SOC_ARCH_EXYNOS5440,
>  };
>  
[snip]
> +#define EXYNOS5420_TMU_DATA \
> +	__EXYNOS5420_TMU_DATA \
> +	.type = SOC_ARCH_EXYNOS5250, \
> +	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +			TMU_SUPPORT_EMUL_TIME)
> +
> +#define EXYNOS5420_TMU_DATA_SHARED \
> +	__EXYNOS5420_TMU_DATA \
> +	.type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
> +	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
> +			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
> +			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
> +
> +struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
> +	.tmu_data = {
> +		{ EXYNOS5420_TMU_DATA },
> +		{ EXYNOS5420_TMU_DATA },
> +		{ EXYNOS5420_TMU_DATA_SHARED },
> +		{ EXYNOS5420_TMU_DATA_SHARED },
> +		{ EXYNOS5420_TMU_DATA_SHARED },

Shouldn't this be inferred from compatible string?

If I understand this code correctly, you can now always use
EXYNOS5420_TMU_DATA for 5420-tmu compatible string and
EXYNOS5420_TMU_DATA_SHARED for 5420-tmu-ext-triminfo.

Best regards,
Tomasz

Re: [PATCH v11 1/4] thermal: samsung: replace inten_ bit fields with intclr_

[Tomasz Figa]

On Tuesday 10 of December 2013 12:11:28 Naveen Krishna Chatradhi wrote:
> This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
> with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
> Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only used
> to configure intclr related registers.
> 
> Description of H/W:
> The offset for the bits in the CLEAR register are not consistent across TMU
> modules in Exynso5250, 5420 and 5440.
> 
> On Exynos5250, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT registers and at an offset of
> 12 in INTCLEAR register.
> 
> On Exynos5420, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT and INTCLEAR registers.
> 
> On Exynos5440,
> the FALL_IRQEN bits are at an offset of 4
> and the RISE_IRQEN bits are at an offset of 0
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
> Changes since v10:
> None
> 
>  drivers/thermal/samsung/exynos_tmu.c      |    6 +++---
>  drivers/thermal/samsung/exynos_tmu.h      |   16 ++++++++--------
>  drivers/thermal/samsung/exynos_tmu_data.c |   18 +++++++++---------
>  drivers/thermal/samsung/exynos_tmu_data.h |    4 ++--
>  4 files changed, 22 insertions(+), 22 deletions(-)

Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

Re: [PATCH v11 2/4] thermal: samsung: change base_common to more meaningful base_second

[Tomasz Figa]

On Tuesday 10 of December 2013 12:11:56 Naveen Krishna Chatradhi wrote:
> On Exynos5440 and Exynos5420 there are registers common
> across the TMU channels.
> 
> To support that, we introduced a ADDRESS_MULTIPLE flag in the
> driver and the 2nd set of register base and size are provided
> in the "reg" property of the node.
> 
> As per Amit's suggestion, this patch changes the base_common
> to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
> Changes since v10:
> Documentation rephrased as per comments from Tomasz Figa
> 
>  .../devicetree/bindings/thermal/exynos-thermal.txt       |    4 ++--
>  drivers/thermal/samsung/exynos_tmu.c                     |   14 +++++++-------
>  drivers/thermal/samsung/exynos_tmu.h                     |    4 ++--
>  drivers/thermal/samsung/exynos_tmu_data.c                |    2 +-
>  4 files changed, 12 insertions(+), 12 deletions(-)

Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

Re: [PATCH v11 3/4] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Ch]

Hello Tomasz,


On 18 December 2013 21:20, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Naveen,
>
> On Tuesday 10 of December 2013 12:12:25 Naveen Krishna Chatradhi wrote:
>> Exynos5420 has 5 TMU channels, the TRIMINFO register is
>> misplaced for TMU channels 2, 3 and 4
>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>> TRIMINFO at 0x10068000 contains data for TMU channel 2
> [snip]
>> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> index a1aa602..a3e78c0 100644
>> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>> @@ -6,6 +6,9 @@
>>              "samsung,exynos4412-tmu"
>>              "samsung,exynos4210-tmu"
>>              "samsung,exynos5250-tmu"
>> +            "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
>> +            "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
>> +                     Exynos5420 (Must pass triminfo base and triminfo clock)
>
> Exact clock names must be specified in description of clock-names property.
Sure, will add them.
>
>>              "samsung,exynos5440-tmu"
>>  - interrupt-parent : The phandle for the interrupt controller
>>  - reg : Address range of the thermal registers. For soc's which has multiple
>> @@ -13,6 +16,16 @@
>>       interrupt related then 2 set of register has to supplied. First set
>>       belongs to register set of TMU instance and second set belongs to
>>       registers shared with the TMU instance.
>> +
>> +  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
>> +     channels 2, 3 and 4
>> +     Use "samsung,exynos5420-tmu-ext-triminfo" in cases, there is a misplaced
>> +     register, also provide clock to access that base.
>> +
>> +     TRIMINFO at 0x1006c000 contains data for TMU channel 3
>> +     TRIMINFO at 0x100a0000 contains data for TMU channel 4
>> +     TRIMINFO at 0x10068000 contains data for TMU channel 2
>> +
>>  - interrupts : Should contain interrupt for thermal system
>>  - clocks : The main clock for TMU device
>>  - clock-names : Thermal system clock name
>> @@ -43,6 +56,31 @@ Example 2):
>>               clock-names = "tmu_apbif";
>>       };
>>
>> +Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
>> +     tmu_cpu2: tmu@10068000 {
>> +             compatible = "samsung,exynos5420-tmu-ext-triminfo";
>> +             reg = <0x10068000 0x100>, <0x1006c000 0x4>;
>> +             interrupts = <0 184 0>;
>> +             clocks = <&clock 318>, <&clock 318>;
>> +             clock-names = "tmu_apbif", "tmu_triminfo_apbif";
>
> Here you have "tmu_triminfo_apbif" clock, but in the driver you call
> clk_get() with "tmu_apbif_triminfo".
My bad, will correct this
>
>> +     };
>> +
> [snip]
>>
>> +     data->clk_sec = devm_clk_get(&pdev->dev, "tmu_apbif_triminfo");
>
> Here you try to get "tmu_apbif_triminfo" clock, but in binding
> documentation you have "tmu_triminfo_apbif" in example.
My bad, will correct this
>
>> +     if (IS_ERR(data->clk_sec)) {
>> +             if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
>> +                     dev_err(&pdev->dev, "Failed to get triminfo clock\n");
>> +                     return PTR_ERR(data->clk_sec);
>> +             }
>> +     } else {
>> +             ret = clk_prepare(data->clk_sec);
>> +             if (ret) {
>> +                     dev_err(&pdev->dev, "Failed to get clock\n");
>> +                     return ret;
>> +             }
>> +     }
>> +
>>       ret = clk_prepare(data->clk);
>> -     if (ret)
>> -             return ret;
>> +     if (ret) {
>> +             dev_err(&pdev->dev, "Failed to get clock\n");
>> +             goto err_clk_sec;
>> +     }
>>
>>       if (pdata->type == SOC_ARCH_EXYNOS4210 ||
>>           pdata->type == SOC_ARCH_EXYNOS4412 ||
>>           pdata->type == SOC_ARCH_EXYNOS5250 ||
>> +         pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
TMU channel 0, 1 on Exynos5420 does not require a new pdata->type.
The are exactly similar to Exynos5250. Only the channels 2, 3 and 4
have the triminfo register misplaced.

Hence, just SOC_ARCH_EXYNOS5420_TRIMINFO should be enough

>
> Don't you also need SOC_ARCH_EXYNOS5420 here?
>
>>           pdata->type == SOC_ARCH_EXYNOS5440)
>>               data->soc = pdata->type;
>>       else {
>> @@ -703,6 +742,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
>>       return 0;
>>  err_clk:
>>       clk_unprepare(data->clk);
>> +err_clk_sec:
>> +     if (!IS_ERR(data->clk_sec))
>> +             clk_unprepare(data->clk_sec);
>>       return ret;
>>  }
>>
>> @@ -715,6 +757,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
>>       exynos_unregister_thermal(data->reg_conf);
>>
>>       clk_unprepare(data->clk);
>> +     if (!IS_ERR(data->clk_sec))
>> +             clk_unprepare(data->clk_sec);
>>
>>       if (!IS_ERR(data->regulator))
>>               regulator_disable(data->regulator);
>> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
>> index 0d6b32f..60cce28 100644
>> --- a/drivers/thermal/samsung/exynos_tmu.h
>> +++ b/drivers/thermal/samsung/exynos_tmu.h
>> @@ -43,6 +43,7 @@ enum soc_type {
>>       SOC_ARCH_EXYNOS4210 = 1,
>>       SOC_ARCH_EXYNOS4412,
>>       SOC_ARCH_EXYNOS5250,
>> +     SOC_ARCH_EXYNOS5420_TRIMINFO,
>
> Here as well.
>
>>       SOC_ARCH_EXYNOS5440,
>>  };
>>
> [snip]
>> +#define EXYNOS5420_TMU_DATA \
>> +     __EXYNOS5420_TMU_DATA \
>> +     .type = SOC_ARCH_EXYNOS5250, \
>> +     .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
>> +                     TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
>> +                     TMU_SUPPORT_EMUL_TIME)
>> +
>> +#define EXYNOS5420_TMU_DATA_SHARED \
>> +     __EXYNOS5420_TMU_DATA \
>> +     .type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
>> +     .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
>> +                     TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
>> +                     TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
>> +
>> +struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
>> +     .tmu_data = {
>> +             { EXYNOS5420_TMU_DATA },
>> +             { EXYNOS5420_TMU_DATA },
>> +             { EXYNOS5420_TMU_DATA_SHARED },
>> +             { EXYNOS5420_TMU_DATA_SHARED },
>> +             { EXYNOS5420_TMU_DATA_SHARED },
>
> Shouldn't this be inferred from compatible string?
>
> If I understand this code correctly, you can now always use
> EXYNOS5420_TMU_DATA for 5420-tmu compatible string and
> EXYNOS5420_TMU_DATA_SHARED for 5420-tmu-ext-triminfo.

Correct,
To avoid changes to exynos_get_driver_data() function the
exynos_get_driver_data struct is defined as above.

As function exynos_get_driver_data(struct platform_device *pdev, int id)
uses the id and matches the approriate structure pointer.

>
> Best regards,
> Tomasz
Thanks for your comments, will respin.
>



-- 
Shine bright,
(: Nav :)

[PATCH v12 1/4] thermal: samsung: replace inten_ bit fields with intclr_

[Naveen Krishna Chatradhi]

This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only used
to configure intclr related registers.

Description of H/W:
The offset for the bits in the CLEAR register are not consistent across TMU
modules in Exynso5250, 5420 and 5440.

On Exynos5250, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT registers and at an offset of
12 in INTCLEAR register.

On Exynos5420, the FALL interrupt related en, status and clear bits are
available at an offset of
16 in INTEN, INTSTAT and INTCLEAR registers.

On Exynos5440,
the FALL_IRQEN bits are at an offset of 4
and the RISE_IRQEN bits are at an offset of 0

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
---
Changes since v11:
Added Reviewed by Tomasz

Changes since v10:
None

 drivers/thermal/samsung/exynos_tmu.c      |    6 +++---
 drivers/thermal/samsung/exynos_tmu.h      |   16 ++++++++--------
 drivers/thermal/samsung/exynos_tmu_data.c |   18 +++++++++---------
 drivers/thermal/samsung/exynos_tmu_data.h |    4 ++--
 4 files changed, 22 insertions(+), 22 deletions(-)

diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 32f38b9..c493245 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -237,7 +237,7 @@ skip_calib_data:
 			writeb(pdata->trigger_levels[i], data->base +
 			reg->threshold_th0 + i * sizeof(reg->threshold_th0));
 
-		writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
+		writel(reg->intclr_rise_mask, data->base + reg->tmu_intclear);
 	} else {
 		/* Write temperature code for rising and falling threshold */
 		for (i = 0;
@@ -264,8 +264,8 @@ skip_calib_data:
 		writel(falling_threshold,
 				data->base + reg->threshold_th1);
 
-		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
-			(reg->inten_fall_mask << reg->inten_fall_shift),
+		writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |
+			(reg->intclr_fall_mask << reg->intclr_fall_shift),
 				data->base + reg->tmu_intclear);
 
 		/* if last threshold limit is also present */
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 3fb6554..980859a 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -122,10 +122,6 @@ enum soc_type {
  * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
  * @tmu_inten: register containing the different threshold interrupt
 	enable bits.
- * @inten_rise_shift: shift bits of all rising interrupt bits.
- * @inten_rise_mask: mask bits of all rising interrupt bits.
- * @inten_fall_shift: shift bits of all rising interrupt bits.
- * @inten_fall_mask: mask bits of all rising interrupt bits.
  * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
  * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
  * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
@@ -136,6 +132,10 @@ enum soc_type {
  * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
  * @tmu_intstat: Register containing the interrupt status values.
  * @tmu_intclear: Register for clearing the raised interrupt status.
+ * @intclr_fall_shift: shift bits for interrupt clear fall 0
+ * @intclr_rise_shift: shift bits of all rising interrupt bits.
+ * @intclr_rise_mask: mask bits of all rising interrupt bits.
+ * @intclr_fall_mask: mask bits of all rising interrupt bits.
  * @emul_con: TMU emulation controller register.
  * @emul_temp_shift: shift bits of emulation temperature.
  * @emul_time_shift: shift bits of emulation time.
@@ -191,10 +191,6 @@ struct exynos_tmu_registers {
 	u32	threshold_th3_l0_shift;
 
 	u32	tmu_inten;
-	u32	inten_rise_shift;
-	u32	inten_rise_mask;
-	u32	inten_fall_shift;
-	u32	inten_fall_mask;
 	u32	inten_rise0_shift;
 	u32	inten_rise1_shift;
 	u32	inten_rise2_shift;
@@ -207,6 +203,10 @@ struct exynos_tmu_registers {
 	u32	tmu_intstat;
 
 	u32	tmu_intclear;
+	u32	intclr_fall_shift;
+	u32	intclr_rise_shift;
+	u32	intclr_fall_mask;
+	u32	intclr_rise_mask;
 
 	u32	emul_con;
 	u32	emul_temp_shift;
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 073c292..7cdb04e 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -40,13 +40,13 @@ static const struct exynos_tmu_registers exynos4210_tmu_registers = {
 	.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
 	.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
 	.tmu_inten = EXYNOS_TMU_REG_INTEN,
-	.inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
 	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
 	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
 };
 
 struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
@@ -112,10 +112,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
 	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
 	.tmu_inten = EXYNOS_TMU_REG_INTEN,
-	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
-	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
-	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
-	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
 	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
@@ -123,6 +119,10 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
 	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
 	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
+	.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
 	.emul_con = EXYNOS_EMUL_CON,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
 	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
@@ -217,10 +217,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
 	.threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
 	.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
-	.inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
-	.inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
-	.inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
-	.inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
 	.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
 	.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
 	.inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
@@ -228,6 +224,10 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
 	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
 	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
+	.intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
+	.intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
+	.intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
+	.intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
 	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
 	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
 	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index a1ea19d..d9495a4 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -69,9 +69,10 @@
 #define EXYNOS_TMU_RISE_INT_MASK	0x111
 #define EXYNOS_TMU_RISE_INT_SHIFT	0
 #define EXYNOS_TMU_FALL_INT_MASK	0x111
-#define EXYNOS_TMU_FALL_INT_SHIFT	12
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
+#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
+#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
@@ -119,7 +120,6 @@
 #define EXYNOS5440_TMU_RISE_INT_MASK		0xf
 #define EXYNOS5440_TMU_RISE_INT_SHIFT		0
 #define EXYNOS5440_TMU_FALL_INT_MASK		0xf
-#define EXYNOS5440_TMU_FALL_INT_SHIFT		4
 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT	0
 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT	1
 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT	2
-- 
1.7.10.4

[PATCH v12 2/4] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Chatradhi]

On Exynos5440 and Exynos5420 there are registers common
across the TMU channels.

To support that, we introduced a ADDRESS_MULTIPLE flag in the
driver and the 2nd set of register base and size are provided
in the "reg" property of the node.

As per Amit's suggestion, this patch changes the base_common
to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
---
Changes since v11:
Added Reviewed by Tomasz

Changes since v10:
Documentation rephrased as per comments from Tomasz Figa

 .../devicetree/bindings/thermal/exynos-thermal.txt       |    4 ++--
 drivers/thermal/samsung/exynos_tmu.c                     |   14 +++++++-------
 drivers/thermal/samsung/exynos_tmu.h                     |    4 ++--
 drivers/thermal/samsung/exynos_tmu_data.c                |    2 +-
 4 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index 284f530..a1aa602 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -11,8 +11,8 @@
 - reg : Address range of the thermal registers. For soc's which has multiple
 	instances of TMU and some registers are shared across all TMU's like
 	interrupt related then 2 set of register has to supplied. First set
-	belongs	to each instance of TMU and second set belongs to common TMU
-	registers.
+	belongs	to register set of TMU instance and second set belongs to
+	registers shared with the TMU instance.
 - interrupts : Should contain interrupt for thermal system
 - clocks : The main clock for TMU device
 - clock-names : Thermal system clock name
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index c493245..bbd0fc3 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -41,7 +41,7 @@
  * @id: identifier of the one instance of the TMU controller.
  * @pdata: pointer to the tmu platform/configuration data
  * @base: base address of the single instance of the TMU controller.
- * @base_common: base address of the common registers of the TMU controller.
+ * @base_second: base address of the common registers of the TMU controller.
  * @irq: irq number of the TMU controller.
  * @soc: id of the SOC type.
  * @irq_work: pointer to the irq work structure.
@@ -56,7 +56,7 @@ struct exynos_tmu_data {
 	int id;
 	struct exynos_tmu_platform_data *pdata;
 	void __iomem *base;
-	void __iomem *base_common;
+	void __iomem *base_second;
 	int irq;
 	enum soc_type soc;
 	struct work_struct irq_work;
@@ -297,7 +297,7 @@ skip_calib_data:
 	}
 	/*Clear the PMIN in the common TMU register*/
 	if (reg->tmu_pmin && !data->id)
-		writel(0, data->base_common + reg->tmu_pmin);
+		writel(0, data->base_second + reg->tmu_pmin);
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
@@ -454,7 +454,7 @@ static void exynos_tmu_work(struct work_struct *work)
 
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
-		val_type = readl(data->base_common + reg->tmu_irqstatus);
+		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
@@ -579,7 +579,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 	 * Check if the TMU shares some registers and then try to map the
 	 * memory of common registers.
 	 */
-	if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
+	if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
 		return 0;
 
 	if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
@@ -587,9 +587,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	data->base_common = devm_ioremap(&pdev->dev, res.start,
+	data->base_second = devm_ioremap(&pdev->dev, res.start,
 					resource_size(&res));
-	if (!data->base_common) {
+	if (!data->base_second) {
 		dev_err(&pdev->dev, "Failed to ioremap memory\n");
 		return -ENOMEM;
 	}
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 980859a..0d6b32f 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -60,7 +60,7 @@ enum soc_type {
  *			state(active/idle) can be checked.
  * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
  *			sample time.
- * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
+ * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
  *			sensors shares some common registers.
  * TMU_SUPPORT - macro to compare the above features with the supplied.
  */
@@ -70,7 +70,7 @@ enum soc_type {
 #define TMU_SUPPORT_FALLING_TRIP		BIT(3)
 #define TMU_SUPPORT_READY_STATUS		BIT(4)
 #define TMU_SUPPORT_EMUL_TIME			BIT(5)
-#define TMU_SUPPORT_SHARED_MEMORY		BIT(6)
+#define TMU_SUPPORT_ADDRESS_MULTIPLE		BIT(6)
 
 #define TMU_SUPPORTS(a, b)	(a->features & TMU_SUPPORT_ ## b)
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 7cdb04e..1d27069 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -255,7 +255,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.type = SOC_ARCH_EXYNOS5440, \
 	.registers = &exynos5440_tmu_registers, \
 	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
-			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
+			TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
 
 struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
 	.tmu_data = {
-- 
1.7.10.4

[PATCH v12 3/4] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Chatradhi]

Exynos5420 has 5 TMU channels, the TRIMINFO register is
misplaced for TMU channels 2, 3 and 4
TRIMINFO at 0x1006c000 contains data for TMU channel 3
TRIMINFO at 0x100a0000 contains data for TMU channel 4
TRIMINFO at 0x10068000 contains data for TMU channel 2

This patch
1 Adds the neccessary register changes and arch information
   to support Exynos5420 SoCs.
2. Handles the gate clock for misplaced TRIMINFO register
3. Updates the Documentation at
   Documentation/devicetree/bindings/thermal/exynos-thermal.txt

Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
---
Changes since v11:
1. Added description for clocks in the Documentation
2. corrected the clock name in clk_get() function as per description

Changes since v10:
1. using renamed compatible "samsung,exynos5420-tmu-ext-triminfo"
   and passing same clock as triminfo_apbif clock for channel 2
2. removed the "exynos5420-tmu-triminfo-clk" compatible
 .../devicetree/bindings/thermal/exynos-thermal.txt |   45 ++++++++-
 drivers/thermal/samsung/exynos_tmu.c               |   52 +++++++++-
 drivers/thermal/samsung/exynos_tmu.h               |    1 +
 drivers/thermal/samsung/exynos_tmu_data.c          |   99 ++++++++++++++++++++
 drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
 5 files changed, 200 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
index a1aa602..79c4055 100644
--- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
@@ -6,6 +6,9 @@
 	       "samsung,exynos4412-tmu"
 	       "samsung,exynos4210-tmu"
 	       "samsung,exynos5250-tmu"
+	       "samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
+	       "samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
+			Exynos5420 (Must pass triminfo base and triminfo clock)
 	       "samsung,exynos5440-tmu"
 - interrupt-parent : The phandle for the interrupt controller
 - reg : Address range of the thermal registers. For soc's which has multiple
@@ -13,9 +16,24 @@
 	interrupt related then 2 set of register has to supplied. First set
 	belongs	to register set of TMU instance and second set belongs to
 	registers shared with the TMU instance.
+
+  NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
+	channels 2, 3 and 4
+	Use "samsung,exynos5420-tmu-ext-triminfo" in cases, there is a misplaced
+	register, also provide clock to access that base.
+
+	TRIMINFO at 0x1006c000 contains data for TMU channel 3
+	TRIMINFO at 0x100a0000 contains data for TMU channel 4
+	TRIMINFO at 0x10068000 contains data for TMU channel 2
+
 - interrupts : Should contain interrupt for thermal system
-- clocks : The main clock for TMU device
+- clocks : The main clocks for TMU device
+	-- 1. operational clock for TMU channel
+	-- 2. optional clock to access the shared registers of TMU channel
 - clock-names : Thermal system clock name
+	-- "tmu_apbif" operational clock for current TMU channel
+	-- "tmu_triminfo_apbif" clock to access the shared triminfo register
+		for current TMU channel
 - vtmu-supply: This entry is optional and provides the regulator node supplying
 		voltage to TMU. If needed this entry can be placed inside
 		board/platform specific dts file.
@@ -43,6 +61,31 @@ Example 2):
 		clock-names = "tmu_apbif";
 	};
 
+Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
+	tmu_cpu2: tmu@10068000 {
+		compatible = "samsung,exynos5420-tmu-ext-triminfo";
+		reg = <0x10068000 0x100>, <0x1006c000 0x4>;
+		interrupts = <0 184 0>;
+		clocks = <&clock 318>, <&clock 318>;
+		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+	};
+
+	tmu_cpu3: tmu@1006c000 {
+		compatible = "samsung,exynos5420-tmu-ext-triminfo";
+		reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
+		interrupts = <0 185 0>;
+		clocks = <&clock 318>, <&clock 319>;
+		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+	};
+
+	tmu_gpu: tmu@100a0000 {
+		compatible = "samsung,exynos5420-tmu-ext-triminfo";
+		reg = <0x100a0000 0x100>, <0x10068000 0x4>;
+		interrupts = <0 215 0>;
+		clocks = <&clock 319>, <&clock 318>;
+		clock-names = "tmu_apbif", "tmu_triminfo_apbif";
+	};
+
 Note: For multi-instance tmu each instance should have an alias correctly
 numbered in "aliases" node.
 
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index bbd0fc3..3246ace 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -47,6 +47,7 @@
  * @irq_work: pointer to the irq work structure.
  * @lock: lock to implement synchronization.
  * @clk: pointer to the clock structure.
+ * @clk_sec: pointer to the clock structure for accessing the base_second.
  * @temp_error1: fused value of the first point trim.
  * @temp_error2: fused value of the second point trim.
  * @regulator: pointer to the TMU regulator structure.
@@ -61,7 +62,7 @@ struct exynos_tmu_data {
 	enum soc_type soc;
 	struct work_struct irq_work;
 	struct mutex lock;
-	struct clk *clk;
+	struct clk *clk, *clk_sec;
 	u8 temp_error1, temp_error2;
 	struct regulator *regulator;
 	struct thermal_sensor_conf *reg_conf;
@@ -152,6 +153,8 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 
 	mutex_lock(&data->lock);
 	clk_enable(data->clk);
+	if (!IS_ERR(data->clk_sec))
+		clk_enable(data->clk_sec);
 
 	if (TMU_SUPPORTS(pdata, READY_STATUS)) {
 		status = readb(data->base + reg->tmu_status);
@@ -186,7 +189,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
 			EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
 		}
 	} else {
-		trim_info = readl(data->base + reg->triminfo_data);
+		/* On exynos5420 the triminfo register is in the shared space */
+		if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
+			trim_info = readl(data->base_second +
+							reg->triminfo_data);
+		else
+			trim_info = readl(data->base + reg->triminfo_data);
 	}
 	data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
 	data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
@@ -301,6 +309,8 @@ skip_calib_data:
 out:
 	clk_disable(data->clk);
 	mutex_unlock(&data->lock);
+	if (!IS_ERR(data->clk_sec))
+		clk_disable(data->clk_sec);
 
 	return ret;
 }
@@ -452,12 +462,16 @@ static void exynos_tmu_work(struct work_struct *work)
 	const struct exynos_tmu_registers *reg = pdata->registers;
 	unsigned int val_irq, val_type;
 
+	if (!IS_ERR(data->clk_sec))
+		clk_enable(data->clk_sec);
 	/* Find which sensor generated this interrupt */
 	if (reg->tmu_irqstatus) {
 		val_type = readl(data->base_second + reg->tmu_irqstatus);
 		if (!((val_type >> data->id) & 0x1))
 			goto out;
 	}
+	if (!IS_ERR(data->clk_sec))
+		clk_disable(data->clk_sec);
 
 	exynos_report_trigger(data->reg_conf);
 	mutex_lock(&data->lock);
@@ -498,6 +512,14 @@ static const struct of_device_id exynos_tmu_match[] = {
 		.data = (void *)EXYNOS5250_TMU_DRV_DATA,
 	},
 	{
+		.compatible = "samsung,exynos5420-tmu",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
+		.compatible = "samsung,exynos5420-tmu-ext-triminfo",
+		.data = (void *)EXYNOS5420_TMU_DRV_DATA,
+	},
+	{
 		.compatible = "samsung,exynos5440-tmu",
 		.data = (void *)EXYNOS5440_TMU_DRV_DATA,
 	},
@@ -628,13 +650,30 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 		return  PTR_ERR(data->clk);
 	}
 
+	data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
+	if (IS_ERR(data->clk_sec)) {
+		if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
+			dev_err(&pdev->dev, "Failed to get triminfo clock\n");
+			return PTR_ERR(data->clk_sec);
+		}
+	} else {
+		ret = clk_prepare(data->clk_sec);
+		if (ret) {
+			dev_err(&pdev->dev, "Failed to get clock\n");
+			return ret;
+		}
+	}
+
 	ret = clk_prepare(data->clk);
-	if (ret)
-		return ret;
+	if (ret) {
+		dev_err(&pdev->dev, "Failed to get clock\n");
+		goto err_clk_sec;
+	}
 
 	if (pdata->type == SOC_ARCH_EXYNOS4210 ||
 	    pdata->type == SOC_ARCH_EXYNOS4412 ||
 	    pdata->type == SOC_ARCH_EXYNOS5250 ||
+	    pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
 	    pdata->type == SOC_ARCH_EXYNOS5440)
 		data->soc = pdata->type;
 	else {
@@ -703,6 +742,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
 	return 0;
 err_clk:
 	clk_unprepare(data->clk);
+err_clk_sec:
+	if (!IS_ERR(data->clk_sec))
+		clk_unprepare(data->clk_sec);
 	return ret;
 }
 
@@ -715,6 +757,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
 	exynos_unregister_thermal(data->reg_conf);
 
 	clk_unprepare(data->clk);
+	if (!IS_ERR(data->clk_sec))
+		clk_unprepare(data->clk_sec);
 
 	if (!IS_ERR(data->regulator))
 		regulator_disable(data->regulator);
diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
index 0d6b32f..60cce28 100644
--- a/drivers/thermal/samsung/exynos_tmu.h
+++ b/drivers/thermal/samsung/exynos_tmu.h
@@ -43,6 +43,7 @@ enum soc_type {
 	SOC_ARCH_EXYNOS4210 = 1,
 	SOC_ARCH_EXYNOS4412,
 	SOC_ARCH_EXYNOS5250,
+	SOC_ARCH_EXYNOS5420_TRIMINFO,
 	SOC_ARCH_EXYNOS5440,
 };
 
diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
index 1d27069..2670cbe 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.c
+++ b/drivers/thermal/samsung/exynos_tmu_data.c
@@ -194,6 +194,105 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
 };
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+static const struct exynos_tmu_registers exynos5420_tmu_registers = {
+	.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
+	.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
+	.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
+	.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
+	.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
+	.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
+	.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
+	.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
+	.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
+	.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
+	.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
+	.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
+	.tmu_status = EXYNOS_TMU_REG_STATUS,
+	.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
+	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
+	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
+	.tmu_inten = EXYNOS_TMU_REG_INTEN,
+	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
+	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
+	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
+	/* INTEN_RISE3 Not availble in exynos5420 */
+	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
+	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
+	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
+	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
+	.intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
+	.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
+	.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
+	.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
+	.emul_con = EXYNOS_EMUL_CON,
+	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
+	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
+	.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
+};
+
+#define __EXYNOS5420_TMU_DATA	\
+	.threshold_falling = 10, \
+	.trigger_levels[0] = 85, \
+	.trigger_levels[1] = 103, \
+	.trigger_levels[2] = 110, \
+	.trigger_levels[3] = 120, \
+	.trigger_enable[0] = true, \
+	.trigger_enable[1] = true, \
+	.trigger_enable[2] = true, \
+	.trigger_enable[3] = false, \
+	.trigger_type[0] = THROTTLE_ACTIVE, \
+	.trigger_type[1] = THROTTLE_ACTIVE, \
+	.trigger_type[2] = SW_TRIP, \
+	.trigger_type[3] = HW_TRIP, \
+	.max_trigger_level = 4, \
+	.gain = 8, \
+	.reference_voltage = 16, \
+	.noise_cancel_mode = 4, \
+	.cal_type = TYPE_ONE_POINT_TRIMMING, \
+	.efuse_value = 55, \
+	.min_efuse_value = 40, \
+	.max_efuse_value = 100, \
+	.first_point_trim = 25, \
+	.second_point_trim = 85, \
+	.default_temp_offset = 50, \
+	.freq_tab[0] = { \
+		.freq_clip_max = 800 * 1000, \
+		.temp_level = 85, \
+	}, \
+	.freq_tab[1] = { \
+		.freq_clip_max = 200 * 1000, \
+		.temp_level = 103, \
+	}, \
+	.freq_tab_count = 2, \
+	.registers = &exynos5420_tmu_registers, \
+
+#define EXYNOS5420_TMU_DATA \
+	__EXYNOS5420_TMU_DATA \
+	.type = SOC_ARCH_EXYNOS5250, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME)
+
+#define EXYNOS5420_TMU_DATA_SHARED \
+	__EXYNOS5420_TMU_DATA \
+	.type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
+	.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
+			TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
+			TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
+
+struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
+	.tmu_data = {
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+		{ EXYNOS5420_TMU_DATA_SHARED },
+	},
+	.tmu_count = 5,
+};
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 static const struct exynos_tmu_registers exynos5440_tmu_registers = {
 	.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
index d9495a4..41f06dc 100644
--- a/drivers/thermal/samsung/exynos_tmu_data.h
+++ b/drivers/thermal/samsung/exynos_tmu_data.h
@@ -72,6 +72,7 @@
 #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
 #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
 #define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
+#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT	16
 #define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
 #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
 #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
@@ -156,6 +157,13 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
 #define EXYNOS5250_TMU_DRV_DATA (NULL)
 #endif
 
+#if defined(CONFIG_SOC_EXYNOS5420)
+extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
+#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
+#else
+#define EXYNOS5420_TMU_DRV_DATA (NULL)
+#endif
+
 #if defined(CONFIG_SOC_EXYNOS5440)
 extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
 #define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
-- 
1.7.10.4

Re: [PATCH v12 3/4] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Tomasz Figa]

On Thursday 19 of December 2013 11:36:31 Naveen Krishna Chatradhi wrote:
> Exynos5420 has 5 TMU channels, the TRIMINFO register is
> misplaced for TMU channels 2, 3 and 4
> TRIMINFO at 0x1006c000 contains data for TMU channel 3
> TRIMINFO at 0x100a0000 contains data for TMU channel 4
> TRIMINFO at 0x10068000 contains data for TMU channel 2
> 
> This patch
> 1 Adds the neccessary register changes and arch information
>    to support Exynos5420 SoCs.
> 2. Handles the gate clock for misplaced TRIMINFO register
> 3. Updates the Documentation at
>    Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> ---
> Changes since v11:
> 1. Added description for clocks in the Documentation
> 2. corrected the clock name in clk_get() function as per description
> 
> Changes since v10:
> 1. using renamed compatible "samsung,exynos5420-tmu-ext-triminfo"
>    and passing same clock as triminfo_apbif clock for channel 2
> 2. removed the "exynos5420-tmu-triminfo-clk" compatible
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   45 ++++++++-
>  drivers/thermal/samsung/exynos_tmu.c               |   52 +++++++++-
>  drivers/thermal/samsung/exynos_tmu.h               |    1 +
>  drivers/thermal/samsung/exynos_tmu_data.c          |   99 ++++++++++++++++++++
>  drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
>  5 files changed, 200 insertions(+), 5 deletions(-)

Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Best regards,
Tomasz

Re: [PATCH v12 1/4] thermal: samsung: replace inten_ bit fields with intclr_

[Zhang Rui]

On Thu, 2013-12-19 at 11:35 +0530, Naveen Krishna Chatradhi wrote:
> This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
> with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
> Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only used
> to configure intclr related registers.
> 
> Description of H/W:
> The offset for the bits in the CLEAR register are not consistent across TMU
> modules in Exynso5250, 5420 and 5440.
> 
> On Exynos5250, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT registers and at an offset of
> 12 in INTCLEAR register.
> 
> On Exynos5420, the FALL interrupt related en, status and clear bits are
> available at an offset of
> 16 in INTEN, INTSTAT and INTCLEAR registers.
> 
> On Exynos5440,
> the FALL_IRQEN bits are at an offset of 4
> and the RISE_IRQEN bits are at an offset of 0
> 
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>

Eduardo,

what do you think of this patch set?

thanks,
rui
> ---
> Changes since v11:
> Added Reviewed by Tomasz
> 
> Changes since v10:
> None
> 
>  drivers/thermal/samsung/exynos_tmu.c      |    6 +++---
>  drivers/thermal/samsung/exynos_tmu.h      |   16 ++++++++--------
>  drivers/thermal/samsung/exynos_tmu_data.c |   18 +++++++++---------
>  drivers/thermal/samsung/exynos_tmu_data.h |    4 ++--
>  4 files changed, 22 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index 32f38b9..c493245 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -237,7 +237,7 @@ skip_calib_data:
>  			writeb(pdata->trigger_levels[i], data->base +
>  			reg->threshold_th0 + i * sizeof(reg->threshold_th0));
>  
> -		writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
> +		writel(reg->intclr_rise_mask, data->base + reg->tmu_intclear);
>  	} else {
>  		/* Write temperature code for rising and falling threshold */
>  		for (i = 0;
> @@ -264,8 +264,8 @@ skip_calib_data:
>  		writel(falling_threshold,
>  				data->base + reg->threshold_th1);
>  
> -		writel((reg->inten_rise_mask << reg->inten_rise_shift) |
> -			(reg->inten_fall_mask << reg->inten_fall_shift),
> +		writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |
> +			(reg->intclr_fall_mask << reg->intclr_fall_shift),
>  				data->base + reg->tmu_intclear);
>  
>  		/* if last threshold limit is also present */
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 3fb6554..980859a 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -122,10 +122,6 @@ enum soc_type {
>   * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
>   * @tmu_inten: register containing the different threshold interrupt
>  	enable bits.
> - * @inten_rise_shift: shift bits of all rising interrupt bits.
> - * @inten_rise_mask: mask bits of all rising interrupt bits.
> - * @inten_fall_shift: shift bits of all rising interrupt bits.
> - * @inten_fall_mask: mask bits of all rising interrupt bits.
>   * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
>   * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
>   * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
> @@ -136,6 +132,10 @@ enum soc_type {
>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
>   * @tmu_intstat: Register containing the interrupt status values.
>   * @tmu_intclear: Register for clearing the raised interrupt status.
> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
> + * @intclr_rise_shift: shift bits of all rising interrupt bits.
> + * @intclr_rise_mask: mask bits of all rising interrupt bits.
> + * @intclr_fall_mask: mask bits of all rising interrupt bits.
>   * @emul_con: TMU emulation controller register.
>   * @emul_temp_shift: shift bits of emulation temperature.
>   * @emul_time_shift: shift bits of emulation time.
> @@ -191,10 +191,6 @@ struct exynos_tmu_registers {
>  	u32	threshold_th3_l0_shift;
>  
>  	u32	tmu_inten;
> -	u32	inten_rise_shift;
> -	u32	inten_rise_mask;
> -	u32	inten_fall_shift;
> -	u32	inten_fall_mask;
>  	u32	inten_rise0_shift;
>  	u32	inten_rise1_shift;
>  	u32	inten_rise2_shift;
> @@ -207,6 +203,10 @@ struct exynos_tmu_registers {
>  	u32	tmu_intstat;
>  
>  	u32	tmu_intclear;
> +	u32	intclr_fall_shift;
> +	u32	intclr_rise_shift;
> +	u32	intclr_fall_mask;
> +	u32	intclr_rise_mask;
>  
>  	u32	emul_con;
>  	u32	emul_temp_shift;
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 073c292..7cdb04e 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -40,13 +40,13 @@ static const struct exynos_tmu_registers exynos4210_tmu_registers = {
>  	.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
>  	.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
>  	.tmu_inten = EXYNOS_TMU_REG_INTEN,
> -	.inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
>  	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
>  	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
>  	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
>  	.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
>  	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>  	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +	.intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
>  };
>  
>  struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
> @@ -112,10 +112,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
>  	.threshold_th0 = EXYNOS_THD_TEMP_RISE,
>  	.threshold_th1 = EXYNOS_THD_TEMP_FALL,
>  	.tmu_inten = EXYNOS_TMU_REG_INTEN,
> -	.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> -	.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> -	.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
> -	.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
>  	.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
>  	.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
>  	.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
> @@ -123,6 +119,10 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
>  	.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>  	.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>  	.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> +	.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
> +	.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> +	.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> +	.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
>  	.emul_con = EXYNOS_EMUL_CON,
>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>  	.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> @@ -217,10 +217,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>  	.threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
>  	.threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
>  	.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
> -	.inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
> -	.inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
> -	.inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
> -	.inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
>  	.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
>  	.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
>  	.inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
> @@ -228,6 +224,10 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>  	.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
>  	.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
>  	.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
> +	.intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
> +	.intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
> +	.intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
> +	.intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
>  	.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
>  	.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
>  	.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> index a1ea19d..d9495a4 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> @@ -69,9 +69,10 @@
>  #define EXYNOS_TMU_RISE_INT_MASK	0x111
>  #define EXYNOS_TMU_RISE_INT_SHIFT	0
>  #define EXYNOS_TMU_FALL_INT_MASK	0x111
> -#define EXYNOS_TMU_FALL_INT_SHIFT	12
>  #define EXYNOS_TMU_CLEAR_RISE_INT	0x111
>  #define EXYNOS_TMU_CLEAR_FALL_INT	(0x111 << 12)
> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT	12
> +#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT	4
>  #define EXYNOS_TMU_TRIP_MODE_SHIFT	13
>  #define EXYNOS_TMU_TRIP_MODE_MASK	0x7
>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT	12
> @@ -119,7 +120,6 @@
>  #define EXYNOS5440_TMU_RISE_INT_MASK		0xf
>  #define EXYNOS5440_TMU_RISE_INT_SHIFT		0
>  #define EXYNOS5440_TMU_FALL_INT_MASK		0xf
> -#define EXYNOS5440_TMU_FALL_INT_SHIFT		4
>  #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT	0
>  #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT	1
>  #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT	2

Re: [PATCH v12 1/4] thermal: samsung: replace inten_ bit fields with intclr_

[Naveen Krishna Ch]

Hello All,

On 2 January 2014 08:03, Zhang Rui <rui.zhang@intel.com> wrote:
> On Thu, 2013-12-19 at 11:35 +0530, Naveen Krishna Chatradhi wrote:
>> This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
>> with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
>> Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only used
>> to configure intclr related registers.
>>
>> Description of H/W:
>> The offset for the bits in the CLEAR register are not consistent across TMU
>> modules in Exynso5250, 5420 and 5440.
>>
>> On Exynos5250, the FALL interrupt related en, status and clear bits are
>> available at an offset of
>> 16 in INTEN, INTSTAT registers and at an offset of
>> 12 in INTCLEAR register.
>>
>> On Exynos5420, the FALL interrupt related en, status and clear bits are
>> available at an offset of
>> 16 in INTEN, INTSTAT and INTCLEAR registers.
>>
>> On Exynos5440,
>> the FALL_IRQEN bits are at an offset of 4
>> and the RISE_IRQEN bits are at an offset of 0
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
>> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
>
> Eduardo,
>
> what do you think of this patch set?
>
> thanks,
> rui
>> ---
>> Changes since v11:
>> Added Reviewed by Tomasz
>>
>> Changes since v10:
>> None
>>
>>  drivers/thermal/samsung/exynos_tmu.c      |    6 +++---
>>  drivers/thermal/samsung/exynos_tmu.h      |   16 ++++++++--------
>>  drivers/thermal/samsung/exynos_tmu_data.c |   18 +++++++++---------
>>  drivers/thermal/samsung/exynos_tmu_data.h |    4 ++--
>>  4 files changed, 22 insertions(+), 22 deletions(-)
>>
>> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
>> index 32f38b9..c493245 100644
>> --- a/drivers/thermal/samsung/exynos_tmu.c
>> +++ b/drivers/thermal/samsung/exynos_tmu.c
>> @@ -237,7 +237,7 @@ skip_calib_data:
>>                       writeb(pdata->trigger_levels[i], data->base +
>>                       reg->threshold_th0 + i * sizeof(reg->threshold_th0));
>>
>> -             writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
>> +             writel(reg->intclr_rise_mask, data->base + reg->tmu_intclear);
>>       } else {
>>               /* Write temperature code for rising and falling threshold */
>>               for (i = 0;
>> @@ -264,8 +264,8 @@ skip_calib_data:
>>               writel(falling_threshold,
>>                               data->base + reg->threshold_th1);
>>
>> -             writel((reg->inten_rise_mask << reg->inten_rise_shift) |
>> -                     (reg->inten_fall_mask << reg->inten_fall_shift),
>> +             writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |
>> +                     (reg->intclr_fall_mask << reg->intclr_fall_shift),
>>                               data->base + reg->tmu_intclear);
>>
>>               /* if last threshold limit is also present */
>> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
>> index 3fb6554..980859a 100644
>> --- a/drivers/thermal/samsung/exynos_tmu.h
>> +++ b/drivers/thermal/samsung/exynos_tmu.h
>> @@ -122,10 +122,6 @@ enum soc_type {
>>   * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
>>   * @tmu_inten: register containing the different threshold interrupt
>>       enable bits.
>> - * @inten_rise_shift: shift bits of all rising interrupt bits.
>> - * @inten_rise_mask: mask bits of all rising interrupt bits.
>> - * @inten_fall_shift: shift bits of all rising interrupt bits.
>> - * @inten_fall_mask: mask bits of all rising interrupt bits.
>>   * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
>>   * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
>>   * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
>> @@ -136,6 +132,10 @@ enum soc_type {
>>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
>>   * @tmu_intstat: Register containing the interrupt status values.
>>   * @tmu_intclear: Register for clearing the raised interrupt status.
>> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
>> + * @intclr_rise_shift: shift bits of all rising interrupt bits.
>> + * @intclr_rise_mask: mask bits of all rising interrupt bits.
>> + * @intclr_fall_mask: mask bits of all rising interrupt bits.
>>   * @emul_con: TMU emulation controller register.
>>   * @emul_temp_shift: shift bits of emulation temperature.
>>   * @emul_time_shift: shift bits of emulation time.
>> @@ -191,10 +191,6 @@ struct exynos_tmu_registers {
>>       u32     threshold_th3_l0_shift;
>>
>>       u32     tmu_inten;
>> -     u32     inten_rise_shift;
>> -     u32     inten_rise_mask;
>> -     u32     inten_fall_shift;
>> -     u32     inten_fall_mask;
>>       u32     inten_rise0_shift;
>>       u32     inten_rise1_shift;
>>       u32     inten_rise2_shift;
>> @@ -207,6 +203,10 @@ struct exynos_tmu_registers {
>>       u32     tmu_intstat;
>>
>>       u32     tmu_intclear;
>> +     u32     intclr_fall_shift;
>> +     u32     intclr_rise_shift;
>> +     u32     intclr_fall_mask;
>> +     u32     intclr_rise_mask;
>>
>>       u32     emul_con;
>>       u32     emul_temp_shift;
>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
>> index 073c292..7cdb04e 100644
>> --- a/drivers/thermal/samsung/exynos_tmu_data.c
>> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
>> @@ -40,13 +40,13 @@ static const struct exynos_tmu_registers exynos4210_tmu_registers = {
>>       .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
>>       .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
>>       .tmu_inten = EXYNOS_TMU_REG_INTEN,
>> -     .inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
>>       .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
>>       .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
>>       .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
>>       .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
>>       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>>       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
>> +     .intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
>>  };
>>
>>  struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
>> @@ -112,10 +112,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
>>       .threshold_th0 = EXYNOS_THD_TEMP_RISE,
>>       .threshold_th1 = EXYNOS_THD_TEMP_FALL,
>>       .tmu_inten = EXYNOS_TMU_REG_INTEN,
>> -     .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
>> -     .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
>> -     .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
>> -     .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
>>       .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
>>       .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
>>       .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
>> @@ -123,6 +119,10 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
>>       .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
>>       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
>>       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
>> +     .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
>> +     .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
>> +     .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
>> +     .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
>>       .emul_con = EXYNOS_EMUL_CON,
>>       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>>       .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
>> @@ -217,10 +217,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>>       .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
>>       .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
>>       .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
>> -     .inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
>> -     .inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
>> -     .inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
>> -     .inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
>>       .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
>>       .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
>>       .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
>> @@ -228,6 +224,10 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>>       .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
>>       .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
>>       .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
>> +     .intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
>> +     .intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
>> +     .intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
>> +     .intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
>>       .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
>>       .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
>>       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
>> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
>> index a1ea19d..d9495a4 100644
>> --- a/drivers/thermal/samsung/exynos_tmu_data.h
>> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
>> @@ -69,9 +69,10 @@
>>  #define EXYNOS_TMU_RISE_INT_MASK     0x111
>>  #define EXYNOS_TMU_RISE_INT_SHIFT    0
>>  #define EXYNOS_TMU_FALL_INT_MASK     0x111
>> -#define EXYNOS_TMU_FALL_INT_SHIFT    12
>>  #define EXYNOS_TMU_CLEAR_RISE_INT    0x111
>>  #define EXYNOS_TMU_CLEAR_FALL_INT    (0x111 << 12)
>> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT      12
>> +#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT  4
>>  #define EXYNOS_TMU_TRIP_MODE_SHIFT   13
>>  #define EXYNOS_TMU_TRIP_MODE_MASK    0x7
>>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT       12
>> @@ -119,7 +120,6 @@
>>  #define EXYNOS5440_TMU_RISE_INT_MASK         0xf
>>  #define EXYNOS5440_TMU_RISE_INT_SHIFT                0
>>  #define EXYNOS5440_TMU_FALL_INT_MASK         0xf
>> -#define EXYNOS5440_TMU_FALL_INT_SHIFT                4
>>  #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT     0
>>  #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT     1
>>  #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT     2
>
>
Ping.



-- 
Shine bright,
(: Nav :)

Re: [PATCH v12 3/4] thermal: samsung: Add TMU support for Exynos5420 SoCs

[Naveen Krishna Ch]

Hello All,

On 19 December 2013 17:04, Tomasz Figa <t.figa@samsung.com> wrote:
> On Thursday 19 of December 2013 11:36:31 Naveen Krishna Chatradhi wrote:
>> Exynos5420 has 5 TMU channels, the TRIMINFO register is
>> misplaced for TMU channels 2, 3 and 4
>> TRIMINFO at 0x1006c000 contains data for TMU channel 3
>> TRIMINFO at 0x100a0000 contains data for TMU channel 4
>> TRIMINFO at 0x10068000 contains data for TMU channel 2
>>
>> This patch
>> 1 Adds the neccessary register changes and arch information
>>    to support Exynos5420 SoCs.
>> 2. Handles the gate clock for misplaced TRIMINFO register
>> 3. Updates the Documentation at
>>    Documentation/devicetree/bindings/thermal/exynos-thermal.txt
>>
>> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
>> Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
>> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
>> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
>> ---
>> Changes since v11:
>> 1. Added description for clocks in the Documentation
>> 2. corrected the clock name in clk_get() function as per description
>>
>> Changes since v10:
>> 1. using renamed compatible "samsung,exynos5420-tmu-ext-triminfo"
>>    and passing same clock as triminfo_apbif clock for channel 2
>> 2. removed the "exynos5420-tmu-triminfo-clk" compatible
>>  .../devicetree/bindings/thermal/exynos-thermal.txt |   45 ++++++++-
>>  drivers/thermal/samsung/exynos_tmu.c               |   52 +++++++++-
>>  drivers/thermal/samsung/exynos_tmu.h               |    1 +
>>  drivers/thermal/samsung/exynos_tmu_data.c          |   99 ++++++++++++++++++++
>>  drivers/thermal/samsung/exynos_tmu_data.h          |    8 ++
>>  5 files changed, 200 insertions(+), 5 deletions(-)
>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
>
> Best regards,
> Tomasz
>
Ping.



-- 
Shine bright,
(: Nav :)

Re: [PATCH v12 2/4] thermal: samsung: change base_common to more meaningful base_second

[Naveen Krishna Ch]

Hello All,

On 19 December 2013 11:36, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> On Exynos5440 and Exynos5420 there are registers common
> across the TMU channels.
>
> To support that, we introduced a ADDRESS_MULTIPLE flag in the
> driver and the 2nd set of register base and size are provided
> in the "reg" property of the node.
>
> As per Amit's suggestion, this patch changes the base_common
> to base_second and SHARED_MEMORY to ADDRESS_MULTIPLE.
>
> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> ---
> Changes since v11:
> Added Reviewed by Tomasz
>
> Changes since v10:
> Documentation rephrased as per comments from Tomasz Figa
>
>  .../devicetree/bindings/thermal/exynos-thermal.txt       |    4 ++--
>  drivers/thermal/samsung/exynos_tmu.c                     |   14 +++++++-------
>  drivers/thermal/samsung/exynos_tmu.h                     |    4 ++--
>  drivers/thermal/samsung/exynos_tmu_data.c                |    2 +-
>  4 files changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> index 284f530..a1aa602 100644
> --- a/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> +++ b/Documentation/devicetree/bindings/thermal/exynos-thermal.txt
> @@ -11,8 +11,8 @@
>  - reg : Address range of the thermal registers. For soc's which has multiple
>         instances of TMU and some registers are shared across all TMU's like
>         interrupt related then 2 set of register has to supplied. First set
> -       belongs to each instance of TMU and second set belongs to common TMU
> -       registers.
> +       belongs to register set of TMU instance and second set belongs to
> +       registers shared with the TMU instance.
>  - interrupts : Should contain interrupt for thermal system
>  - clocks : The main clock for TMU device
>  - clock-names : Thermal system clock name
> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> index c493245..bbd0fc3 100644
> --- a/drivers/thermal/samsung/exynos_tmu.c
> +++ b/drivers/thermal/samsung/exynos_tmu.c
> @@ -41,7 +41,7 @@
>   * @id: identifier of the one instance of the TMU controller.
>   * @pdata: pointer to the tmu platform/configuration data
>   * @base: base address of the single instance of the TMU controller.
> - * @base_common: base address of the common registers of the TMU controller.
> + * @base_second: base address of the common registers of the TMU controller.
>   * @irq: irq number of the TMU controller.
>   * @soc: id of the SOC type.
>   * @irq_work: pointer to the irq work structure.
> @@ -56,7 +56,7 @@ struct exynos_tmu_data {
>         int id;
>         struct exynos_tmu_platform_data *pdata;
>         void __iomem *base;
> -       void __iomem *base_common;
> +       void __iomem *base_second;
>         int irq;
>         enum soc_type soc;
>         struct work_struct irq_work;
> @@ -297,7 +297,7 @@ skip_calib_data:
>         }
>         /*Clear the PMIN in the common TMU register*/
>         if (reg->tmu_pmin && !data->id)
> -               writel(0, data->base_common + reg->tmu_pmin);
> +               writel(0, data->base_second + reg->tmu_pmin);
>  out:
>         clk_disable(data->clk);
>         mutex_unlock(&data->lock);
> @@ -454,7 +454,7 @@ static void exynos_tmu_work(struct work_struct *work)
>
>         /* Find which sensor generated this interrupt */
>         if (reg->tmu_irqstatus) {
> -               val_type = readl(data->base_common + reg->tmu_irqstatus);
> +               val_type = readl(data->base_second + reg->tmu_irqstatus);
>                 if (!((val_type >> data->id) & 0x1))
>                         goto out;
>         }
> @@ -579,7 +579,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>          * Check if the TMU shares some registers and then try to map the
>          * memory of common registers.
>          */
> -       if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
> +       if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
>                 return 0;
>
>         if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
> @@ -587,9 +587,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
>                 return -ENODEV;
>         }
>
> -       data->base_common = devm_ioremap(&pdev->dev, res.start,
> +       data->base_second = devm_ioremap(&pdev->dev, res.start,
>                                         resource_size(&res));
> -       if (!data->base_common) {
> +       if (!data->base_second) {
>                 dev_err(&pdev->dev, "Failed to ioremap memory\n");
>                 return -ENOMEM;
>         }
> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> index 980859a..0d6b32f 100644
> --- a/drivers/thermal/samsung/exynos_tmu.h
> +++ b/drivers/thermal/samsung/exynos_tmu.h
> @@ -60,7 +60,7 @@ enum soc_type {
>   *                     state(active/idle) can be checked.
>   * TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
>   *                     sample time.
> - * TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
> + * TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
>   *                     sensors shares some common registers.
>   * TMU_SUPPORT - macro to compare the above features with the supplied.
>   */
> @@ -70,7 +70,7 @@ enum soc_type {
>  #define TMU_SUPPORT_FALLING_TRIP               BIT(3)
>  #define TMU_SUPPORT_READY_STATUS               BIT(4)
>  #define TMU_SUPPORT_EMUL_TIME                  BIT(5)
> -#define TMU_SUPPORT_SHARED_MEMORY              BIT(6)
> +#define TMU_SUPPORT_ADDRESS_MULTIPLE           BIT(6)
>
>  #define TMU_SUPPORTS(a, b)     (a->features & TMU_SUPPORT_ ## b)
>
> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> index 7cdb04e..1d27069 100644
> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> @@ -255,7 +255,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
>         .type = SOC_ARCH_EXYNOS5440, \
>         .registers = &exynos5440_tmu_registers, \
>         .features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
> -                       TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
> +                       TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
>
>  struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
>         .tmu_data = {
> --
> 1.7.10.4
>
Ping.



-- 
Shine bright,
(: Nav :)

Re: [PATCH v11 0/4] thermal: samsung: Clean up and add support for Exynos5420

[Leela Krishna Amudala]

Hi All,

I didn't see this series in mainline, Any comments for this ?

Thanks,
Leela Krishna Amudala.


On Tue, Dec 10, 2013 at 12:10 PM, Naveen Krishna Chatradhi
<ch.naveen@samsung.com> wrote:
> This patchset does a little clean up of the existing code (linux-soc-thermal)
> 1.  [v11] thermal: samsung: replace inten_ bit fields with intclr_
> 2.  [v11] thermal: samsung: change base_common to more meaningful base_second
>
> adds support for Exynos5420 in the driver and (linux-soc-thermal)
> 3.  [v11] thermal: samsung: Add TMU support for Exynos5420 SoCs
> also adds the device tree nodes for the same to exynos5420.dtsi (linux-samsung.git)
> 4.  [v11] ARM: dts: Exynos5420: Add device nodes for TMU blocks
>
> (linux-soc-thermal)
> Naveen Krishna Chatradhi (3):
>   thermal: samsung: replace inten_ bit fields with intclr_
>   thermal: samsung: change base_common to more meaningful base_second
>   thermal: samsung: Add TMU support for Exynos5420 SoCs
>
>  .../devicetree/bindings/thermal/exynos-thermal.txt |   42 ++++++-
>  drivers/thermal/samsung/exynos_tmu.c               |   72 +++++++++---
>  drivers/thermal/samsung/exynos_tmu.h               |   21 ++--
>  drivers/thermal/samsung/exynos_tmu_data.c          |  119 ++++++++++++++++++--
>  drivers/thermal/samsung/exynos_tmu_data.h          |   12 +-
>  5 files changed, 228 insertions(+), 38 deletions(-)
>
> (linux-samsung.git)
> Naveen Krishna Chatradhi (1):
>   ARM: dts: Exynos5420: Add device nodes for TMU blocks
>
>  arch/arm/boot/dts/exynos5420.dtsi |   40 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 40 insertions(+)
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH v11 0/4] thermal: samsung: Clean up and add support for Exynos5420

[Tomasz Figa]

Hi Leela,

On 19.03.2014 12:19, Leela Krishna Amudala wrote:
> Hi All,
>
> I didn't see this series in mainline, Any comments for this ?

Naveen had posted v12 of this series and I believe all the patches got 
my Reviewed-by.

Best regards,
Tomasz

Re: [PATCH v11 0/4] thermal: samsung: Clean up and add support for Exynos5420

[Naveen Krishna Ch]

Hello Tomasz,

On 20 March 2014 00:58, Tomasz Figa <t.figa@samsung.com> wrote:
> Hi Leela,
>
>
> On 19.03.2014 12:19, Leela Krishna Amudala wrote:
>>
>> Hi All,
>>
>> I didn't see this series in mainline, Any comments for this ?
>
>
> Naveen had posted v12 of this series and I believe all the patches got my
> Reviewed-by.
>
> Best regards,
> Tomasz
Thanks for your reply.
These patches are posted to the mailing list quite some time now.
Anything i can do to speed up the process.




-- 
Shine bright,
(: Nav :)

Re: [PATCH v11 0/4] thermal: samsung: Clean up and add support for Exynos5420

[Javi Merino]

On Thu, Mar 20, 2014 at 02:45:54AM +0000, Naveen Krishna Ch wrote:
> Hello Tomasz,
> 
> On 20 March 2014 00:58, Tomasz Figa <t.figa@samsung.com> wrote:
> > Hi Leela,
> >
> >
> > On 19.03.2014 12:19, Leela Krishna Amudala wrote:
> >>
> >> Hi All,
> >>
> >> I didn't see this series in mainline, Any comments for this ?
> >
> >
> > Naveen had posted v12 of this series and I believe all the patches got my
> > Reviewed-by.
> >
> > Best regards,
> > Tomasz
> Thanks for your reply.
> These patches are posted to the mailing list quite some time now.
> Anything i can do to speed up the process.

These patches create 5 thermal zones, one for each sensor.  Due to the
way the exynos code in drivers/thermal/samsung/exynos_thermal_common.c
registers thermal zones, each one gets a cpufreq_cooling_device.
Therefore you end up with 5 thermal zone each of which is controlling
the cpu frequency.

Wouldn't it be better to collate these 5 sensors to create one thermal
zone for the whole SoC?  Maybe a simplistic algorithm like reporting
the maximum temperature of all the sensors as the thermal zone
temperature is good enough.

Cheers,
Javi

Re: [PATCH v12 1/4] thermal: samsung: replace inten_ bit fields with intclr_

[Bartlomiej Zolnierkiewicz]

Hi,

Zhang, could you please review/merge this patchset?

[ We have been waiting for a review for over 3 months now.. ]

Best regards,
--
Bartlomiej Zolnierkiewicz
Samsung R&D Institute Poland
Samsung Electronics

On Friday, February 07, 2014 03:03:46 PM Naveen Krishna Ch wrote:
> Hello All,
> 
> On 2 January 2014 08:03, Zhang Rui <rui.zhang@intel.com> wrote:
> > On Thu, 2013-12-19 at 11:35 +0530, Naveen Krishna Chatradhi wrote:
> >> This patch replaces the inten_rise_shift/mask and inten_fall_shift/mask
> >> with intclr_rise_shift/mask and intclr_fall_shift/mask respectively.
> >> Currently, inten_rise_shift/mask and inten_fall_shift/mask bits are only used
> >> to configure intclr related registers.
> >>
> >> Description of H/W:
> >> The offset for the bits in the CLEAR register are not consistent across TMU
> >> modules in Exynso5250, 5420 and 5440.
> >>
> >> On Exynos5250, the FALL interrupt related en, status and clear bits are
> >> available at an offset of
> >> 16 in INTEN, INTSTAT registers and at an offset of
> >> 12 in INTCLEAR register.
> >>
> >> On Exynos5420, the FALL interrupt related en, status and clear bits are
> >> available at an offset of
> >> 16 in INTEN, INTSTAT and INTCLEAR registers.
> >>
> >> On Exynos5440,
> >> the FALL_IRQEN bits are at an offset of 4
> >> and the RISE_IRQEN bits are at an offset of 0
> >>
> >> Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
> >> Acked-by: Amit Daniel Kachhap <amit.daniel@samsung.com>
> >> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
> >> Reviewed-by: Tomasz Figa <t.figa@samsung.com>
> >
> > Eduardo,
> >
> > what do you think of this patch set?
> >
> > thanks,
> > rui
> >> ---
> >> Changes since v11:
> >> Added Reviewed by Tomasz
> >>
> >> Changes since v10:
> >> None
> >>
> >>  drivers/thermal/samsung/exynos_tmu.c      |    6 +++---
> >>  drivers/thermal/samsung/exynos_tmu.h      |   16 ++++++++--------
> >>  drivers/thermal/samsung/exynos_tmu_data.c |   18 +++++++++---------
> >>  drivers/thermal/samsung/exynos_tmu_data.h |    4 ++--
> >>  4 files changed, 22 insertions(+), 22 deletions(-)
> >>
> >> diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
> >> index 32f38b9..c493245 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu.c
> >> +++ b/drivers/thermal/samsung/exynos_tmu.c
> >> @@ -237,7 +237,7 @@ skip_calib_data:
> >>                       writeb(pdata->trigger_levels[i], data->base +
> >>                       reg->threshold_th0 + i * sizeof(reg->threshold_th0));
> >>
> >> -             writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
> >> +             writel(reg->intclr_rise_mask, data->base + reg->tmu_intclear);
> >>       } else {
> >>               /* Write temperature code for rising and falling threshold */
> >>               for (i = 0;
> >> @@ -264,8 +264,8 @@ skip_calib_data:
> >>               writel(falling_threshold,
> >>                               data->base + reg->threshold_th1);
> >>
> >> -             writel((reg->inten_rise_mask << reg->inten_rise_shift) |
> >> -                     (reg->inten_fall_mask << reg->inten_fall_shift),
> >> +             writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |
> >> +                     (reg->intclr_fall_mask << reg->intclr_fall_shift),
> >>                               data->base + reg->tmu_intclear);
> >>
> >>               /* if last threshold limit is also present */
> >> diff --git a/drivers/thermal/samsung/exynos_tmu.h b/drivers/thermal/samsung/exynos_tmu.h
> >> index 3fb6554..980859a 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu.h
> >> +++ b/drivers/thermal/samsung/exynos_tmu.h
> >> @@ -122,10 +122,6 @@ enum soc_type {
> >>   * @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
> >>   * @tmu_inten: register containing the different threshold interrupt
> >>       enable bits.
> >> - * @inten_rise_shift: shift bits of all rising interrupt bits.
> >> - * @inten_rise_mask: mask bits of all rising interrupt bits.
> >> - * @inten_fall_shift: shift bits of all rising interrupt bits.
> >> - * @inten_fall_mask: mask bits of all rising interrupt bits.
> >>   * @inten_rise0_shift: shift bits of rising 0 interrupt bits.
> >>   * @inten_rise1_shift: shift bits of rising 1 interrupt bits.
> >>   * @inten_rise2_shift: shift bits of rising 2 interrupt bits.
> >> @@ -136,6 +132,10 @@ enum soc_type {
> >>   * @inten_fall3_shift: shift bits of falling 3 interrupt bits.
> >>   * @tmu_intstat: Register containing the interrupt status values.
> >>   * @tmu_intclear: Register for clearing the raised interrupt status.
> >> + * @intclr_fall_shift: shift bits for interrupt clear fall 0
> >> + * @intclr_rise_shift: shift bits of all rising interrupt bits.
> >> + * @intclr_rise_mask: mask bits of all rising interrupt bits.
> >> + * @intclr_fall_mask: mask bits of all rising interrupt bits.
> >>   * @emul_con: TMU emulation controller register.
> >>   * @emul_temp_shift: shift bits of emulation temperature.
> >>   * @emul_time_shift: shift bits of emulation time.
> >> @@ -191,10 +191,6 @@ struct exynos_tmu_registers {
> >>       u32     threshold_th3_l0_shift;
> >>
> >>       u32     tmu_inten;
> >> -     u32     inten_rise_shift;
> >> -     u32     inten_rise_mask;
> >> -     u32     inten_fall_shift;
> >> -     u32     inten_fall_mask;
> >>       u32     inten_rise0_shift;
> >>       u32     inten_rise1_shift;
> >>       u32     inten_rise2_shift;
> >> @@ -207,6 +203,10 @@ struct exynos_tmu_registers {
> >>       u32     tmu_intstat;
> >>
> >>       u32     tmu_intclear;
> >> +     u32     intclr_fall_shift;
> >> +     u32     intclr_rise_shift;
> >> +     u32     intclr_fall_mask;
> >> +     u32     intclr_rise_mask;
> >>
> >>       u32     emul_con;
> >>       u32     emul_temp_shift;
> >> diff --git a/drivers/thermal/samsung/exynos_tmu_data.c b/drivers/thermal/samsung/exynos_tmu_data.c
> >> index 073c292..7cdb04e 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu_data.c
> >> +++ b/drivers/thermal/samsung/exynos_tmu_data.c
> >> @@ -40,13 +40,13 @@ static const struct exynos_tmu_registers exynos4210_tmu_registers = {
> >>       .threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
> >>       .threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
> >>       .tmu_inten = EXYNOS_TMU_REG_INTEN,
> >> -     .inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
> >>       .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
> >>       .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
> >>       .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
> >>       .inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
> >>       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
> >>       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> >> +     .intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
> >>  };
> >>
> >>  struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
> >> @@ -112,10 +112,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
> >>       .threshold_th0 = EXYNOS_THD_TEMP_RISE,
> >>       .threshold_th1 = EXYNOS_THD_TEMP_FALL,
> >>       .tmu_inten = EXYNOS_TMU_REG_INTEN,
> >> -     .inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> >> -     .inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> >> -     .inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
> >> -     .inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
> >>       .inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
> >>       .inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
> >>       .inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
> >> @@ -123,6 +119,10 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
> >>       .inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
> >>       .tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
> >>       .tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
> >> +     .intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
> >> +     .intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
> >> +     .intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
> >> +     .intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
> >>       .emul_con = EXYNOS_EMUL_CON,
> >>       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> >>       .emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
> >> @@ -217,10 +217,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
> >>       .threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
> >>       .threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
> >>       .tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
> >> -     .inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
> >> -     .inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
> >> -     .inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
> >> -     .inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
> >>       .inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
> >>       .inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
> >>       .inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
> >> @@ -228,6 +224,10 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
> >>       .inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
> >>       .tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
> >>       .tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
> >> +     .intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
> >> +     .intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
> >> +     .intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
> >> +     .intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
> >>       .tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
> >>       .emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
> >>       .emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
> >> diff --git a/drivers/thermal/samsung/exynos_tmu_data.h b/drivers/thermal/samsung/exynos_tmu_data.h
> >> index a1ea19d..d9495a4 100644
> >> --- a/drivers/thermal/samsung/exynos_tmu_data.h
> >> +++ b/drivers/thermal/samsung/exynos_tmu_data.h
> >> @@ -69,9 +69,10 @@
> >>  #define EXYNOS_TMU_RISE_INT_MASK     0x111
> >>  #define EXYNOS_TMU_RISE_INT_SHIFT    0
> >>  #define EXYNOS_TMU_FALL_INT_MASK     0x111
> >> -#define EXYNOS_TMU_FALL_INT_SHIFT    12
> >>  #define EXYNOS_TMU_CLEAR_RISE_INT    0x111
> >>  #define EXYNOS_TMU_CLEAR_FALL_INT    (0x111 << 12)
> >> +#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT      12
> >> +#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT  4
> >>  #define EXYNOS_TMU_TRIP_MODE_SHIFT   13
> >>  #define EXYNOS_TMU_TRIP_MODE_MASK    0x7
> >>  #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT       12
> >> @@ -119,7 +120,6 @@
> >>  #define EXYNOS5440_TMU_RISE_INT_MASK         0xf
> >>  #define EXYNOS5440_TMU_RISE_INT_SHIFT                0
> >>  #define EXYNOS5440_TMU_FALL_INT_MASK         0xf
> >> -#define EXYNOS5440_TMU_FALL_INT_SHIFT                4
> >>  #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT     0
> >>  #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT     1
> >>  #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT     2
> >
> >
> Ping.