From: Yakir Yang <ykk@rock-chips.com>
To: Inki Dae <inki.dae@samsung.com>,
Andrzej Hajda <a.hajda@samsung.com>,
Joonyoung Shim <jy0922.shim@samsung.com>,
Seung-Woo Kim <sw0312.kim@samsung.com>,
Kyungmin Park <kyungmin.park@samsung.com>,
Jingoo Han <jingoohan1@gmail.com>,
Thierry Reding <treding@nvidia.com>,
Krzysztof Kozlowski <k.kozlowski@samsung.com>,
Rob Herring <robh+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Mark Yao <mark.yao@rock-chips.com>
Cc: Russell King <linux@arm.linux.org.uk>,
djkurtz@chromium.org, dianders@chromium.org,
Sean Paul <seanpaul@chromium.org>, Kukjin Kim <kgene@kernel.org>,
Kumar Gala <galak@codeaurora.org>,
emil.l.velikov@gmail.com,
Ian Campbell <ijc+devicetree@hellion.org.uk>,
Gustavo Padovan <gustavo.padovan@collabora.co.uk>,
Kishon Vijay Abraham I <kishon@ti.com>,
Pawel Moll <pawel.moll@arm.com>,
ajaynumb@gmail.com, robherring2@gmail.com,
javier@osg.samsung.com, Andy Yan <andy.yan@rock-chips.com>,
Yakir Yang <ykk@rock-chips.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
linux-rockchip@lists.infradead.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v10 10/17] phy: Add driver for rockchip Display Port PHY
Date: Tue, 17 Nov 2015 21:09:00 +0800 [thread overview]
Message-ID: <1447765740-3777-1-git-send-email-ykk@rock-chips.com> (raw)
In-Reply-To: <1446020143-32645-1-git-send-email-ykk@rock-chips.com>
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v10:
- Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK (Brian)
BIT(4) -> BIT(20)
Changes in v9:
- Removed the unused the variable "res" in probe function. (Heiko)
- Removed the unused head file.
Changes in v8:
- Fix the mixed spacers on macro definitions. (Heiko)
- Remove the unnecessary empty line after clk_prepare_enable. (Heiko)
Changes in v7:
- Simply the commit message. (Kishon)
- Symmetrical enable/disbale the phy clock and power. (Kishon)
Changes in v6: None
Changes in v5:
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
the exist "grf" syscon already. And rename the example DT node from
"edp_phy: phy@ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
struct" to "static const struct". And correct the input paramters of
devm_phy_create() interfaces. (Heiko)
Changes in v4:
- Add commit message, and remove the redundant rockchip_dp_phy_init()
function, move those code to probe() method. And remove driver .owner
number. (Kishon)
Changes in v3:
- Suggest, add rockchip dp phy driver, collect the phy clocks and
power control. (Heiko)
Changes in v2: None
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 159 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-dp.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859d..7355819 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -319,6 +319,13 @@ config PHY_ROCKCHIP_USB
help
Enable this to support the Rockchip USB 2.0 PHY.
+config PHY_ROCKCHIP_DP
+ tristate "Rockchip Display Port PHY Driver"
+ depends on ARCH_ROCKCHIP && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip Display Port PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a..b1700cd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 0000000..3cb3bf8
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,151 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#define GRF_SOC_CON12 0x0274
+
+#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20)
+#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
+
+#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
+#define GRF_EDP_PHY_SIDDQ_ON 0
+#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
+
+struct rockchip_dp_phy {
+ struct device *dev;
+ struct regmap *grf;
+ struct clk *phy_24m;
+};
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+ struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+ int ret;
+
+ if (enable) {
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+ GRF_EDP_PHY_SIDDQ_ON);
+ if (ret < 0) {
+ dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(dp->phy_24m);
+ } else {
+ clk_disable_unprepare(dp->phy_24m);
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+ GRF_EDP_PHY_SIDDQ_OFF);
+ }
+
+ return ret;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+ return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+ return rockchip_set_phy_state(phy, false);
+}
+
+static const struct phy_ops rockchip_dp_phy_ops = {
+ .power_on = rockchip_dp_phy_power_on,
+ .power_off = rockchip_dp_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct phy_provider *phy_provider;
+ struct rockchip_dp_phy *dp;
+ struct phy *phy;
+ int ret;
+
+ if (!np)
+ return -ENODEV;
+
+ dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+ if (IS_ERR(dp))
+ return -ENOMEM;
+
+ dp->dev = dev;
+
+ dp->phy_24m = devm_clk_get(dev, "24m");
+ if (IS_ERR(dp->phy_24m)) {
+ dev_err(dev, "cannot get clock 24m\n");
+ return PTR_ERR(dp->phy_24m);
+ }
+
+ ret = clk_set_rate(dp->phy_24m, 24000000);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+ return ret;
+ }
+
+ dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dp->grf)) {
+ dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+ return PTR_ERR(dp->grf);
+ }
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
+ GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
+ if (ret != 0) {
+ dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+ return ret;
+ }
+
+ phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create phy\n");
+ return PTR_ERR(phy);
+ }
+ phy_set_drvdata(phy, dp);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+ { .compatible = "rockchip,rk3288-dp-phy" },
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+ .probe = rockchip_dp_phy_probe,
+ .driver = {
+ .name = "rockchip-dp-phy",
+ .of_match_table = rockchip_dp_phy_dt_ids,
+ },
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1
next prev parent reply other threads:[~2015-11-17 13:12 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
2015-10-28 8:19 ` [PATCH v8 01/17] drm: exynos: dp: convert to drm bridge mode Yakir Yang
2016-03-22 22:22 ` Inki Dae
2015-10-28 8:21 ` [PATCH v8 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang
2015-11-26 17:30 ` Heiko Stübner
2015-11-27 1:20 ` Yakir Yang
2015-11-27 8:42 ` Heiko Stübner
2015-10-28 8:23 ` [PATCH v8 03/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
2015-10-28 8:24 ` [PATCH v8 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
2015-10-28 8:25 ` [PATCH v8 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
2015-10-28 8:26 ` [PATCH v8 06/17] dt-bindings: add document for analogix display port driver Yakir Yang
2015-10-28 20:02 ` Heiko Stuebner
2015-10-29 1:12 ` Yakir Yang
2015-10-29 8:40 ` Heiko Stuebner
2015-10-28 8:27 ` [PATCH v8 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
2015-10-28 8:27 ` [PATCH v8 08/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
2015-11-27 8:41 ` Heiko Stübner
2015-10-28 8:28 ` [PATCH v8 09/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
2015-10-30 16:46 ` Rob Herring
2015-10-31 3:15 ` Yakir Yang
2015-10-28 8:30 ` [PATCH v8 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-10-28 20:36 ` Heiko Stuebner
2015-10-29 1:14 ` Yakir Yang
2015-11-11 23:23 ` Heiko Stuebner
[not found] ` <5643FB43.6090408@rock-chips.com>
2015-11-12 9:21 ` Heiko Stuebner
2015-10-28 8:31 ` [PATCH v8 11/17] dt-bindings: add document for rockchip dp phy Yakir Yang
2015-10-30 16:42 ` Rob Herring
2015-10-31 3:13 ` Yakir Yang
2015-10-28 8:52 ` [PATCH v8 12/17] drm: rockchip: vop: add bpc and color mode setting Yakir Yang
2015-10-28 8:55 ` [PATCH v8 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
2015-10-28 8:56 ` [PATCH v8 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
2015-11-27 13:32 ` Heiko Stübner
2015-12-02 10:46 ` Yakir Yang
2015-10-28 9:12 ` [PATCH v8 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
2015-10-28 9:13 ` [PATCH v8 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
2015-10-29 1:58 ` [PATCH v9 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-11-03 4:38 ` Brian Norris
2015-11-04 0:48 ` Yakir Yang
2015-11-04 1:13 ` Brian Norris
2015-11-05 23:45 ` Brian Norris
2015-11-17 12:58 ` Yakir Yang
2015-10-29 17:49 ` [PATCH v8 0/17] Add Analogix Core Display Port Driver Heiko Stuebner
2015-10-30 1:05 ` Yakir Yang
2015-10-30 1:09 ` [PATCH v9 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
2015-11-11 23:10 ` Rob Herring
[not found] ` <5643EAF9.9020508@rock-chips.com>
2015-11-12 23:38 ` Rob Herring
2015-10-31 6:30 ` [PATCH v9 09/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
2015-10-31 6:40 ` Yakir Yang
2015-10-31 6:42 ` [PATCH v10 " Yakir Yang
2015-10-31 18:37 ` Rob Herring
2015-11-02 0:41 ` Yakir Yang
2015-11-17 13:09 ` Yakir Yang [this message]
2015-11-17 13:31 ` [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
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