[PATCH 0/9] x86: TSC calibration update

[Len Brown <lenb@kernel.org>]

cpu_khz and tsc_khz initialization can be unreliable and expensive.
They are initialized in tsc_init()/native_calibrate_tsc(), which prints:

pr_info("Detected %lu.%03lu MHz processor\n", cpu_khz...)

native_calibrate_cpu() first tries quick_pit_calibrate(),
which can take over 50.0M cycles to succeed,
or as few as 2.4M cycles to fail.

On failure, pit_calibrate_tsc() is attempted, which can succeed
in as few as 20M cycles, but may consume over 240M cycles
before it fails.

By comparison, on many processors, tsc frequency can be discovered by
table and MSR or CPUID in under 0.002M cycles.

Subsequently tsc_refine_calibration_work() checks our work,
but it takes under 0.004M cycles.

pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n", tsc_khz...)

Finally, CPU and TSC frequency are not guaranteed to be identical,
and this series allows cpu_khz and tsc_khz to differ
within a few percent.

cheers,
Len Brown, Intel Open Source Technology Center

this patch set is also available via git:

git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux.git x86


Bin Gao (1):
      x86 tsc: enumerate BXT tsc_khz via CPUID

Len Brown (8):
      x86 tsc_msr: Identify Intel-specific code
      x86 tsc_msr: Remove debugging messages
      x86 tsc_msr: Update comments, expand definitions
      x86 tsc_msr: Correct Silvermont reference clock values
      x86 tsc_msr: Add Airmont reference clock values
      x86 tsc_msr: Extend to include Intel Core Architecture
      x86 tsc_msr: Remove irqoff around MSR-based TSC enumeration
      x86 tsc: enumerate SKL cpu_khz and tsc_khz via CPUID

 arch/x86/include/asm/tsc.h      |   4 +-
 arch/x86/include/asm/x86_init.h |   4 +-
 arch/x86/kernel/tsc.c           |  96 ++++++++++++++++++++++++++++++----
 arch/x86/kernel/tsc_msr.c       | 112 ++++++++++++++++++++++------------------
 arch/x86/kernel/x86_init.c      |   1 +
 5 files changed, 152 insertions(+), 65 deletions(-)