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From: Len Brown <lenb@kernel.org>
To: x86@kernel.org
Cc: linux-kernel@vger.kernel.org, Bin Gao <bin.gao@intel.com>,
	Len Brown <len.brown@intel.com>
Subject: [PATCH 9/9] x86 tsc: enumerate BXT tsc_khz via CPUID
Date: Thu, 31 Mar 2016 00:13:55 -0400	[thread overview]
Message-ID: <3152b94afb8c27595f9b1bfa67885015cb569ba2.1459397558.git.len.brown@intel.com> (raw)
In-Reply-To: <1459397635-4871-1-git-send-email-lenb@kernel.org>
In-Reply-To: <6e0c25e64e0fb65a42dfc63ad5f660302e07cd87.1459397558.git.len.brown@intel.com>

From: Bin Gao <bin.gao@intel.com>

Hard code the BXT crystal clock (aka ART - Always Running Timer)
to 19.200 MHz, and use CPUID leaf 0x15 to determine the BXT TSC frequency.

Use tsc_khz to sanity check BXT cpu_khz,
which can be erroneous in some configurations.

Signed-off-by: Bin Gao <bin.gao@intel.com>
[lenb: simplified]
Signed-off-by: Len Brown <len.brown@intel.com>
---
 arch/x86/kernel/tsc.c | 18 +++++++++++++++++-
 1 file changed, 17 insertions(+), 1 deletion(-)

diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index ca41c30..64dc998 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -693,7 +693,11 @@ unsigned long native_calibrate_tsc(void)
 		switch (boot_cpu_data.x86_model) {
 		case 0x4E:	/* SKL */
 		case 0x5E:	/* SKL */
-			crystal_khz = 24000;	/* 24 MHz */
+			crystal_khz = 24000;	/* 24.0 MHz */
+			break;
+		case 0x5C:	/* BXT */
+			crystal_khz = 19200;	/* 19.2 MHz */
+			break;
 		}
 	}
 
@@ -891,8 +895,12 @@ int recalibrate_cpu_khz(void)
 	if (cpu_has_tsc) {
 		cpu_khz = x86_platform.calibrate_cpu();
 		tsc_khz = x86_platform.calibrate_tsc();
+
 		if (tsc_khz == 0)
 			tsc_khz = cpu_khz;
+		else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
+			cpu_khz = tsc_khz;
+
 		cpu_data(0).loops_per_jiffy =
 			cpufreq_scale(cpu_data(0).loops_per_jiffy,
 					cpu_khz_old, cpu_khz);
@@ -1305,8 +1313,16 @@ void __init tsc_init(void)
 
 	cpu_khz = x86_platform.calibrate_cpu();
 	tsc_khz = x86_platform.calibrate_tsc();
+
+	/*
+	 * Trust non-zero tsc_khz as authorative,
+	 * and use it to sanity check cpu_khz,
+	 * which will be off if system timer is off.
+	 */
 	if (tsc_khz == 0)
 		tsc_khz = cpu_khz;
+	else if (abs(cpu_khz - tsc_khz) * 10 > tsc_khz)
+		cpu_khz = tsc_khz;
 
 	if (!tsc_khz) {
 		mark_tsc_unstable("could not calculate TSC khz");
-- 
2.8.0.rc4.16.g56331f8

  parent reply	other threads:[~2016-03-31  4:14 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-03-31  4:13 [PATCH 0/9] x86: TSC calibration update Len Brown
2016-03-31  4:13 ` [PATCH 1/9] x86 tsc_msr: Identify Intel-specific code Len Brown
2016-03-31  4:13   ` [PATCH 2/9] x86 tsc_msr: Remove debugging messages Len Brown
2016-03-31  4:13   ` [PATCH 3/9] x86 tsc_msr: Update comments, expand definitions Len Brown
2016-03-31  4:13   ` [PATCH 4/9] x86 tsc_msr: Correct Silvermont reference clock values Len Brown
2016-03-31  4:13   ` [PATCH 5/9] x86 tsc_msr: Add Airmont " Len Brown
2016-03-31  4:13   ` [PATCH 6/9] x86 tsc_msr: Extend to include Intel Core Architecture Len Brown
2016-03-31  4:13   ` [PATCH 7/9] x86 tsc_msr: Remove irqoff around MSR-based TSC enumeration Len Brown
2016-03-31  4:13   ` [PATCH 8/9] x86 tsc: enumerate SKL cpu_khz and tsc_khz via CPUID Len Brown
2016-03-31  4:13   ` Len Brown [this message]
2016-06-10 13:20 ` [PATCH 0/9] x86: TSC calibration update Thomas Gleixner

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