linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH v2 0/4] Add EDAC driver for QCOM SoCs
@ 2018-08-18  0:08 Venkata Narendra Kumar Gutta
  2018-08-18  0:08 ` [PATCH v2 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
                   ` (3 more replies)
  0 siblings, 4 replies; 19+ messages in thread
From: Venkata Narendra Kumar Gutta @ 2018-08-18  0:08 UTC (permalink / raw)
  To: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp, evgreen

This series implements EDAC driver for QCOM SoCs. As of now, this driver
supports EDAC for Last Level Cache Controller (LLCC). LLCC EDAC driver is
to detect and report single and double bit errors on Last Level Cache
Controller (LLCC) cache. This driver also takes care of dumping registers
and also adding config options to enable and disable panic when these
errors happen in LLCC.

The driver functionality is implemented in:
qcom_edac.c : This platform driver registers to edac framework and
handles the single and double bit errors in cache by registering
interrupt handlers.

llcc-slice.c: It invokes the llcc edac driver and passes platform
data to it.

This patchset depends on the LLCC driver, which is part of 4.19 release.
Link: https://patchwork.kernel.org/patch/10422531/
Link: http://lists-archives.com/linux-kernel/29157082-dt-bindings-documentation-for-qcom-llcc.html

Patch wise description given below:

Patch 1 adds the broadcast base regmap for broadcast writes in llcc.

Patch 2 adds the required changes to register edac driver from llcc driver.

Patch 3 adds the EDAC driver support for QCOM SoCS.

Patch 4 updates the dt bindings of llcc.

Changes since v1:
  * Modified the edac driver
    - Removed duplicate functions that are used to dump the syndrome registers,
      replaced that with a common function and a reg_data datastructure.
    - Removed structure containing function pointers.
    - Addressed comments on error handling to clear the interrupt status.
  * updated Kconfig

Changes since v0:
  * Added EDAC_QCOM config and updated the driver
  * Addressed comments related to indentation and other minor ones

Channagoud Kadabi (1):
  drivers: edac: Add EDAC driver support for QCOM SoCs

Venkata Narendra Kumar Gutta (3):
  drivers: soc: Add broadcast base for Last Level Cache Controller
    (LLCC)
  drivers: soc: Add support to register LLCC EDAC driver
  dt-bindigs: msm: Update documentation of qcom,llcc

 .../devicetree/bindings/arm/msm/qcom,llcc.txt      |  15 +-
 MAINTAINERS                                        |   8 +
 drivers/edac/Kconfig                               |  28 ++
 drivers/edac/Makefile                              |   1 +
 drivers/edac/qcom_edac.c                           | 446 +++++++++++++++++++++
 drivers/soc/qcom/llcc-slice.c                      |  73 ++--
 include/linux/soc/qcom/llcc-qcom.h                 |  31 +-
 7 files changed, 575 insertions(+), 27 deletions(-)
 create mode 100644 drivers/edac/qcom_edac.c

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v2 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC)
  2018-08-18  0:08 [PATCH v2 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
@ 2018-08-18  0:08 ` Venkata Narendra Kumar Gutta
  2018-08-23 23:01   ` Evan Green
  2018-08-18  0:08 ` [PATCH v2 2/4] drivers: soc: Add support to register LLCC EDAC driver Venkata Narendra Kumar Gutta
                   ` (2 subsequent siblings)
  3 siblings, 1 reply; 19+ messages in thread
From: Venkata Narendra Kumar Gutta @ 2018-08-18  0:08 UTC (permalink / raw)
  To: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp, evgreen
  Cc: Venkata Narendra Kumar Gutta

Currently, boradcast base is set to end of the LLCC banks, which may
not be correct always. As the number of banks may vary for each chipset
and the broadcast base could be at a different address as well. This info
depends on the chipset, so get the broadcast base info from the device
tree (DT). Add broadcast base in LLCC driver and use this for broadcast
writes.

Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
 drivers/soc/qcom/llcc-slice.c      | 55 +++++++++++++++++++++++---------------
 include/linux/soc/qcom/llcc-qcom.h |  4 +--
 2 files changed, 35 insertions(+), 24 deletions(-)

diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c
index fcaad1a..a63640d 100644
--- a/drivers/soc/qcom/llcc-slice.c
+++ b/drivers/soc/qcom/llcc-slice.c
@@ -105,22 +105,24 @@ static int llcc_update_act_ctrl(u32 sid,
 	u32 slice_status;
 	int ret;
 
-	act_ctrl_reg = drv_data->bcast_off + LLCC_TRP_ACT_CTRLn(sid);
-	status_reg = drv_data->bcast_off + LLCC_TRP_STATUSn(sid);
+	act_ctrl_reg = LLCC_TRP_ACT_CTRLn(sid);
+	status_reg = LLCC_TRP_STATUSn(sid);
 
 	/* Set the ACTIVE trigger */
 	act_ctrl_reg_val |= ACT_CTRL_ACT_TRIG;
-	ret = regmap_write(drv_data->regmap, act_ctrl_reg, act_ctrl_reg_val);
+	ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
+				act_ctrl_reg_val);
 	if (ret)
 		return ret;
 
 	/* Clear the ACTIVE trigger */
 	act_ctrl_reg_val &= ~ACT_CTRL_ACT_TRIG;
-	ret = regmap_write(drv_data->regmap, act_ctrl_reg, act_ctrl_reg_val);
+	ret = regmap_write(drv_data->bcast_regmap, act_ctrl_reg,
+				act_ctrl_reg_val);
 	if (ret)
 		return ret;
 
-	ret = regmap_read_poll_timeout(drv_data->regmap, status_reg,
+	ret = regmap_read_poll_timeout(drv_data->bcast_regmap, status_reg,
 				      slice_status, !(slice_status & status),
 				      0, LLCC_STATUS_READ_DELAY);
 	return ret;
@@ -225,16 +227,13 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
 	int ret;
 	const struct llcc_slice_config *llcc_table;
 	struct llcc_slice_desc desc;
-	u32 bcast_off = drv_data->bcast_off;
 
 	sz = drv_data->cfg_size;
 	llcc_table = drv_data->cfg;
 
 	for (i = 0; i < sz; i++) {
-		attr1_cfg = bcast_off +
-				LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
-		attr0_cfg = bcast_off +
-				LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
+		attr1_cfg = LLCC_TRP_ATTR1_CFGn(llcc_table[i].slice_id);
+		attr0_cfg = LLCC_TRP_ATTR0_CFGn(llcc_table[i].slice_id);
 
 		attr1_val = llcc_table[i].cache_mode;
 		attr1_val |= llcc_table[i].probe_target_ways <<
@@ -259,10 +258,12 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
 		attr0_val = llcc_table[i].res_ways & ATTR0_RES_WAYS_MASK;
 		attr0_val |= llcc_table[i].bonus_ways << ATTR0_BONUS_WAYS_SHIFT;
 
-		ret = regmap_write(drv_data->regmap, attr1_cfg, attr1_val);
+		ret = regmap_write(drv_data->bcast_regmap, attr1_cfg,
+					attr1_val);
 		if (ret)
 			return ret;
-		ret = regmap_write(drv_data->regmap, attr0_cfg, attr0_val);
+		ret = regmap_write(drv_data->bcast_regmap, attr0_cfg,
+					attr0_val);
 		if (ret)
 			return ret;
 		if (llcc_table[i].activate_on_init) {
@@ -278,24 +279,36 @@ int qcom_llcc_probe(struct platform_device *pdev,
 {
 	u32 num_banks;
 	struct device *dev = &pdev->dev;
-	struct resource *res;
-	void __iomem *base;
+	struct resource *llcc_banks_res, *llcc_bcast_res;
+	void __iomem *llcc_banks_base, *llcc_bcast_base;
 	int ret, i;
 
 	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
 	if (!drv_data)
 		return -ENOMEM;
 
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(base))
-		return PTR_ERR(base);
+	llcc_banks_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+							"llcc_base");
+	llcc_banks_base = devm_ioremap_resource(&pdev->dev, llcc_banks_res);
+	if (IS_ERR(llcc_banks_base))
+		return PTR_ERR(llcc_banks_base);
 
-	drv_data->regmap = devm_regmap_init_mmio(dev, base,
-					&llcc_regmap_config);
+	drv_data->regmap = devm_regmap_init_mmio(dev, llcc_banks_base,
+						&llcc_regmap_config);
 	if (IS_ERR(drv_data->regmap))
 		return PTR_ERR(drv_data->regmap);
 
+	llcc_bcast_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+							"llcc_broadcast_base");
+	llcc_bcast_base = devm_ioremap_resource(&pdev->dev, llcc_bcast_res);
+	if (IS_ERR(llcc_bcast_base))
+		return PTR_ERR(llcc_bcast_base);
+
+	drv_data->bcast_regmap = devm_regmap_init_mmio(dev, llcc_bcast_base,
+							&llcc_regmap_config);
+	if (IS_ERR(drv_data->bcast_regmap))
+		return PTR_ERR(drv_data->bcast_regmap);
+
 	ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
 						&num_banks);
 	if (ret)
@@ -317,8 +330,6 @@ int qcom_llcc_probe(struct platform_device *pdev,
 	for (i = 0; i < num_banks; i++)
 		drv_data->offsets[i] = i * BANK_OFFSET_STRIDE;
 
-	drv_data->bcast_off = num_banks * BANK_OFFSET_STRIDE;
-
 	drv_data->bitmap = devm_kcalloc(dev,
 	BITS_TO_LONGS(drv_data->max_slices), sizeof(unsigned long),
 						GFP_KERNEL);
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 7e3b9c6..c681e79 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -70,22 +70,22 @@ struct llcc_slice_config {
 /**
  * llcc_drv_data - Data associated with the llcc driver
  * @regmap: regmap associated with the llcc device
+ * @bcast_regmap: regmap associated with llcc broadcast offset
  * @cfg: pointer to the data structure for slice configuration
  * @lock: mutex associated with each slice
  * @cfg_size: size of the config data table
  * @max_slices: max slices as read from device tree
- * @bcast_off: Offset of the broadcast bank
  * @num_banks: Number of llcc banks
  * @bitmap: Bit map to track the active slice ids
  * @offsets: Pointer to the bank offsets array
  */
 struct llcc_drv_data {
 	struct regmap *regmap;
+	struct regmap *bcast_regmap;
 	const struct llcc_slice_config *cfg;
 	struct mutex lock;
 	u32 cfg_size;
 	u32 max_slices;
-	u32 bcast_off;
 	u32 num_banks;
 	unsigned long *bitmap;
 	u32 *offsets;
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v2 2/4] drivers: soc: Add support to register LLCC EDAC driver
  2018-08-18  0:08 [PATCH v2 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
  2018-08-18  0:08 ` [PATCH v2 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
@ 2018-08-18  0:08 ` Venkata Narendra Kumar Gutta
  2018-08-23 23:01   ` Evan Green
  2018-08-18  0:08 ` [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
  2018-08-18  0:08 ` [PATCH v2 4/4] dt-bindigs: msm: Update documentation of qcom,llcc Venkata Narendra Kumar Gutta
  3 siblings, 1 reply; 19+ messages in thread
From: Venkata Narendra Kumar Gutta @ 2018-08-18  0:08 UTC (permalink / raw)
  To: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp, evgreen
  Cc: Venkata Narendra Kumar Gutta

Cache error reporting controller is to detect and report single
and double bit errors on Last Level Cache Controller (LLCC) cache.
Add required support to register LLCC EDAC driver as platform driver,
from LLCC driver.

Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
 drivers/soc/qcom/llcc-slice.c      | 18 ++++++++++++++++--
 include/linux/soc/qcom/llcc-qcom.h |  2 ++
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/drivers/soc/qcom/llcc-slice.c b/drivers/soc/qcom/llcc-slice.c
index a63640d..09c8bb0 100644
--- a/drivers/soc/qcom/llcc-slice.c
+++ b/drivers/soc/qcom/llcc-slice.c
@@ -224,7 +224,7 @@ static int qcom_llcc_cfg_program(struct platform_device *pdev)
 	u32 attr0_val;
 	u32 max_cap_cacheline;
 	u32 sz;
-	int ret;
+	int ret = 0;
 	const struct llcc_slice_config *llcc_table;
 	struct llcc_slice_desc desc;
 
@@ -282,6 +282,7 @@ int qcom_llcc_probe(struct platform_device *pdev,
 	struct resource *llcc_banks_res, *llcc_bcast_res;
 	void __iomem *llcc_banks_base, *llcc_bcast_base;
 	int ret, i;
+	struct platform_device *llcc_edac;
 
 	drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
 	if (!drv_data)
@@ -341,6 +342,19 @@ int qcom_llcc_probe(struct platform_device *pdev,
 	mutex_init(&drv_data->lock);
 	platform_set_drvdata(pdev, drv_data);
 
-	return qcom_llcc_cfg_program(pdev);
+	ret = qcom_llcc_cfg_program(pdev);
+	if (ret)
+		return ret;
+
+	drv_data->ecc_irq = platform_get_irq(pdev, 0);
+	if (drv_data->ecc_irq >= 0) {
+		llcc_edac = platform_device_register_data(&pdev->dev,
+						"qcom_llcc_edac", -1, drv_data,
+						sizeof(*drv_data));
+		if (IS_ERR(llcc_edac))
+			dev_err(dev, "Failed to register llcc edac driver\n");
+	}
+
+	return ret;
 }
 EXPORT_SYMBOL_GPL(qcom_llcc_probe);
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index c681e79..2e4b34d 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -78,6 +78,7 @@ struct llcc_slice_config {
  * @num_banks: Number of llcc banks
  * @bitmap: Bit map to track the active slice ids
  * @offsets: Pointer to the bank offsets array
+ * @ecc_irq: interrupt for llcc cache error detection and reporting
  */
 struct llcc_drv_data {
 	struct regmap *regmap;
@@ -89,6 +90,7 @@ struct llcc_drv_data {
 	u32 num_banks;
 	unsigned long *bitmap;
 	u32 *offsets;
+	int ecc_irq;
 };
 
 #if IS_ENABLED(CONFIG_QCOM_LLCC)
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-18  0:08 [PATCH v2 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
  2018-08-18  0:08 ` [PATCH v2 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
  2018-08-18  0:08 ` [PATCH v2 2/4] drivers: soc: Add support to register LLCC EDAC driver Venkata Narendra Kumar Gutta
@ 2018-08-18  0:08 ` Venkata Narendra Kumar Gutta
  2018-08-23 23:04   ` Evan Green
  2018-08-24 16:11   ` Stephen Boyd
  2018-08-18  0:08 ` [PATCH v2 4/4] dt-bindigs: msm: Update documentation of qcom,llcc Venkata Narendra Kumar Gutta
  3 siblings, 2 replies; 19+ messages in thread
From: Venkata Narendra Kumar Gutta @ 2018-08-18  0:08 UTC (permalink / raw)
  To: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp, evgreen
  Cc: Venkata Narendra Kumar Gutta

From: Channagoud Kadabi <ckadabi@codeaurora.org>

Add error reporting driver for Single Bit Errors (SBEs) and Double Bit
Errors (DBEs). As of now, this driver supports erp for Last Level Cache
Controller (LLCC). This driver takes care of dumping registers and adding
config options to enable and disable panic when the errors happen in cache.

Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
Co-developed-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
 MAINTAINERS                        |   8 +
 drivers/edac/Kconfig               |  28 +++
 drivers/edac/Makefile              |   1 +
 drivers/edac/qcom_edac.c           | 446 +++++++++++++++++++++++++++++++++++++
 include/linux/soc/qcom/llcc-qcom.h |  25 +++
 5 files changed, 508 insertions(+)
 create mode 100644 drivers/edac/qcom_edac.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 0a23427..0bff713 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5227,6 +5227,14 @@ L:	linux-edac@vger.kernel.org
 S:	Maintained
 F:	drivers/edac/ti_edac.c
 
+EDAC-QUALCOMM
+M:	Channagoud Kadabi <ckadabi@codeaurora.org>
+M:	Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
+L:	linux-arm-msm@vger.kernel.org
+L:	linux-edac@vger.kernel.org
+S:	Maintained
+F:	drivers/edac/qcom_edac.c
+
 EDIROL UA-101/UA-1000 DRIVER
 M:	Clemens Ladisch <clemens@ladisch.de>
 L:	alsa-devel@alsa-project.org (moderated for non-subscribers)
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 57304b2..da8f150 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -460,4 +460,32 @@ config EDAC_TI
 	  Support for error detection and correction on the
           TI SoCs.
 
+config EDAC_QCOM
+	tristate "QCOM EDAC Controller"
+	depends on EDAC
+	help
+	  Support for error detection and correction on the
+	  QCOM SoCs.
+
+config EDAC_QCOM_LLCC
+	tristate "QCOM EDAC Controller for LLCC Cache"
+	depends on EDAC_QCOM && QCOM_LLCC
+	help
+	  Support for error detection and correction on the
+	  QCOM LLCC cache. Report errors caught by LLCC ECC
+	  mechanism.
+
+	  For debugging issues having to do with stability and overall system
+          health, you should probably say 'Y' here.
+
+config EDAC_QCOM_LLCC_PANIC_ON_UE
+	bool "Panic on uncorrectable errors - qcom llcc"
+	depends on EDAC_QCOM_LLCC
+	help
+	  Forcibly cause a kernel panic if an uncorrectable error (UE) is
+	  detected. This can reduce debugging times on hardware which may be
+	  operating at voltages or frequencies outside normal specification.
+
+	  For production builds, you should probably say 'N' here.
+
 endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index 02b43a7..716096d 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)		+= altera_edac.o
 obj-$(CONFIG_EDAC_SYNOPSYS)		+= synopsys_edac.o
 obj-$(CONFIG_EDAC_XGENE)		+= xgene_edac.o
 obj-$(CONFIG_EDAC_TI)			+= ti_edac.o
+obj-$(CONFIG_EDAC_QCOM)			+= qcom_edac.o
diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
new file mode 100644
index 0000000..9a8c670
--- /dev/null
+++ b/drivers/edac/qcom_edac.c
@@ -0,0 +1,446 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/edac.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/smp.h>
+#include <linux/soc/qcom/llcc-qcom.h>
+
+#include "edac_mc.h"
+#include "edac_device.h"
+
+#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
+#define LLCC_ERP_PANIC_ON_UE            1
+#else
+#define LLCC_ERP_PANIC_ON_UE            0
+#endif
+
+#define EDAC_LLCC                       "qcom_llcc"
+
+#define TRP_SYN_REG_CNT                 6
+
+#define DRP_SYN_REG_CNT                 8
+
+#define LLCC_COMMON_STATUS0             0x0003000C
+#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
+#define LLCC_LB_CNT_SHIFT               28
+
+/* single & Double Bit syndrome register offsets */
+#define TRP_ECC_SB_ERR_SYN0             0x0002304C
+#define TRP_ECC_DB_ERR_SYN0             0x00020370
+#define DRP_ECC_SB_ERR_SYN0             0x0004204C
+#define DRP_ECC_DB_ERR_SYN0             0x00042070
+
+/* Error register offsets */
+#define TRP_ECC_ERROR_STATUS1           0x00020348
+#define TRP_ECC_ERROR_STATUS0           0x00020344
+#define DRP_ECC_ERROR_STATUS1           0x00042048
+#define DRP_ECC_ERROR_STATUS0           0x00042044
+
+/* TRP, DRP interrupt register offsets */
+#define DRP_INTERRUPT_STATUS            0x00041000
+#define TRP_INTERRUPT_0_STATUS          0x00020480
+#define DRP_INTERRUPT_CLEAR             0x00041008
+#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
+#define TRP_INTERRUPT_0_CLEAR           0x00020484
+#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
+
+/* Mask and shift macros */
+#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
+#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
+#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
+
+#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
+#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
+#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
+
+#define SB_ECC_ERROR                    BIT(0)
+#define DB_ECC_ERROR                    BIT(1)
+
+#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
+#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
+
+/* Config registers offsets*/
+#define DRP_ECC_ERROR_CFG               0x00040000
+
+/* TRP, DRP interrupt register offsets */
+#define CMN_INTERRUPT_0_ENABLE          0x0003001C
+#define CMN_INTERRUPT_2_ENABLE          0x0003003C
+#define TRP_INTERRUPT_0_ENABLE          0x00020488
+#define DRP_INTERRUPT_ENABLE            0x0004100C
+
+#define SB_ERROR_THRESHOLD              0x1
+#define SB_ERROR_THRESHOLD_SHIFT        24
+#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
+#define TRP0_INTERRUPT_ENABLE           0x1
+#define DRP0_INTERRUPT_ENABLE           BIT(6)
+#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
+
+enum {
+	LLCC_DRAM_CE = 0,
+	LLCC_DRAM_UE,
+	LLCC_TRAM_CE,
+	LLCC_TRAM_UE,
+	LLCC_ERR_TYPE_MAX = LLCC_TRAM_UE + 1,
+};
+
+static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
+{
+	u32 sb_err_threshold;
+	int ret;
+
+	/* Enable TRP in instance 2 of common interrupt enable register */
+	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
+				 TRP0_INTERRUPT_ENABLE,
+				 TRP0_INTERRUPT_ENABLE);
+	if (ret)
+		return ret;
+
+	/* Enable ECC interrupts on Tag Ram */
+	ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
+				 SB_DB_TRP_INTERRUPT_ENABLE,
+				 SB_DB_TRP_INTERRUPT_ENABLE);
+	if (ret)
+		return ret;
+
+	/* Enable SB error for Data RAM */
+	sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
+	ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
+			   sb_err_threshold);
+	if (ret)
+		return ret;
+
+	/* Enable DRP in instance 2 of common interrupt enable register */
+	ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
+				 DRP0_INTERRUPT_ENABLE,
+				 DRP0_INTERRUPT_ENABLE);
+	if (ret)
+		return ret;
+
+	/* Enable ECC interrupts on Data Ram */
+	ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
+			   SB_DB_DRP_INTERRUPT_ENABLE);
+	return ret;
+}
+
+/* Clear the error interrupt and counter registers */
+static int
+qcom_llcc_clear_errors_status(int err_type, struct llcc_drv_data *drv)
+{
+	int ret = 0;
+
+	switch (err_type) {
+	case LLCC_DRAM_CE:
+	case LLCC_DRAM_UE:
+		/* Clear the interrupt */
+		ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
+				   DRP_TRP_INT_CLEAR);
+		if (ret)
+			return ret;
+
+		/* Clear the counters */
+		ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
+				   DRP_TRP_CNT_CLEAR);
+		if (ret)
+			return ret;
+		break;
+	case LLCC_TRAM_CE:
+	case LLCC_TRAM_UE:
+		ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
+				   DRP_TRP_INT_CLEAR);
+		if (ret)
+			return ret;
+
+		ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
+				   DRP_TRP_CNT_CLEAR);
+		if (ret)
+			return ret;
+		break;
+	}
+	return ret;
+}
+
+/* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/
+static int
+dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type)
+{
+	struct llcc_edac_reg_data *reg_data = &(drv->edac_reg[err_type]);
+	int err_cnt, err_ways, ret, i;
+	u32 synd_reg, synd_val;
+
+	for (i = 0; i < reg_data->reg_cnt; i++) {
+		synd_reg = reg_data->synd_reg + (i * 4);
+		ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
+				  &synd_val);
+		if (ret)
+			goto clear;
+		edac_printk(KERN_CRIT, EDAC_LLCC, "%s: ECC_SYN%d: 0x%8x\n",
+			    reg_data->err_name, i, synd_val);
+	}
+
+	ret = regmap_read(drv->regmap,
+			  drv->offsets[bank] + reg_data->err_status_reg,
+			  &err_cnt);
+	if (ret)
+		goto clear;
+
+	err_cnt &= reg_data->err_count_mask;
+	err_cnt >>= reg_data->err_count_shift;
+	edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error count: 0x%4x\n",
+		    reg_data->err_name, err_cnt);
+
+	ret = regmap_read(drv->regmap,
+			  drv->offsets[bank] + reg_data->err_ways_status,
+			  &err_ways);
+	if (ret)
+		goto clear;
+
+	err_ways &= reg_data->err_ways_mask;
+	err_ways >>= reg_data->err_ways_shift;
+
+	edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error ways: 0x%4x\n",
+		    reg_data->err_name, err_ways);
+
+clear:
+	ret = qcom_llcc_clear_errors_status(err_type, drv);
+	return ret;
+}
+
+static int
+dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank)
+{
+	struct llcc_drv_data *drv = edev_ctl->pvt_info;
+	int ret = 0;
+
+	ret = dump_syn_reg_values(drv, bank, err_type);
+	if (ret)
+		return ret;
+
+	switch (err_type) {
+	case LLCC_DRAM_CE:
+		edac_device_handle_ce(edev_ctl, 0, bank,
+				      "LLCC Data RAM correctable Error");
+		break;
+	case LLCC_DRAM_UE:
+		edac_device_handle_ue(edev_ctl, 0, bank,
+				      "LLCC Data RAM uncorrectable Error");
+		break;
+	case LLCC_TRAM_CE:
+		edac_device_handle_ce(edev_ctl, 0, bank,
+				      "LLCC Tag RAM correctable Error");
+		break;
+	case LLCC_TRAM_UE:
+		edac_device_handle_ue(edev_ctl, 0, bank,
+				      "LLCC Tag RAM uncorrectable Error");
+		break;
+	}
+
+	return ret;
+}
+
+static irqreturn_t
+llcc_ecc_irq_handler(int irq, void *edev_ctl)
+{
+	struct edac_device_ctl_info *edac_dev_ctl;
+	irqreturn_t irq_rc = IRQ_NONE;
+	u32 drp_error, trp_error, i;
+	struct llcc_drv_data *drv;
+	int ret;
+
+	edac_dev_ctl = (struct edac_device_ctl_info *)edev_ctl;
+	drv = edac_dev_ctl->pvt_info;
+
+	for (i = 0; i < drv->num_banks; i++) {
+		/* Look for Data RAM errors */
+		ret = regmap_read(drv->regmap,
+				  drv->offsets[i] + DRP_INTERRUPT_STATUS,
+				  &drp_error);
+		if (ret)
+			return irq_rc;
+
+		if (drp_error & SB_ECC_ERROR) {
+			edac_printk(KERN_CRIT, EDAC_LLCC,
+				    "Single Bit Error detected in Data Ram\n");
+			ret = dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
+			if (!ret)
+				irq_rc = IRQ_HANDLED;
+		} else if (drp_error & DB_ECC_ERROR) {
+			edac_printk(KERN_CRIT, EDAC_LLCC,
+				    "Double Bit Error detected in Data Ram\n");
+			ret = dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
+			if (!ret)
+				irq_rc = IRQ_HANDLED;
+		}
+
+		/* Look for Tag RAM errors */
+		ret = regmap_read(drv->regmap,
+				  drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
+				  &trp_error);
+		if (ret)
+			return irq_rc;
+
+		if (trp_error & SB_ECC_ERROR) {
+			edac_printk(KERN_CRIT, EDAC_LLCC,
+				    "Single Bit Error detected in Tag Ram\n");
+			ret = dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
+			if (!ret)
+				irq_rc = IRQ_HANDLED;
+		} else if (trp_error & DB_ECC_ERROR) {
+			edac_printk(KERN_CRIT, EDAC_LLCC,
+				    "Double Bit Error detected in Tag Ram\n");
+			ret = dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
+			if (!ret)
+				irq_rc = IRQ_HANDLED;
+		}
+	}
+
+	return irq_rc;
+}
+
+static void llcc_edac_reg_data_init(struct llcc_edac_reg_data *edac_reg)
+{
+
+	struct llcc_edac_reg_data *reg_data;
+
+	/* Initialize register info for LLCC_DRAM_CE */
+	reg_data = &edac_reg[LLCC_DRAM_CE];
+	reg_data->err_name = "DRAM Single-bit";
+	reg_data->reg_cnt = DRP_SYN_REG_CNT;
+	reg_data->synd_reg = DRP_ECC_SB_ERR_SYN0;
+	reg_data->err_status_reg = DRP_ECC_ERROR_STATUS1;
+	reg_data->err_count_mask = ECC_SB_ERR_COUNT_MASK;
+	reg_data->err_count_shift = ECC_SB_ERR_COUNT_SHIFT;
+	reg_data->err_ways_status = DRP_ECC_ERROR_STATUS0;
+	reg_data->err_ways_mask = ECC_SB_ERR_WAYS_MASK;
+
+	/* Initialize register info for LLCC_DRAM_UE */
+	reg_data = &edac_reg[LLCC_DRAM_UE];
+	reg_data->err_name = "DRAM Double-bit";
+	reg_data->reg_cnt = DRP_SYN_REG_CNT;
+	reg_data->synd_reg = DRP_ECC_DB_ERR_SYN0;
+	reg_data->err_status_reg = DRP_ECC_ERROR_STATUS1;
+	reg_data->err_count_mask = ECC_DB_ERR_COUNT_MASK;
+	reg_data->err_ways_status = DRP_ECC_ERROR_STATUS0;
+	reg_data->err_ways_mask = ECC_DB_ERR_WAYS_MASK;
+	reg_data->err_ways_shift = ECC_DB_ERR_WAYS_SHIFT;
+
+	/* Initialize register info for LLCC_TRAM_CE */
+	reg_data = &edac_reg[LLCC_TRAM_CE];
+	reg_data->err_name = "TRAM Single-bit";
+	reg_data->reg_cnt = TRP_SYN_REG_CNT;
+	reg_data->synd_reg = TRP_ECC_SB_ERR_SYN0;
+	reg_data->err_status_reg = TRP_ECC_ERROR_STATUS1;
+	reg_data->err_count_mask = ECC_SB_ERR_COUNT_MASK;
+	reg_data->err_count_shift = ECC_SB_ERR_COUNT_SHIFT;
+	reg_data->err_ways_status = TRP_ECC_ERROR_STATUS0;
+	reg_data->err_ways_mask = ECC_SB_ERR_WAYS_MASK;
+
+	/* Initialize register info for LLCC_TRAM_UE */
+	reg_data = &edac_reg[LLCC_TRAM_UE];
+	reg_data->err_name = "TRAM Double-bit";
+	reg_data->reg_cnt = TRP_SYN_REG_CNT;
+	reg_data->synd_reg = TRP_ECC_DB_ERR_SYN0;
+	reg_data->err_status_reg = TRP_ECC_ERROR_STATUS1;
+	reg_data->err_count_mask = ECC_DB_ERR_COUNT_MASK;
+	reg_data->err_ways_status = TRP_ECC_ERROR_STATUS0;
+	reg_data->err_ways_mask = ECC_DB_ERR_WAYS_MASK;
+	reg_data->err_ways_shift = ECC_DB_ERR_WAYS_SHIFT;
+}
+
+static int qcom_llcc_edac_probe(struct platform_device *pdev)
+{
+	struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
+	struct edac_device_ctl_info *edev_ctl;
+	struct device *dev = &pdev->dev;
+	int ecc_irq;
+	int rc;
+
+	/* Initialize register set for the error types*/
+	llcc_driv_data->edac_reg = devm_kcalloc(dev, LLCC_ERR_TYPE_MAX,
+					sizeof(struct llcc_edac_reg_data),
+					GFP_KERNEL);
+	llcc_edac_reg_data_init(llcc_driv_data->edac_reg);
+
+	rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
+	if (rc)
+		return rc;
+
+	/* Allocate edac control info */
+	edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",
+					      llcc_driv_data->num_banks, 1,
+					      NULL, 0,
+					      edac_device_alloc_index());
+
+	if (!edev_ctl)
+		return -ENOMEM;
+
+	edev_ctl->dev = dev;
+	edev_ctl->mod_name = dev_name(dev);
+	edev_ctl->dev_name = dev_name(dev);
+	edev_ctl->ctl_name = "llcc";
+	edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
+	edev_ctl->pvt_info = llcc_driv_data;
+
+	rc = edac_device_add_device(edev_ctl);
+	if (rc)
+		goto out_mem;
+
+	platform_set_drvdata(pdev, edev_ctl);
+
+	/* Request for ecc irq */
+	ecc_irq = llcc_driv_data->ecc_irq;
+	if (ecc_irq < 0) {
+		rc = -ENODEV;
+		goto out_dev;
+	}
+	rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
+			      IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl);
+	if (rc)
+		goto out_dev;
+
+	return rc;
+
+out_dev:
+	edac_device_del_device(edev_ctl->dev);
+out_mem:
+	edac_device_free_ctl_info(edev_ctl);
+
+	return rc;
+}
+
+static int qcom_llcc_edac_remove(struct platform_device *pdev)
+{
+	struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&pdev->dev);
+
+	edac_device_del_device(edev_ctl->dev);
+	edac_device_free_ctl_info(edev_ctl);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+static const struct of_device_id qcom_llcc_edac_match_table[] = {
+#ifdef EDAC_QCOM_LLCC
+	{ .compatible = "qcom,llcc-edac" },
+#endif
+	{ },
+};
+
+static struct platform_driver qcom_llcc_edac_driver = {
+	.probe = qcom_llcc_edac_probe,
+	.remove = qcom_llcc_edac_remove,
+	.driver = {
+		.name = "qcom_llcc_edac",
+		.of_match_table = qcom_llcc_edac_match_table,
+	},
+};
+module_platform_driver(qcom_llcc_edac_driver);
+
+MODULE_DESCRIPTION("QCOM EDAC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
index 2e4b34d..25096e0 100644
--- a/include/linux/soc/qcom/llcc-qcom.h
+++ b/include/linux/soc/qcom/llcc-qcom.h
@@ -84,6 +84,7 @@ struct llcc_drv_data {
 	struct regmap *regmap;
 	struct regmap *bcast_regmap;
 	const struct llcc_slice_config *cfg;
+	struct llcc_edac_reg_data *edac_reg;
 	struct mutex lock;
 	u32 cfg_size;
 	u32 max_slices;
@@ -93,6 +94,30 @@ struct llcc_drv_data {
 	int ecc_irq;
 };
 
+/**
+ * llcc_edac_reg_data - llcc edac registers data for each error type
+ * @err_name: name of the error
+ * @reg_cnt: number of registers
+ * @synd_reg: syndrome register address
+ * @err_status_reg: Status register address to read the error count
+ * @err_count_mask: Mask value to get the error count
+ * @err_count_shift: Shift value to get the error count
+ * @err_ways_status: Status register address to read error ways
+ * @err_ways_mask: Mask value to get the error ways
+ * @err_ways_shift: Shift value to get the error ways
+ */
+struct llcc_edac_reg_data {
+	char *err_name;
+	int reg_cnt;
+	int synd_reg;
+	int err_status_reg;
+	int err_count_mask;
+	int err_count_shift;
+	int err_ways_status;
+	int err_ways_mask;
+	int err_ways_shift;
+};
+
 #if IS_ENABLED(CONFIG_QCOM_LLCC)
 /**
  * llcc_slice_getd - get llcc slice descriptor
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 19+ messages in thread

* [PATCH v2 4/4] dt-bindigs: msm: Update documentation of qcom,llcc
  2018-08-18  0:08 [PATCH v2 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
                   ` (2 preceding siblings ...)
  2018-08-18  0:08 ` [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
@ 2018-08-18  0:08 ` Venkata Narendra Kumar Gutta
  2018-08-20 19:53   ` Rob Herring
  3 siblings, 1 reply; 19+ messages in thread
From: Venkata Narendra Kumar Gutta @ 2018-08-18  0:08 UTC (permalink / raw)
  To: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp, evgreen
  Cc: Venkata Narendra Kumar Gutta

Add reg-names and interrupts for LLCC documentation and the usage
examples. llcc broadcast base is added in addition to llcc base,
which is used for llcc broadcast writes.

Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
---
 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
index 5e85749..b4b1c86 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
@@ -18,9 +18,22 @@ Properties:
 	Value Type: <prop-encoded-array>
 	Definition: Start address and the the size of the register region.
 
+- reg-names:
+        Usage: required
+        Value Type: <stringlist>
+        Definition: Register region names. Must be "llcc_base", "llcc_bcast_base".
+
+- interrupts:
+	Usage: required
+	Definition: The interrupt is associated with the llcc edac device.
+			It's used for llcc cache single and double bit error detection
+			and reporting.
+
 Example:
 
 	cache-controller@1100000 {
 		compatible = "qcom,sdm845-llcc";
-		reg = <0x1100000 0x250000>;
+		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
+		reg-names = "llcc_base", "llcc_bcast_base";
+		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
 	};
-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project


^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 4/4] dt-bindigs: msm: Update documentation of qcom,llcc
  2018-08-18  0:08 ` [PATCH v2 4/4] dt-bindigs: msm: Update documentation of qcom,llcc Venkata Narendra Kumar Gutta
@ 2018-08-20 19:53   ` Rob Herring
  2018-08-22 21:46     ` vnkgutta
  0 siblings, 1 reply; 19+ messages in thread
From: Rob Herring @ 2018-08-20 19:53 UTC (permalink / raw)
  To: Venkata Narendra Kumar Gutta
  Cc: mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, mark.rutland, devicetree, tsoni,
	ckadabi, rishabhb, bp, evgreen

On Fri, Aug 17, 2018 at 05:08:35PM -0700, Venkata Narendra Kumar Gutta wrote:
> Add reg-names and interrupts for LLCC documentation and the usage
> examples. llcc broadcast base is added in addition to llcc base,
> which is used for llcc broadcast writes.

Typo in the subject.

This binding just landed recently and it's already being updated? Sigh.
Bindings should be complete from the start. Technically, you can't add 
new required properties.

> 
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> ---
>  Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 ++++++++++++++-
>  1 file changed, 14 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
> index 5e85749..b4b1c86 100644
> --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
> @@ -18,9 +18,22 @@ Properties:
>  	Value Type: <prop-encoded-array>
>  	Definition: Start address and the the size of the register region.
>  
> +- reg-names:
> +        Usage: required
> +        Value Type: <stringlist>
> +        Definition: Register region names. Must be "llcc_base", "llcc_bcast_base".

reg needs to be updated that there are 2 entries.

> +
> +- interrupts:
> +	Usage: required
> +	Definition: The interrupt is associated with the llcc edac device.
> +			It's used for llcc cache single and double bit error detection
> +			and reporting.
> +
>  Example:
>  
>  	cache-controller@1100000 {
>  		compatible = "qcom,sdm845-llcc";
> -		reg = <0x1100000 0x250000>;
> +		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
> +		reg-names = "llcc_base", "llcc_bcast_base";
> +		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
>  	};
> -- 
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
> 

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 4/4] dt-bindigs: msm: Update documentation of qcom,llcc
  2018-08-20 19:53   ` Rob Herring
@ 2018-08-22 21:46     ` vnkgutta
  0 siblings, 0 replies; 19+ messages in thread
From: vnkgutta @ 2018-08-22 21:46 UTC (permalink / raw)
  To: Rob Herring
  Cc: mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, mark.rutland, devicetree, tsoni,
	ckadabi, rishabhb, bp, evgreen

On 2018-08-20 12:53, Rob Herring wrote:
> On Fri, Aug 17, 2018 at 05:08:35PM -0700, Venkata Narendra Kumar Gutta 
> wrote:
>> Add reg-names and interrupts for LLCC documentation and the usage
>> examples. llcc broadcast base is added in addition to llcc base,
>> which is used for llcc broadcast writes.
> 
> Typo in the subject.
> 
> This binding just landed recently and it's already being updated? Sigh.
> Bindings should be complete from the start. Technically, you can't add
> new required properties.

Sure, I'll correct the typo.

llcc broadcast base was being computed from the number of banks which 
was incorrect,
so we have to add this property.

And the interrupt is needed for EDAC functionality.

> 
>> 
>> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
>> ---
>>  Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt | 15 
>> ++++++++++++++-
>>  1 file changed, 14 insertions(+), 1 deletion(-)
>> 
>> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt 
>> b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>> index 5e85749..b4b1c86 100644
>> --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>> @@ -18,9 +18,22 @@ Properties:
>>  	Value Type: <prop-encoded-array>
>>  	Definition: Start address and the the size of the register region.
>> 
>> +- reg-names:
>> +        Usage: required
>> +        Value Type: <stringlist>
>> +        Definition: Register region names. Must be "llcc_base", 
>> "llcc_bcast_base".
> 
> reg needs to be updated that there are 2 entries.

Ok, I'll update this in the next version.

> 
>> +
>> +- interrupts:
>> +	Usage: required
>> +	Definition: The interrupt is associated with the llcc edac device.
>> +			It's used for llcc cache single and double bit error detection
>> +			and reporting.
>> +
>>  Example:
>> 
>>  	cache-controller@1100000 {
>>  		compatible = "qcom,sdm845-llcc";
>> -		reg = <0x1100000 0x250000>;
>> +		reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
>> +		reg-names = "llcc_base", "llcc_bcast_base";
>> +		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
>>  	};
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
>> Forum,
>> a Linux Foundation Collaborative Project
>> 

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC)
  2018-08-18  0:08 ` [PATCH v2 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
@ 2018-08-23 23:01   ` Evan Green
  2018-08-24 17:58     ` vnkgutta
  0 siblings, 1 reply; 19+ messages in thread
From: Evan Green @ 2018-08-23 23:01 UTC (permalink / raw)
  To: vnkgutta
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
<vnkgutta@codeaurora.org> wrote:
>
> Currently, boradcast base is set to end of the LLCC banks, which may

s/boradcast/broadcast/

> not be correct always. As the number of banks may vary for each chipset
> and the broadcast base could be at a different address as well. This info
> depends on the chipset, so get the broadcast base info from the device
> tree (DT). Add broadcast base in LLCC driver and use this for broadcast
> writes.
>
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> ---
>  drivers/soc/qcom/llcc-slice.c      | 55 +++++++++++++++++++++++---------------
>  include/linux/soc/qcom/llcc-qcom.h |  4 +--
>  2 files changed, 35 insertions(+), 24 deletions(-)
>

Reviewed-by: Evan Green <evgreen@chromium.org>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 2/4] drivers: soc: Add support to register LLCC EDAC driver
  2018-08-18  0:08 ` [PATCH v2 2/4] drivers: soc: Add support to register LLCC EDAC driver Venkata Narendra Kumar Gutta
@ 2018-08-23 23:01   ` Evan Green
  2018-08-24 17:57     ` vnkgutta
  0 siblings, 1 reply; 19+ messages in thread
From: Evan Green @ 2018-08-23 23:01 UTC (permalink / raw)
  To: vnkgutta
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
<vnkgutta@codeaurora.org> wrote:
>
> Cache error reporting controller is to detect and report single

Should be "Cache error reporting controller detects and reports single"...

Other than that:
Reviewed-by: Evan Green <evgreen@chromium.org>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-18  0:08 ` [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
@ 2018-08-23 23:04   ` Evan Green
  2018-08-23 23:07     ` Evan Green
  2018-08-24 18:32     ` vnkgutta
  2018-08-24 16:11   ` Stephen Boyd
  1 sibling, 2 replies; 19+ messages in thread
From: Evan Green @ 2018-08-23 23:04 UTC (permalink / raw)
  To: vnkgutta
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
<vnkgutta@codeaurora.org> wrote:
>
> From: Channagoud Kadabi <ckadabi@codeaurora.org>
>
> Add error reporting driver for Single Bit Errors (SBEs) and Double Bit
> Errors (DBEs). As of now, this driver supports erp for Last Level Cache
> Controller (LLCC). This driver takes care of dumping registers and adding
> config options to enable and disable panic when the errors happen in cache.
>
> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> Co-developed-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> ---
>  MAINTAINERS                        |   8 +
>  drivers/edac/Kconfig               |  28 +++
>  drivers/edac/Makefile              |   1 +
>  drivers/edac/qcom_edac.c           | 446 +++++++++++++++++++++++++++++++++++++
>  include/linux/soc/qcom/llcc-qcom.h |  25 +++
>  5 files changed, 508 insertions(+)
>  create mode 100644 drivers/edac/qcom_edac.c
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 0a23427..0bff713 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -5227,6 +5227,14 @@ L:       linux-edac@vger.kernel.org
>  S:     Maintained
>  F:     drivers/edac/ti_edac.c
>
> +EDAC-QUALCOMM
> +M:     Channagoud Kadabi <ckadabi@codeaurora.org>
> +M:     Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> +L:     linux-arm-msm@vger.kernel.org
> +L:     linux-edac@vger.kernel.org
> +S:     Maintained
> +F:     drivers/edac/qcom_edac.c
> +
>  EDIROL UA-101/UA-1000 DRIVER
>  M:     Clemens Ladisch <clemens@ladisch.de>
>  L:     alsa-devel@alsa-project.org (moderated for non-subscribers)
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 57304b2..da8f150 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -460,4 +460,32 @@ config EDAC_TI
>           Support for error detection and correction on the
>            TI SoCs.
>
> +config EDAC_QCOM
> +       tristate "QCOM EDAC Controller"
> +       depends on EDAC
> +       help
> +         Support for error detection and correction on the
> +         QCOM SoCs.
> +
> +config EDAC_QCOM_LLCC
> +       tristate "QCOM EDAC Controller for LLCC Cache"
> +       depends on EDAC_QCOM && QCOM_LLCC
> +       help
> +         Support for error detection and correction on the
> +         QCOM LLCC cache. Report errors caught by LLCC ECC
> +         mechanism.
> +
> +         For debugging issues having to do with stability and overall system
> +          health, you should probably say 'Y' here.
> +
> +config EDAC_QCOM_LLCC_PANIC_ON_UE
> +       bool "Panic on uncorrectable errors - qcom llcc"
> +       depends on EDAC_QCOM_LLCC
> +       help
> +         Forcibly cause a kernel panic if an uncorrectable error (UE) is
> +         detected. This can reduce debugging times on hardware which may be
> +         operating at voltages or frequencies outside normal specification.
> +
> +         For production builds, you should probably say 'N' here.
> +
>  endif # EDAC
> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> index 02b43a7..716096d 100644
> --- a/drivers/edac/Makefile
> +++ b/drivers/edac/Makefile
> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)             += altera_edac.o
>  obj-$(CONFIG_EDAC_SYNOPSYS)            += synopsys_edac.o
>  obj-$(CONFIG_EDAC_XGENE)               += xgene_edac.o
>  obj-$(CONFIG_EDAC_TI)                  += ti_edac.o
> +obj-$(CONFIG_EDAC_QCOM)                        += qcom_edac.o
> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
> new file mode 100644
> index 0000000..9a8c670
> --- /dev/null
> +++ b/drivers/edac/qcom_edac.c
> @@ -0,0 +1,446 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/edac.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/smp.h>
> +#include <linux/soc/qcom/llcc-qcom.h>
> +
> +#include "edac_mc.h"
> +#include "edac_device.h"
> +
> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
> +#define LLCC_ERP_PANIC_ON_UE            1
> +#else
> +#define LLCC_ERP_PANIC_ON_UE            0
> +#endif
> +
> +#define EDAC_LLCC                       "qcom_llcc"
> +
> +#define TRP_SYN_REG_CNT                 6
> +
> +#define DRP_SYN_REG_CNT                 8
> +
> +#define LLCC_COMMON_STATUS0             0x0003000C
> +#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
> +#define LLCC_LB_CNT_SHIFT               28
> +
> +/* single & Double Bit syndrome register offsets */

Strange capitalization going on here.

> +#define TRP_ECC_SB_ERR_SYN0             0x0002304C
> +#define TRP_ECC_DB_ERR_SYN0             0x00020370
> +#define DRP_ECC_SB_ERR_SYN0             0x0004204C
> +#define DRP_ECC_DB_ERR_SYN0             0x00042070

I think the convention is to use lowercase hex everywhere.

> +
> +/* Error register offsets */
> +#define TRP_ECC_ERROR_STATUS1           0x00020348
> +#define TRP_ECC_ERROR_STATUS0           0x00020344
> +#define DRP_ECC_ERROR_STATUS1           0x00042048
> +#define DRP_ECC_ERROR_STATUS0           0x00042044
> +
> +/* TRP, DRP interrupt register offsets */
> +#define DRP_INTERRUPT_STATUS            0x00041000
> +#define TRP_INTERRUPT_0_STATUS          0x00020480
> +#define DRP_INTERRUPT_CLEAR             0x00041008
> +#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
> +#define TRP_INTERRUPT_0_CLEAR           0x00020484
> +#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
> +
> +/* Mask and shift macros */
> +#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
> +#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
> +#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
> +
> +#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
> +#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
> +#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
> +
> +#define SB_ECC_ERROR                    BIT(0)
> +#define DB_ECC_ERROR                    BIT(1)
> +
> +#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
> +#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
> +
> +/* Config registers offsets*/
> +#define DRP_ECC_ERROR_CFG               0x00040000
> +
> +/* TRP, DRP interrupt register offsets */
> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
> +#define DRP_INTERRUPT_ENABLE            0x0004100C
> +
> +#define SB_ERROR_THRESHOLD              0x1
> +#define SB_ERROR_THRESHOLD_SHIFT        24
> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
> +#define TRP0_INTERRUPT_ENABLE           0x1
> +#define DRP0_INTERRUPT_ENABLE           BIT(6)
> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
> +
> +enum {
> +       LLCC_DRAM_CE = 0,
> +       LLCC_DRAM_UE,
> +       LLCC_TRAM_CE,
> +       LLCC_TRAM_UE,
> +       LLCC_ERR_TYPE_MAX = LLCC_TRAM_UE + 1,

This is a nit, or perhaps personal preference, but I prefer to not
have initializers for sentinel values, since it's one more thing
someone could forget to update when adding new values.

> +};
> +
> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
> +{
> +       u32 sb_err_threshold;
> +       int ret;
> +
> +       /* Enable TRP in instance 2 of common interrupt enable register */

Can we get a comment explaining what's so special about instance 2?
Instances 1 and 3 get no love?

> +       ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
> +                                TRP0_INTERRUPT_ENABLE,
> +                                TRP0_INTERRUPT_ENABLE);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable ECC interrupts on Tag Ram */
> +       ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
> +                                SB_DB_TRP_INTERRUPT_ENABLE,
> +                                SB_DB_TRP_INTERRUPT_ENABLE);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable SB error for Data RAM */
> +       sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
> +       ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
> +                          sb_err_threshold);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable DRP in instance 2 of common interrupt enable register */
> +       ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
> +                                DRP0_INTERRUPT_ENABLE,
> +                                DRP0_INTERRUPT_ENABLE);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable ECC interrupts on Data Ram */
> +       ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
> +                          SB_DB_DRP_INTERRUPT_ENABLE);
> +       return ret;
> +}
> +
> +/* Clear the error interrupt and counter registers */
> +static int
> +qcom_llcc_clear_errors_status(int err_type, struct llcc_drv_data *drv)

Another nit: errors_status is kind of weird. Maybe
qcom_llcc_clear_errors or qcom_llcc_clear_error_status?

> +{
> +       int ret = 0;
> +
> +       switch (err_type) {
> +       case LLCC_DRAM_CE:
> +       case LLCC_DRAM_UE:
> +               /* Clear the interrupt */
> +               ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
> +                                  DRP_TRP_INT_CLEAR);
> +               if (ret)
> +                       return ret;
> +
> +               /* Clear the counters */
> +               ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
> +                                  DRP_TRP_CNT_CLEAR);
> +               if (ret)
> +                       return ret;
> +               break;
> +       case LLCC_TRAM_CE:
> +       case LLCC_TRAM_UE:
> +               ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
> +                                  DRP_TRP_INT_CLEAR);
> +               if (ret)
> +                       return ret;
> +
> +               ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
> +                                  DRP_TRP_CNT_CLEAR);
> +               if (ret)
> +                       return ret;
> +               break;

A default case that errors or complains or both would be nice.

> +       }
> +       return ret;
> +}
> +
> +/* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/
> +static int
> +dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type)
> +{
> +       struct llcc_edac_reg_data *reg_data = &(drv->edac_reg[err_type]);
> +       int err_cnt, err_ways, ret, i;
> +       u32 synd_reg, synd_val;
> +
> +       for (i = 0; i < reg_data->reg_cnt; i++) {
> +               synd_reg = reg_data->synd_reg + (i * 4);
> +               ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +                                 &synd_val);
> +               if (ret)
> +                       goto clear;
> +               edac_printk(KERN_CRIT, EDAC_LLCC, "%s: ECC_SYN%d: 0x%8x\n",
> +                           reg_data->err_name, i, synd_val);
> +       }
> +
> +       ret = regmap_read(drv->regmap,
> +                         drv->offsets[bank] + reg_data->err_status_reg,
> +                         &err_cnt);
> +       if (ret)
> +               goto clear;
> +
> +       err_cnt &= reg_data->err_count_mask;
> +       err_cnt >>= reg_data->err_count_shift;
> +       edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error count: 0x%4x\n",
> +                   reg_data->err_name, err_cnt);
> +
> +       ret = regmap_read(drv->regmap,
> +                         drv->offsets[bank] + reg_data->err_ways_status,
> +                         &err_ways);
> +       if (ret)
> +               goto clear;
> +
> +       err_ways &= reg_data->err_ways_mask;
> +       err_ways >>= reg_data->err_ways_shift;
> +
> +       edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error ways: 0x%4x\n",
> +                   reg_data->err_name, err_ways);
> +
> +clear:
> +       ret = qcom_llcc_clear_errors_status(err_type, drv);
> +       return ret;
> +}

Nice job consolidating those 4 functions down into one.

> +
> +static int
> +dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank)
> +{
> +       struct llcc_drv_data *drv = edev_ctl->pvt_info;
> +       int ret = 0;
> +
> +       ret = dump_syn_reg_values(drv, bank, err_type);
> +       if (ret)
> +               return ret;
> +
> +       switch (err_type) {
> +       case LLCC_DRAM_CE:
> +               edac_device_handle_ce(edev_ctl, 0, bank,
> +                                     "LLCC Data RAM correctable Error");
> +               break;
> +       case LLCC_DRAM_UE:
> +               edac_device_handle_ue(edev_ctl, 0, bank,
> +                                     "LLCC Data RAM uncorrectable Error");
> +               break;
> +       case LLCC_TRAM_CE:
> +               edac_device_handle_ce(edev_ctl, 0, bank,
> +                                     "LLCC Tag RAM correctable Error");
> +               break;
> +       case LLCC_TRAM_UE:
> +               edac_device_handle_ue(edev_ctl, 0, bank,
> +                                     "LLCC Tag RAM uncorrectable Error");
> +               break;
> +       }
> +
> +       return ret;
> +}
> +
> +static irqreturn_t
> +llcc_ecc_irq_handler(int irq, void *edev_ctl)
> +{
> +       struct edac_device_ctl_info *edac_dev_ctl;
> +       irqreturn_t irq_rc = IRQ_NONE;
> +       u32 drp_error, trp_error, i;
> +       struct llcc_drv_data *drv;
> +       int ret;
> +
> +       edac_dev_ctl = (struct edac_device_ctl_info *)edev_ctl;
> +       drv = edac_dev_ctl->pvt_info;
> +
> +       for (i = 0; i < drv->num_banks; i++) {
> +               /* Look for Data RAM errors */
> +               ret = regmap_read(drv->regmap,
> +                                 drv->offsets[i] + DRP_INTERRUPT_STATUS,
> +                                 &drp_error);
> +               if (ret)
> +                       return irq_rc;
> +
> +               if (drp_error & SB_ECC_ERROR) {
> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
> +                                   "Single Bit Error detected in Data Ram\n");
> +                       ret = dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
> +                       if (!ret)
> +                               irq_rc = IRQ_HANDLED;
> +               } else if (drp_error & DB_ECC_ERROR) {
> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
> +                                   "Double Bit Error detected in Data Ram\n");
> +                       ret = dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
> +                       if (!ret)
> +                               irq_rc = IRQ_HANDLED;
> +               }
> +
> +               /* Look for Tag RAM errors */
> +               ret = regmap_read(drv->regmap,
> +                                 drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
> +                                 &trp_error);
> +               if (ret)
> +                       return irq_rc;
> +
> +               if (trp_error & SB_ECC_ERROR) {
> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
> +                                   "Single Bit Error detected in Tag Ram\n");
> +                       ret = dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
> +                       if (!ret)
> +                               irq_rc = IRQ_HANDLED;
> +               } else if (trp_error & DB_ECC_ERROR) {
> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
> +                                   "Double Bit Error detected in Tag Ram\n");
> +                       ret = dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
> +                       if (!ret)
> +                               irq_rc = IRQ_HANDLED;
> +               }
> +       }
> +
> +       return irq_rc;
> +}
> +
> +static void llcc_edac_reg_data_init(struct llcc_edac_reg_data *edac_reg)
> +{
> +
> +       struct llcc_edac_reg_data *reg_data;
> +
> +       /* Initialize register info for LLCC_DRAM_CE */
> +       reg_data = &edac_reg[LLCC_DRAM_CE];
> +       reg_data->err_name = "DRAM Single-bit";
> +       reg_data->reg_cnt = DRP_SYN_REG_CNT;
> +       reg_data->synd_reg = DRP_ECC_SB_ERR_SYN0;
> +       reg_data->err_status_reg = DRP_ECC_ERROR_STATUS1;
> +       reg_data->err_count_mask = ECC_SB_ERR_COUNT_MASK;
> +       reg_data->err_count_shift = ECC_SB_ERR_COUNT_SHIFT;
> +       reg_data->err_ways_status = DRP_ECC_ERROR_STATUS0;
> +       reg_data->err_ways_mask = ECC_SB_ERR_WAYS_MASK;
> +
> +       /* Initialize register info for LLCC_DRAM_UE */
> +       reg_data = &edac_reg[LLCC_DRAM_UE];
> +       reg_data->err_name = "DRAM Double-bit";
> +       reg_data->reg_cnt = DRP_SYN_REG_CNT;
> +       reg_data->synd_reg = DRP_ECC_DB_ERR_SYN0;
> +       reg_data->err_status_reg = DRP_ECC_ERROR_STATUS1;
> +       reg_data->err_count_mask = ECC_DB_ERR_COUNT_MASK;
> +       reg_data->err_ways_status = DRP_ECC_ERROR_STATUS0;
> +       reg_data->err_ways_mask = ECC_DB_ERR_WAYS_MASK;
> +       reg_data->err_ways_shift = ECC_DB_ERR_WAYS_SHIFT;
> +
> +       /* Initialize register info for LLCC_TRAM_CE */
> +       reg_data = &edac_reg[LLCC_TRAM_CE];
> +       reg_data->err_name = "TRAM Single-bit";
> +       reg_data->reg_cnt = TRP_SYN_REG_CNT;
> +       reg_data->synd_reg = TRP_ECC_SB_ERR_SYN0;
> +       reg_data->err_status_reg = TRP_ECC_ERROR_STATUS1;
> +       reg_data->err_count_mask = ECC_SB_ERR_COUNT_MASK;
> +       reg_data->err_count_shift = ECC_SB_ERR_COUNT_SHIFT;
> +       reg_data->err_ways_status = TRP_ECC_ERROR_STATUS0;
> +       reg_data->err_ways_mask = ECC_SB_ERR_WAYS_MASK;
> +
> +       /* Initialize register info for LLCC_TRAM_UE */
> +       reg_data = &edac_reg[LLCC_TRAM_UE];
> +       reg_data->err_name = "TRAM Double-bit";
> +       reg_data->reg_cnt = TRP_SYN_REG_CNT;
> +       reg_data->synd_reg = TRP_ECC_DB_ERR_SYN0;
> +       reg_data->err_status_reg = TRP_ECC_ERROR_STATUS1;
> +       reg_data->err_count_mask = ECC_DB_ERR_COUNT_MASK;
> +       reg_data->err_ways_status = TRP_ECC_ERROR_STATUS0;
> +       reg_data->err_ways_mask = ECC_DB_ERR_WAYS_MASK;
> +       reg_data->err_ways_shift = ECC_DB_ERR_WAYS_SHIFT;

This should all just be a statically initialized const table, there's
no need to do this in code.

> +}
> +
> +static int qcom_llcc_edac_probe(struct platform_device *pdev)
> +{
> +       struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
> +       struct edac_device_ctl_info *edev_ctl;
> +       struct device *dev = &pdev->dev;
> +       int ecc_irq;
> +       int rc;
> +
> +       /* Initialize register set for the error types*/
> +       llcc_driv_data->edac_reg = devm_kcalloc(dev, LLCC_ERR_TYPE_MAX,
> +                                       sizeof(struct llcc_edac_reg_data),
> +                                       GFP_KERNEL);
> +       llcc_edac_reg_data_init(llcc_driv_data->edac_reg);
> +
> +       rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
> +       if (rc)
> +               return rc;
> +
> +       /* Allocate edac control info */
> +       edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",
> +                                             llcc_driv_data->num_banks, 1,
> +                                             NULL, 0,
> +                                             edac_device_alloc_index());
> +
> +       if (!edev_ctl)
> +               return -ENOMEM;
> +
> +       edev_ctl->dev = dev;
> +       edev_ctl->mod_name = dev_name(dev);
> +       edev_ctl->dev_name = dev_name(dev);
> +       edev_ctl->ctl_name = "llcc";
> +       edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
> +       edev_ctl->pvt_info = llcc_driv_data;
> +
> +       rc = edac_device_add_device(edev_ctl);
> +       if (rc)
> +               goto out_mem;
> +
> +       platform_set_drvdata(pdev, edev_ctl);
> +
> +       /* Request for ecc irq */
> +       ecc_irq = llcc_driv_data->ecc_irq;
> +       if (ecc_irq < 0) {
> +               rc = -ENODEV;
> +               goto out_dev;
> +       }
> +       rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
> +                             IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl);
> +       if (rc)
> +               goto out_dev;
> +
> +       return rc;
> +
> +out_dev:
> +       edac_device_del_device(edev_ctl->dev);
> +out_mem:
> +       edac_device_free_ctl_info(edev_ctl);
> +
> +       return rc;
> +}
> +
> +static int qcom_llcc_edac_remove(struct platform_device *pdev)
> +{
> +       struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&pdev->dev);
> +
> +       edac_device_del_device(edev_ctl->dev);
> +       edac_device_free_ctl_info(edev_ctl);
> +       platform_set_drvdata(pdev, NULL);
> +
> +       return 0;
> +}
> +
> +static const struct of_device_id qcom_llcc_edac_match_table[] = {
> +#ifdef EDAC_QCOM_LLCC
> +       { .compatible = "qcom,llcc-edac" },
> +#endif
> +       { },
> +};
> +
> +static struct platform_driver qcom_llcc_edac_driver = {
> +       .probe = qcom_llcc_edac_probe,
> +       .remove = qcom_llcc_edac_remove,
> +       .driver = {
> +               .name = "qcom_llcc_edac",
> +               .of_match_table = qcom_llcc_edac_match_table,
> +       },
> +};
> +module_platform_driver(qcom_llcc_edac_driver);
> +
> +MODULE_DESCRIPTION("QCOM EDAC driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
> index 2e4b34d..25096e0 100644
> --- a/include/linux/soc/qcom/llcc-qcom.h
> +++ b/include/linux/soc/qcom/llcc-qcom.h
> @@ -84,6 +84,7 @@ struct llcc_drv_data {
>         struct regmap *regmap;
>         struct regmap *bcast_regmap;
>         const struct llcc_slice_config *cfg;
> +       struct llcc_edac_reg_data *edac_reg;

This needs a comment description.

>         struct mutex lock;
>         u32 cfg_size;
>         u32 max_slices;
> @@ -93,6 +94,30 @@ struct llcc_drv_data {
>         int ecc_irq;
>  };
>
> +/**
> + * llcc_edac_reg_data - llcc edac registers data for each error type
> + * @err_name: name of the error
> + * @reg_cnt: number of registers
> + * @synd_reg: syndrome register address
> + * @err_status_reg: Status register address to read the error count
> + * @err_count_mask: Mask value to get the error count
> + * @err_count_shift: Shift value to get the error count
> + * @err_ways_status: Status register address to read error ways
> + * @err_ways_mask: Mask value to get the error ways
> + * @err_ways_shift: Shift value to get the error ways
> + */
> +struct llcc_edac_reg_data {
> +       char *err_name;
> +       int reg_cnt;
> +       int synd_reg;
> +       int err_status_reg;
> +       int err_count_mask;
> +       int err_count_shift;
> +       int err_ways_status;
> +       int err_ways_mask;
> +       int err_ways_shift;
> +};
> +
>  #if IS_ENABLED(CONFIG_QCOM_LLCC)
>  /**
>   * llcc_slice_getd - get llcc slice descriptor
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-23 23:04   ` Evan Green
@ 2018-08-23 23:07     ` Evan Green
  2018-08-24 18:38       ` vnkgutta
  2018-08-24 18:32     ` vnkgutta
  1 sibling, 1 reply; 19+ messages in thread
From: Evan Green @ 2018-08-23 23:07 UTC (permalink / raw)
  To: vnkgutta
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On Thu, Aug 23, 2018 at 4:04 PM Evan Green <evgreen@chromium.org> wrote:
>
> On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
> <vnkgutta@codeaurora.org> wrote:
> >
> > From: Channagoud Kadabi <ckadabi@codeaurora.org>

Also checkpatch.pl complains a bit about this patch:

            WARNING: Non-standard signature: Co-developed-by:
            #14:
            Co-developed-by: Venkata Narendra Kumar Gutta
<vnkgutta@codeaurora.org>

            WARNING: please write a paragraph that describes the
config symbol fully
            #63: FILE: drivers/edac/Kconfig:460:
            +config EDAC_QCOM

            WARNING: DT compatible string "qcom,llcc-edac" appears
un-documented -- check ./Documentation/devicetree/bindings/
            #536: FILE: drivers/edac/qcom_edac.c:430:
            + { .compatible = "qcom,llcc-edac" },

            total: 0 errors, 3 warnings, 533 lines checked

-Evan

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-18  0:08 ` [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
  2018-08-23 23:04   ` Evan Green
@ 2018-08-24 16:11   ` Stephen Boyd
  2018-08-24 19:47     ` vnkgutta
  1 sibling, 1 reply; 19+ messages in thread
From: Stephen Boyd @ 2018-08-24 16:11 UTC (permalink / raw)
  To: Andy Gross, David Brown, Venkata Narendra Kumar Gutta, bp,
	ckadabi, devicetree, evgreen, linux-arm-msm, linux-edac,
	linux-kernel, linux-soc, mark.rutland, mchehab, rishabhb,
	robh+dt, robh, tsoni
  Cc: Venkata Narendra Kumar Gutta

Quoting Venkata Narendra Kumar Gutta (2018-08-17 17:08:34)
> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> index 57304b2..da8f150 100644
> --- a/drivers/edac/Kconfig
> +++ b/drivers/edac/Kconfig
> @@ -460,4 +460,32 @@ config EDAC_TI
>           Support for error detection and correction on the
>            TI SoCs.
>  
> +config EDAC_QCOM
> +       tristate "QCOM EDAC Controller"
> +       depends on EDAC
> +       help
> +         Support for error detection and correction on the
> +         QCOM SoCs.
> +
> +config EDAC_QCOM_LLCC
> +       tristate "QCOM EDAC Controller for LLCC Cache"
> +       depends on EDAC_QCOM && QCOM_LLCC
> +       help
> +         Support for error detection and correction on the
> +         QCOM LLCC cache. Report errors caught by LLCC ECC
> +         mechanism.
> +
> +         For debugging issues having to do with stability and overall system
> +          health, you should probably say 'Y' here.
> +
> +config EDAC_QCOM_LLCC_PANIC_ON_UE
> +       bool "Panic on uncorrectable errors - qcom llcc"

Why isn't this a generic option for all EDAC?

> +       depends on EDAC_QCOM_LLCC
> +       help
> +         Forcibly cause a kernel panic if an uncorrectable error (UE) is
> +         detected. This can reduce debugging times on hardware which may be
> +         operating at voltages or frequencies outside normal specification.
> +
> +         For production builds, you should probably say 'N' here.
> +
>  endif # EDAC
> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> index 02b43a7..716096d 100644
> --- a/drivers/edac/Makefile
> +++ b/drivers/edac/Makefile
> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)             += altera_edac.o
>  obj-$(CONFIG_EDAC_SYNOPSYS)            += synopsys_edac.o
>  obj-$(CONFIG_EDAC_XGENE)               += xgene_edac.o
>  obj-$(CONFIG_EDAC_TI)                  += ti_edac.o
> +obj-$(CONFIG_EDAC_QCOM)                        += qcom_edac.o

Maybe put this in sort of alphabetical order so conflicts don't happen.

> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
> new file mode 100644
> index 0000000..9a8c670
> --- /dev/null
> +++ b/drivers/edac/qcom_edac.c
> @@ -0,0 +1,446 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + */
> +
> +#include <linux/edac.h>
> +#include <linux/interrupt.h>
> +#include <linux/kernel.h>
> +#include <linux/of_device.h>

Used? Maybe it should just be linux/of.h

> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +#include <linux/smp.h>

Why?

> +#include <linux/soc/qcom/llcc-qcom.h>
> +
> +#include "edac_mc.h"
> +#include "edac_device.h"
> +
> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
> +#define LLCC_ERP_PANIC_ON_UE            1
> +#else
> +#define LLCC_ERP_PANIC_ON_UE            0
> +#endif
> +
> +#define EDAC_LLCC                       "qcom_llcc"
> +
> +#define TRP_SYN_REG_CNT                 6
> +
> +#define DRP_SYN_REG_CNT                 8
> +
> +#define LLCC_COMMON_STATUS0             0x0003000C
> +#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
> +#define LLCC_LB_CNT_SHIFT               28
> +
> +/* single & Double Bit syndrome register offsets */
> +#define TRP_ECC_SB_ERR_SYN0             0x0002304C
> +#define TRP_ECC_DB_ERR_SYN0             0x00020370
> +#define DRP_ECC_SB_ERR_SYN0             0x0004204C
> +#define DRP_ECC_DB_ERR_SYN0             0x00042070
> +
> +/* Error register offsets */
> +#define TRP_ECC_ERROR_STATUS1           0x00020348
> +#define TRP_ECC_ERROR_STATUS0           0x00020344
> +#define DRP_ECC_ERROR_STATUS1           0x00042048
> +#define DRP_ECC_ERROR_STATUS0           0x00042044
> +
> +/* TRP, DRP interrupt register offsets */
> +#define DRP_INTERRUPT_STATUS            0x00041000
> +#define TRP_INTERRUPT_0_STATUS          0x00020480
> +#define DRP_INTERRUPT_CLEAR             0x00041008
> +#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
> +#define TRP_INTERRUPT_0_CLEAR           0x00020484
> +#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
> +
> +/* Mask and shift macros */
> +#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
> +#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
> +#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
> +
> +#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
> +#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
> +#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
> +
> +#define SB_ECC_ERROR                    BIT(0)
> +#define DB_ECC_ERROR                    BIT(1)
> +
> +#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
> +#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
> +
> +/* Config registers offsets*/
> +#define DRP_ECC_ERROR_CFG               0x00040000
> +
> +/* TRP, DRP interrupt register offsets */
> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
> +#define DRP_INTERRUPT_ENABLE            0x0004100C
> +
> +#define SB_ERROR_THRESHOLD              0x1
> +#define SB_ERROR_THRESHOLD_SHIFT        24
> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
> +#define TRP0_INTERRUPT_ENABLE           0x1
> +#define DRP0_INTERRUPT_ENABLE           BIT(6)
> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
> +
> +enum {
> +       LLCC_DRAM_CE = 0,
> +       LLCC_DRAM_UE,
> +       LLCC_TRAM_CE,
> +       LLCC_TRAM_UE,
> +       LLCC_ERR_TYPE_MAX = LLCC_TRAM_UE + 1,

What's the point?

> +};
> +
> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
> +{
> +       u32 sb_err_threshold;
> +       int ret;
> +
> +       /* Enable TRP in instance 2 of common interrupt enable register */

What is TRP?

> +       ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
> +                                TRP0_INTERRUPT_ENABLE,
> +                                TRP0_INTERRUPT_ENABLE);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable ECC interrupts on Tag Ram */
> +       ret = regmap_update_bits(llcc_bcast_regmap, TRP_INTERRUPT_0_ENABLE,
> +                                SB_DB_TRP_INTERRUPT_ENABLE,
> +                                SB_DB_TRP_INTERRUPT_ENABLE);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable SB error for Data RAM */

SB is single bit?

> +       sb_err_threshold = (SB_ERROR_THRESHOLD << SB_ERROR_THRESHOLD_SHIFT);
> +       ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
> +                          sb_err_threshold);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable DRP in instance 2 of common interrupt enable register */

DRP is double bit?

> +       ret = regmap_update_bits(llcc_bcast_regmap, CMN_INTERRUPT_2_ENABLE,
> +                                DRP0_INTERRUPT_ENABLE,
> +                                DRP0_INTERRUPT_ENABLE);
> +       if (ret)
> +               return ret;
> +
> +       /* Enable ECC interrupts on Data Ram */
> +       ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
> +                          SB_DB_DRP_INTERRUPT_ENABLE);
> +       return ret;
> +}
> +
> +/* Clear the error interrupt and counter registers */
> +static int
> +qcom_llcc_clear_errors_status(int err_type, struct llcc_drv_data *drv)
> +{
> +       int ret = 0;
> +
> +       switch (err_type) {
> +       case LLCC_DRAM_CE:
> +       case LLCC_DRAM_UE:
> +               /* Clear the interrupt */
> +               ret = regmap_write(drv->bcast_regmap, DRP_INTERRUPT_CLEAR,
> +                                  DRP_TRP_INT_CLEAR);
> +               if (ret)
> +                       return ret;
> +
> +               /* Clear the counters */

A lot of these comments are just saying what the register write is doing
which is fairly obvious from the register names. Can you remove these
obvious comments?

> +               ret = regmap_write(drv->bcast_regmap, DRP_ECC_ERROR_CNTR_CLEAR,
> +                                  DRP_TRP_CNT_CLEAR);
> +               if (ret)
> +                       return ret;
> +               break;
> +       case LLCC_TRAM_CE:
> +       case LLCC_TRAM_UE:
> +               ret = regmap_write(drv->bcast_regmap, TRP_INTERRUPT_0_CLEAR,
> +                                  DRP_TRP_INT_CLEAR);
> +               if (ret)
> +                       return ret;
> +
> +               ret = regmap_write(drv->bcast_regmap, TRP_ECC_ERROR_CNTR_CLEAR,
> +                                  DRP_TRP_CNT_CLEAR);
> +               if (ret)
> +                       return ret;
> +               break;
> +       }
> +       return ret;
> +}
> +
> +/* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/
> +static int
> +dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type)
> +{
> +       struct llcc_edac_reg_data *reg_data = &(drv->edac_reg[err_type]);

const? Also, drop the useless parenthesis.

> +       int err_cnt, err_ways, ret, i;
> +       u32 synd_reg, synd_val;
> +
> +       for (i = 0; i < reg_data->reg_cnt; i++) {
> +               synd_reg = reg_data->synd_reg + (i * 4);
> +               ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg,
> +                                 &synd_val);
> +               if (ret)
> +                       goto clear;
> +               edac_printk(KERN_CRIT, EDAC_LLCC, "%s: ECC_SYN%d: 0x%8x\n",
> +                           reg_data->err_name, i, synd_val);
> +       }
> +
> +       ret = regmap_read(drv->regmap,
> +                         drv->offsets[bank] + reg_data->err_status_reg,
> +                         &err_cnt);
> +       if (ret)
> +               goto clear;
> +
> +       err_cnt &= reg_data->err_count_mask;
> +       err_cnt >>= reg_data->err_count_shift;
> +       edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error count: 0x%4x\n",
> +                   reg_data->err_name, err_cnt);
> +
> +       ret = regmap_read(drv->regmap,
> +                         drv->offsets[bank] + reg_data->err_ways_status,
> +                         &err_ways);
> +       if (ret)
> +               goto clear;
> +
> +       err_ways &= reg_data->err_ways_mask;
> +       err_ways >>= reg_data->err_ways_shift;
> +
> +       edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error ways: 0x%4x\n",
> +                   reg_data->err_name, err_ways);
> +
> +clear:
> +       ret = qcom_llcc_clear_errors_status(err_type, drv);
> +       return ret;

Just 'return qcom_llcc_clear_errors_status(...)'

> +}
> +
> +static int
> +dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 bank)
> +{
> +       struct llcc_drv_data *drv = edev_ctl->pvt_info;
> +       int ret = 0;

Please don't assign local variables at the start of a function and then
reassign them again immediately after. It hides initialization problems.

> +
> +       ret = dump_syn_reg_values(drv, bank, err_type);
> +       if (ret)
> +               return ret;
> +
> +       switch (err_type) {
> +       case LLCC_DRAM_CE:
> +               edac_device_handle_ce(edev_ctl, 0, bank,
> +                                     "LLCC Data RAM correctable Error");
> +               break;
> +       case LLCC_DRAM_UE:
> +               edac_device_handle_ue(edev_ctl, 0, bank,
> +                                     "LLCC Data RAM uncorrectable Error");
> +               break;
> +       case LLCC_TRAM_CE:
> +               edac_device_handle_ce(edev_ctl, 0, bank,
> +                                     "LLCC Tag RAM correctable Error");
> +               break;
> +       case LLCC_TRAM_UE:
> +               edac_device_handle_ue(edev_ctl, 0, bank,
> +                                     "LLCC Tag RAM uncorrectable Error");
> +               break;
> +       }
> +
> +       return ret;
> +}
> +
> +static irqreturn_t
> +llcc_ecc_irq_handler(int irq, void *edev_ctl)
> +{
> +       struct edac_device_ctl_info *edac_dev_ctl;
> +       irqreturn_t irq_rc = IRQ_NONE;
> +       u32 drp_error, trp_error, i;
> +       struct llcc_drv_data *drv;
> +       int ret;
> +
> +       edac_dev_ctl = (struct edac_device_ctl_info *)edev_ctl;

Remove useless cast please.

> +       drv = edac_dev_ctl->pvt_info;
> +
> +       for (i = 0; i < drv->num_banks; i++) {
> +               /* Look for Data RAM errors */
> +               ret = regmap_read(drv->regmap,
> +                                 drv->offsets[i] + DRP_INTERRUPT_STATUS,
> +                                 &drp_error);
> +               if (ret)
> +                       return irq_rc;
> +
> +               if (drp_error & SB_ECC_ERROR) {
> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
> +                                   "Single Bit Error detected in Data Ram\n");
> +                       ret = dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
> +                       if (!ret)
> +                               irq_rc = IRQ_HANDLED;

Rename 'irq_rc' to 'handled' and make it a bool and then break from all
these 'return irq_rc' places and 'if (handled) return IRQ_HANDLED;
return IRQ_NONE;' at the end of this function so we have one exit point
from the irq handler.

> +               } else if (drp_error & DB_ECC_ERROR) {
> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
> +                                   "Double Bit Error detected in Data Ram\n");
> +                       ret = dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
> +                       if (!ret)
> +                               irq_rc = IRQ_HANDLED;
> +               }
> +
> +               /* Look for Tag RAM errors */
> +               ret = regmap_read(drv->regmap,
> +                                 drv->offsets[i] + TRP_INTERRUPT_0_STATUS,
> +                                 &trp_error);
> +               if (ret)
> +                       return irq_rc;
> +
> +               if (trp_error & SB_ECC_ERROR) {
> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
> +                                   "Single Bit Error detected in Tag Ram\n");
> +                       ret = dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
> +                       if (!ret)
> +                               irq_rc = IRQ_HANDLED;
> +               } else if (trp_error & DB_ECC_ERROR) {
> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
> +                                   "Double Bit Error detected in Tag Ram\n");
> +                       ret = dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
> +                       if (!ret)
> +                               irq_rc = IRQ_HANDLED;
> +               }
> +       }
> +
> +       return irq_rc;
> +}
> +
> +static void llcc_edac_reg_data_init(struct llcc_edac_reg_data *edac_reg)
> +{
> +
> +       struct llcc_edac_reg_data *reg_data;
> +
> +       /* Initialize register info for LLCC_DRAM_CE */
> +       reg_data = &edac_reg[LLCC_DRAM_CE];
> +       reg_data->err_name = "DRAM Single-bit";
> +       reg_data->reg_cnt = DRP_SYN_REG_CNT;
> +       reg_data->synd_reg = DRP_ECC_SB_ERR_SYN0;
> +       reg_data->err_status_reg = DRP_ECC_ERROR_STATUS1;
> +       reg_data->err_count_mask = ECC_SB_ERR_COUNT_MASK;
> +       reg_data->err_count_shift = ECC_SB_ERR_COUNT_SHIFT;
> +       reg_data->err_ways_status = DRP_ECC_ERROR_STATUS0;
> +       reg_data->err_ways_mask = ECC_SB_ERR_WAYS_MASK;
> +
> +       /* Initialize register info for LLCC_DRAM_UE */
> +       reg_data = &edac_reg[LLCC_DRAM_UE];
> +       reg_data->err_name = "DRAM Double-bit";
> +       reg_data->reg_cnt = DRP_SYN_REG_CNT;
> +       reg_data->synd_reg = DRP_ECC_DB_ERR_SYN0;
> +       reg_data->err_status_reg = DRP_ECC_ERROR_STATUS1;
> +       reg_data->err_count_mask = ECC_DB_ERR_COUNT_MASK;
> +       reg_data->err_ways_status = DRP_ECC_ERROR_STATUS0;
> +       reg_data->err_ways_mask = ECC_DB_ERR_WAYS_MASK;
> +       reg_data->err_ways_shift = ECC_DB_ERR_WAYS_SHIFT;
> +
> +       /* Initialize register info for LLCC_TRAM_CE */
> +       reg_data = &edac_reg[LLCC_TRAM_CE];
> +       reg_data->err_name = "TRAM Single-bit";
> +       reg_data->reg_cnt = TRP_SYN_REG_CNT;
> +       reg_data->synd_reg = TRP_ECC_SB_ERR_SYN0;
> +       reg_data->err_status_reg = TRP_ECC_ERROR_STATUS1;
> +       reg_data->err_count_mask = ECC_SB_ERR_COUNT_MASK;
> +       reg_data->err_count_shift = ECC_SB_ERR_COUNT_SHIFT;
> +       reg_data->err_ways_status = TRP_ECC_ERROR_STATUS0;
> +       reg_data->err_ways_mask = ECC_SB_ERR_WAYS_MASK;
> +
> +       /* Initialize register info for LLCC_TRAM_UE */
> +       reg_data = &edac_reg[LLCC_TRAM_UE];
> +       reg_data->err_name = "TRAM Double-bit";
> +       reg_data->reg_cnt = TRP_SYN_REG_CNT;
> +       reg_data->synd_reg = TRP_ECC_DB_ERR_SYN0;
> +       reg_data->err_status_reg = TRP_ECC_ERROR_STATUS1;
> +       reg_data->err_count_mask = ECC_DB_ERR_COUNT_MASK;
> +       reg_data->err_ways_status = TRP_ECC_ERROR_STATUS0;
> +       reg_data->err_ways_mask = ECC_DB_ERR_WAYS_MASK;
> +       reg_data->err_ways_shift = ECC_DB_ERR_WAYS_SHIFT;

Why can't these things be a static const array that the driver looks up
in? What's the point of it being per-device instance?

> +}
> +
> +static int qcom_llcc_edac_probe(struct platform_device *pdev)
> +{
> +       struct llcc_drv_data *llcc_driv_data = pdev->dev.platform_data;
> +       struct edac_device_ctl_info *edev_ctl;
> +       struct device *dev = &pdev->dev;
> +       int ecc_irq;
> +       int rc;
> +
> +       /* Initialize register set for the error types*/
> +       llcc_driv_data->edac_reg = devm_kcalloc(dev, LLCC_ERR_TYPE_MAX,
> +                                       sizeof(struct llcc_edac_reg_data),
> +                                       GFP_KERNEL);
> +       llcc_edac_reg_data_init(llcc_driv_data->edac_reg);
> +
> +       rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
> +       if (rc)
> +               return rc;
> +
> +       /* Allocate edac control info */
> +       edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, "bank",
> +                                             llcc_driv_data->num_banks, 1,
> +                                             NULL, 0,
> +                                             edac_device_alloc_index());
> +
> +       if (!edev_ctl)
> +               return -ENOMEM;
> +
> +       edev_ctl->dev = dev;
> +       edev_ctl->mod_name = dev_name(dev);
> +       edev_ctl->dev_name = dev_name(dev);
> +       edev_ctl->ctl_name = "llcc";
> +       edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
> +       edev_ctl->pvt_info = llcc_driv_data;
> +
> +       rc = edac_device_add_device(edev_ctl);
> +       if (rc)
> +               goto out_mem;
> +
> +       platform_set_drvdata(pdev, edev_ctl);
> +
> +       /* Request for ecc irq */
> +       ecc_irq = llcc_driv_data->ecc_irq;
> +       if (ecc_irq < 0) {
> +               rc = -ENODEV;

Return error code from platform_get_irq()? Oh, that's weird. Why is some
other driver getting and storing the irq away? Hopefully it isn't a
shared IRQ.

> +               goto out_dev;
> +       }
> +       rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
> +                             IRQF_TRIGGER_HIGH, "llcc_ecc", edev_ctl);
> +       if (rc)
> +               goto out_dev;
> +
> +       return rc;
> +
> +out_dev:
> +       edac_device_del_device(edev_ctl->dev);
> +out_mem:
> +       edac_device_free_ctl_info(edev_ctl);
> +
> +       return rc;
> +}
> +
> +static int qcom_llcc_edac_remove(struct platform_device *pdev)
> +{
> +       struct edac_device_ctl_info *edev_ctl = dev_get_drvdata(&pdev->dev);
> +
> +       edac_device_del_device(edev_ctl->dev);
> +       edac_device_free_ctl_info(edev_ctl);
> +       platform_set_drvdata(pdev, NULL);

No need. Don't set platform data to NULL.

> +
> +       return 0;
> +}
> +
> +static const struct of_device_id qcom_llcc_edac_match_table[] = {
> +#ifdef EDAC_QCOM_LLCC

Huh? Shouldn't this driver only be compiled when this config is enabled?

> +       { .compatible = "qcom,llcc-edac" },
> +#endif
> +       { },
> +};
> +
> +static struct platform_driver qcom_llcc_edac_driver = {
> +       .probe = qcom_llcc_edac_probe,
> +       .remove = qcom_llcc_edac_remove,
> +       .driver = {
> +               .name = "qcom_llcc_edac",
> +               .of_match_table = qcom_llcc_edac_match_table,
> +       },
> +};
> +module_platform_driver(qcom_llcc_edac_driver);
> +
> +MODULE_DESCRIPTION("QCOM EDAC driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
> index 2e4b34d..25096e0 100644
> --- a/include/linux/soc/qcom/llcc-qcom.h
> +++ b/include/linux/soc/qcom/llcc-qcom.h
> @@ -84,6 +84,7 @@ struct llcc_drv_data {
>         struct regmap *regmap;
>         struct regmap *bcast_regmap;
>         const struct llcc_slice_config *cfg;
> +       struct llcc_edac_reg_data *edac_reg;

Why a pointer instead of an array of proper size?

>         struct mutex lock;
>         u32 cfg_size;
>         u32 max_slices;
> @@ -93,6 +94,30 @@ struct llcc_drv_data {
>         int ecc_irq;
>  };
>  
> +/**
> + * llcc_edac_reg_data - llcc edac registers data for each error type
> + * @err_name: name of the error
> + * @reg_cnt: number of registers
> + * @synd_reg: syndrome register address
> + * @err_status_reg: Status register address to read the error count
> + * @err_count_mask: Mask value to get the error count
> + * @err_count_shift: Shift value to get the error count
> + * @err_ways_status: Status register address to read error ways
> + * @err_ways_mask: Mask value to get the error ways
> + * @err_ways_shift: Shift value to get the error ways
> + */
> +struct llcc_edac_reg_data {
> +       char *err_name;

Just name instead?

> +       int reg_cnt;
> +       int synd_reg;
> +       int err_status_reg;
> +       int err_count_mask;
> +       int err_count_shift;
> +       int err_ways_status;
> +       int err_ways_mask;
> +       int err_ways_shift;

Do any of these need to be signed types? Use u8 for register offsets and
shifts, u32 for masks and unsigned ints for counts please.

> +};

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 2/4] drivers: soc: Add support to register LLCC EDAC driver
  2018-08-23 23:01   ` Evan Green
@ 2018-08-24 17:57     ` vnkgutta
  0 siblings, 0 replies; 19+ messages in thread
From: vnkgutta @ 2018-08-24 17:57 UTC (permalink / raw)
  To: Evan Green
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On 2018-08-23 16:01, Evan Green wrote:
> On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
> <vnkgutta@codeaurora.org> wrote:
>> 
>> Cache error reporting controller is to detect and report single
> 
> Should be "Cache error reporting controller detects and reports 
> single"...

Ok. I'll update this in next patchset.

> 
> Other than that:
> Reviewed-by: Evan Green <evgreen@chromium.org>

Thanks

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC)
  2018-08-23 23:01   ` Evan Green
@ 2018-08-24 17:58     ` vnkgutta
  0 siblings, 0 replies; 19+ messages in thread
From: vnkgutta @ 2018-08-24 17:58 UTC (permalink / raw)
  To: Evan Green
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On 2018-08-23 16:01, Evan Green wrote:
> On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
> <vnkgutta@codeaurora.org> wrote:
>> 
>> Currently, boradcast base is set to end of the LLCC banks, which may
> 
> s/boradcast/broadcast/

I'll correct this typo in the next version.

> 
>> not be correct always. As the number of banks may vary for each 
>> chipset
>> and the broadcast base could be at a different address as well. This 
>> info
>> depends on the chipset, so get the broadcast base info from the device
>> tree (DT). Add broadcast base in LLCC driver and use this for 
>> broadcast
>> writes.
>> 
>> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
>> ---
>>  drivers/soc/qcom/llcc-slice.c      | 55 
>> +++++++++++++++++++++++---------------
>>  include/linux/soc/qcom/llcc-qcom.h |  4 +--
>>  2 files changed, 35 insertions(+), 24 deletions(-)
>> 
> 
> Reviewed-by: Evan Green <evgreen@chromium.org>

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-23 23:04   ` Evan Green
  2018-08-23 23:07     ` Evan Green
@ 2018-08-24 18:32     ` vnkgutta
  2018-08-24 20:18       ` Evan Green
  1 sibling, 1 reply; 19+ messages in thread
From: vnkgutta @ 2018-08-24 18:32 UTC (permalink / raw)
  To: Evan Green
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On 2018-08-23 16:04, Evan Green wrote:
> On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
> <vnkgutta@codeaurora.org> wrote:
>> 
>> From: Channagoud Kadabi <ckadabi@codeaurora.org>
>> 
>> Add error reporting driver for Single Bit Errors (SBEs) and Double Bit
>> Errors (DBEs). As of now, this driver supports erp for Last Level 
>> Cache
>> Controller (LLCC). This driver takes care of dumping registers and 
>> adding
>> config options to enable and disable panic when the errors happen in 
>> cache.
>> 
>> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
>> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
>> Co-developed-by: Venkata Narendra Kumar Gutta 
>> <vnkgutta@codeaurora.org>
>> ---
>>  MAINTAINERS                        |   8 +
>>  drivers/edac/Kconfig               |  28 +++
>>  drivers/edac/Makefile              |   1 +
>>  drivers/edac/qcom_edac.c           | 446 
>> +++++++++++++++++++++++++++++++++++++
>>  include/linux/soc/qcom/llcc-qcom.h |  25 +++
>>  5 files changed, 508 insertions(+)
>>  create mode 100644 drivers/edac/qcom_edac.c
>> 
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 0a23427..0bff713 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -5227,6 +5227,14 @@ L:       linux-edac@vger.kernel.org
>>  S:     Maintained
>>  F:     drivers/edac/ti_edac.c
>> 
>> +EDAC-QUALCOMM
>> +M:     Channagoud Kadabi <ckadabi@codeaurora.org>
>> +M:     Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
>> +L:     linux-arm-msm@vger.kernel.org
>> +L:     linux-edac@vger.kernel.org
>> +S:     Maintained
>> +F:     drivers/edac/qcom_edac.c
>> +
>>  EDIROL UA-101/UA-1000 DRIVER
>>  M:     Clemens Ladisch <clemens@ladisch.de>
>>  L:     alsa-devel@alsa-project.org (moderated for non-subscribers)
>> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
>> index 57304b2..da8f150 100644
>> --- a/drivers/edac/Kconfig
>> +++ b/drivers/edac/Kconfig
>> @@ -460,4 +460,32 @@ config EDAC_TI
>>           Support for error detection and correction on the
>>            TI SoCs.
>> 
>> +config EDAC_QCOM
>> +       tristate "QCOM EDAC Controller"
>> +       depends on EDAC
>> +       help
>> +         Support for error detection and correction on the
>> +         QCOM SoCs.
>> +
>> +config EDAC_QCOM_LLCC
>> +       tristate "QCOM EDAC Controller for LLCC Cache"
>> +       depends on EDAC_QCOM && QCOM_LLCC
>> +       help
>> +         Support for error detection and correction on the
>> +         QCOM LLCC cache. Report errors caught by LLCC ECC
>> +         mechanism.
>> +
>> +         For debugging issues having to do with stability and overall 
>> system
>> +          health, you should probably say 'Y' here.
>> +
>> +config EDAC_QCOM_LLCC_PANIC_ON_UE
>> +       bool "Panic on uncorrectable errors - qcom llcc"
>> +       depends on EDAC_QCOM_LLCC
>> +       help
>> +         Forcibly cause a kernel panic if an uncorrectable error (UE) 
>> is
>> +         detected. This can reduce debugging times on hardware which 
>> may be
>> +         operating at voltages or frequencies outside normal 
>> specification.
>> +
>> +         For production builds, you should probably say 'N' here.
>> +
>>  endif # EDAC
>> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
>> index 02b43a7..716096d 100644
>> --- a/drivers/edac/Makefile
>> +++ b/drivers/edac/Makefile
>> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)             += 
>> altera_edac.o
>>  obj-$(CONFIG_EDAC_SYNOPSYS)            += synopsys_edac.o
>>  obj-$(CONFIG_EDAC_XGENE)               += xgene_edac.o
>>  obj-$(CONFIG_EDAC_TI)                  += ti_edac.o
>> +obj-$(CONFIG_EDAC_QCOM)                        += qcom_edac.o
>> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
>> new file mode 100644
>> index 0000000..9a8c670
>> --- /dev/null
>> +++ b/drivers/edac/qcom_edac.c
>> @@ -0,0 +1,446 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/edac.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/kernel.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/smp.h>
>> +#include <linux/soc/qcom/llcc-qcom.h>
>> +
>> +#include "edac_mc.h"
>> +#include "edac_device.h"
>> +
>> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
>> +#define LLCC_ERP_PANIC_ON_UE            1
>> +#else
>> +#define LLCC_ERP_PANIC_ON_UE            0
>> +#endif
>> +
>> +#define EDAC_LLCC                       "qcom_llcc"
>> +
>> +#define TRP_SYN_REG_CNT                 6
>> +
>> +#define DRP_SYN_REG_CNT                 8
>> +
>> +#define LLCC_COMMON_STATUS0             0x0003000C
>> +#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
>> +#define LLCC_LB_CNT_SHIFT               28
>> +
>> +/* single & Double Bit syndrome register offsets */
> 
> Strange capitalization going on here.
I'll fix this.

> 
>> +#define TRP_ECC_SB_ERR_SYN0             0x0002304C
>> +#define TRP_ECC_DB_ERR_SYN0             0x00020370
>> +#define DRP_ECC_SB_ERR_SYN0             0x0004204C
>> +#define DRP_ECC_DB_ERR_SYN0             0x00042070
> 
> I think the convention is to use lowercase hex everywhere.

I didn't get you. Do you mean, the Macros should be in lower case or the 
comments?

> 
>> +
>> +/* Error register offsets */
>> +#define TRP_ECC_ERROR_STATUS1           0x00020348
>> +#define TRP_ECC_ERROR_STATUS0           0x00020344
>> +#define DRP_ECC_ERROR_STATUS1           0x00042048
>> +#define DRP_ECC_ERROR_STATUS0           0x00042044
>> +
>> +/* TRP, DRP interrupt register offsets */
>> +#define DRP_INTERRUPT_STATUS            0x00041000
>> +#define TRP_INTERRUPT_0_STATUS          0x00020480
>> +#define DRP_INTERRUPT_CLEAR             0x00041008
>> +#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
>> +#define TRP_INTERRUPT_0_CLEAR           0x00020484
>> +#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
>> +
>> +/* Mask and shift macros */
>> +#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
>> +#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
>> +#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
>> +
>> +#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
>> +#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
>> +#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
>> +
>> +#define SB_ECC_ERROR                    BIT(0)
>> +#define DB_ECC_ERROR                    BIT(1)
>> +
>> +#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
>> +#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
>> +
>> +/* Config registers offsets*/
>> +#define DRP_ECC_ERROR_CFG               0x00040000
>> +
>> +/* TRP, DRP interrupt register offsets */
>> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
>> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
>> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
>> +#define DRP_INTERRUPT_ENABLE            0x0004100C
>> +
>> +#define SB_ERROR_THRESHOLD              0x1
>> +#define SB_ERROR_THRESHOLD_SHIFT        24
>> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
>> +#define TRP0_INTERRUPT_ENABLE           0x1
>> +#define DRP0_INTERRUPT_ENABLE           BIT(6)
>> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
>> +
>> +enum {
>> +       LLCC_DRAM_CE = 0,
>> +       LLCC_DRAM_UE,
>> +       LLCC_TRAM_CE,
>> +       LLCC_TRAM_UE,
>> +       LLCC_ERR_TYPE_MAX = LLCC_TRAM_UE + 1,
> 
> This is a nit, or perhaps personal preference, but I prefer to not
> have initializers for sentinel values, since it's one more thing
> someone could forget to update when adding new values.

I'll get rid of this, I was using this one to allocate the memory for
llcc_driv_data->edac_reg, (struct llcc_edac_reg_data).
But the suggestion was to initialize that one statically.


> 
>> +};
>> +
>> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
>> +{
>> +       u32 sb_err_threshold;
>> +       int ret;
>> +
>> +       /* Enable TRP in instance 2 of common interrupt enable 
>> register */
> 
> Can we get a comment explaining what's so special about instance 2?
> Instances 1 and 3 get no love?

I'll try to elaborate on this.

> 
>> +       ret = regmap_update_bits(llcc_bcast_regmap, 
>> CMN_INTERRUPT_2_ENABLE,
>> +                                TRP0_INTERRUPT_ENABLE,
>> +                                TRP0_INTERRUPT_ENABLE);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Enable ECC interrupts on Tag Ram */
>> +       ret = regmap_update_bits(llcc_bcast_regmap, 
>> TRP_INTERRUPT_0_ENABLE,
>> +                                SB_DB_TRP_INTERRUPT_ENABLE,
>> +                                SB_DB_TRP_INTERRUPT_ENABLE);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Enable SB error for Data RAM */
>> +       sb_err_threshold = (SB_ERROR_THRESHOLD << 
>> SB_ERROR_THRESHOLD_SHIFT);
>> +       ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
>> +                          sb_err_threshold);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Enable DRP in instance 2 of common interrupt enable 
>> register */
>> +       ret = regmap_update_bits(llcc_bcast_regmap, 
>> CMN_INTERRUPT_2_ENABLE,
>> +                                DRP0_INTERRUPT_ENABLE,
>> +                                DRP0_INTERRUPT_ENABLE);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Enable ECC interrupts on Data Ram */
>> +       ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
>> +                          SB_DB_DRP_INTERRUPT_ENABLE);
>> +       return ret;
>> +}
>> +
>> +/* Clear the error interrupt and counter registers */
>> +static int
>> +qcom_llcc_clear_errors_status(int err_type, struct llcc_drv_data 
>> *drv)
> 
> Another nit: errors_status is kind of weird. Maybe
> qcom_llcc_clear_errors or qcom_llcc_clear_error_status?

I'll update the name.

> 
>> +{
>> +       int ret = 0;
>> +
>> +       switch (err_type) {
>> +       case LLCC_DRAM_CE:
>> +       case LLCC_DRAM_UE:
>> +               /* Clear the interrupt */
>> +               ret = regmap_write(drv->bcast_regmap, 
>> DRP_INTERRUPT_CLEAR,
>> +                                  DRP_TRP_INT_CLEAR);
>> +               if (ret)
>> +                       return ret;
>> +
>> +               /* Clear the counters */
>> +               ret = regmap_write(drv->bcast_regmap, 
>> DRP_ECC_ERROR_CNTR_CLEAR,
>> +                                  DRP_TRP_CNT_CLEAR);
>> +               if (ret)
>> +                       return ret;
>> +               break;
>> +       case LLCC_TRAM_CE:
>> +       case LLCC_TRAM_UE:
>> +               ret = regmap_write(drv->bcast_regmap, 
>> TRP_INTERRUPT_0_CLEAR,
>> +                                  DRP_TRP_INT_CLEAR);
>> +               if (ret)
>> +                       return ret;
>> +
>> +               ret = regmap_write(drv->bcast_regmap, 
>> TRP_ECC_ERROR_CNTR_CLEAR,
>> +                                  DRP_TRP_CNT_CLEAR);
>> +               if (ret)
>> +                       return ret;
>> +               break;
> 
> A default case that errors or complains or both would be nice.

Ok, I had this thought too, but we never run into that scenario,
that's we don't ever call this function with any other types,
Had it been an API it makes sense to have a default case.
The internal functions require them too! I don't know!!
What do you think?
As we say, if it's good to have it, I'll add it.

> 
>> +       }
>> +       return ret;
>> +}
>> +
>> +/* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/
>> +static int
>> +dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int 
>> err_type)
>> +{
>> +       struct llcc_edac_reg_data *reg_data = 
>> &(drv->edac_reg[err_type]);
>> +       int err_cnt, err_ways, ret, i;
>> +       u32 synd_reg, synd_val;
>> +
>> +       for (i = 0; i < reg_data->reg_cnt; i++) {
>> +               synd_reg = reg_data->synd_reg + (i * 4);
>> +               ret = regmap_read(drv->regmap, drv->offsets[bank] + 
>> synd_reg,
>> +                                 &synd_val);
>> +               if (ret)
>> +                       goto clear;
>> +               edac_printk(KERN_CRIT, EDAC_LLCC, "%s: ECC_SYN%d: 
>> 0x%8x\n",
>> +                           reg_data->err_name, i, synd_val);
>> +       }
>> +
>> +       ret = regmap_read(drv->regmap,
>> +                         drv->offsets[bank] + 
>> reg_data->err_status_reg,
>> +                         &err_cnt);
>> +       if (ret)
>> +               goto clear;
>> +
>> +       err_cnt &= reg_data->err_count_mask;
>> +       err_cnt >>= reg_data->err_count_shift;
>> +       edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error count: 0x%4x\n",
>> +                   reg_data->err_name, err_cnt);
>> +
>> +       ret = regmap_read(drv->regmap,
>> +                         drv->offsets[bank] + 
>> reg_data->err_ways_status,
>> +                         &err_ways);
>> +       if (ret)
>> +               goto clear;
>> +
>> +       err_ways &= reg_data->err_ways_mask;
>> +       err_ways >>= reg_data->err_ways_shift;
>> +
>> +       edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error ways: 0x%4x\n",
>> +                   reg_data->err_name, err_ways);
>> +
>> +clear:
>> +       ret = qcom_llcc_clear_errors_status(err_type, drv);
>> +       return ret;
>> +}
> 
> Nice job consolidating those 4 functions down into one.
Thanks :)
> 
>> +
>> +static int
>> +dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 
>> bank)
>> +{
>> +       struct llcc_drv_data *drv = edev_ctl->pvt_info;
>> +       int ret = 0;
>> +
>> +       ret = dump_syn_reg_values(drv, bank, err_type);
>> +       if (ret)
>> +               return ret;
>> +
>> +       switch (err_type) {
>> +       case LLCC_DRAM_CE:
>> +               edac_device_handle_ce(edev_ctl, 0, bank,
>> +                                     "LLCC Data RAM correctable 
>> Error");
>> +               break;
>> +       case LLCC_DRAM_UE:
>> +               edac_device_handle_ue(edev_ctl, 0, bank,
>> +                                     "LLCC Data RAM uncorrectable 
>> Error");
>> +               break;
>> +       case LLCC_TRAM_CE:
>> +               edac_device_handle_ce(edev_ctl, 0, bank,
>> +                                     "LLCC Tag RAM correctable 
>> Error");
>> +               break;
>> +       case LLCC_TRAM_UE:
>> +               edac_device_handle_ue(edev_ctl, 0, bank,
>> +                                     "LLCC Tag RAM uncorrectable 
>> Error");
>> +               break;
>> +       }
>> +
>> +       return ret;
>> +}
>> +
>> +static irqreturn_t
>> +llcc_ecc_irq_handler(int irq, void *edev_ctl)
>> +{
>> +       struct edac_device_ctl_info *edac_dev_ctl;
>> +       irqreturn_t irq_rc = IRQ_NONE;
>> +       u32 drp_error, trp_error, i;
>> +       struct llcc_drv_data *drv;
>> +       int ret;
>> +
>> +       edac_dev_ctl = (struct edac_device_ctl_info *)edev_ctl;
>> +       drv = edac_dev_ctl->pvt_info;
>> +
>> +       for (i = 0; i < drv->num_banks; i++) {
>> +               /* Look for Data RAM errors */
>> +               ret = regmap_read(drv->regmap,
>> +                                 drv->offsets[i] + 
>> DRP_INTERRUPT_STATUS,
>> +                                 &drp_error);
>> +               if (ret)
>> +                       return irq_rc;
>> +
>> +               if (drp_error & SB_ECC_ERROR) {
>> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
>> +                                   "Single Bit Error detected in Data 
>> Ram\n");
>> +                       ret = dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
>> +                       if (!ret)
>> +                               irq_rc = IRQ_HANDLED;
>> +               } else if (drp_error & DB_ECC_ERROR) {
>> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
>> +                                   "Double Bit Error detected in Data 
>> Ram\n");
>> +                       ret = dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
>> +                       if (!ret)
>> +                               irq_rc = IRQ_HANDLED;
>> +               }
>> +
>> +               /* Look for Tag RAM errors */
>> +               ret = regmap_read(drv->regmap,
>> +                                 drv->offsets[i] + 
>> TRP_INTERRUPT_0_STATUS,
>> +                                 &trp_error);
>> +               if (ret)
>> +                       return irq_rc;
>> +
>> +               if (trp_error & SB_ECC_ERROR) {
>> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
>> +                                   "Single Bit Error detected in Tag 
>> Ram\n");
>> +                       ret = dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
>> +                       if (!ret)
>> +                               irq_rc = IRQ_HANDLED;
>> +               } else if (trp_error & DB_ECC_ERROR) {
>> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
>> +                                   "Double Bit Error detected in Tag 
>> Ram\n");
>> +                       ret = dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
>> +                       if (!ret)
>> +                               irq_rc = IRQ_HANDLED;
>> +               }
>> +       }
>> +
>> +       return irq_rc;
>> +}
>> +
>> +static void llcc_edac_reg_data_init(struct llcc_edac_reg_data 
>> *edac_reg)
>> +{
>> +
>> +       struct llcc_edac_reg_data *reg_data;
>> +
>> +       /* Initialize register info for LLCC_DRAM_CE */
>> +       reg_data = &edac_reg[LLCC_DRAM_CE];
>> +       reg_data->err_name = "DRAM Single-bit";
>> +       reg_data->reg_cnt = DRP_SYN_REG_CNT;
>> +       reg_data->synd_reg = DRP_ECC_SB_ERR_SYN0;
>> +       reg_data->err_status_reg = DRP_ECC_ERROR_STATUS1;
>> +       reg_data->err_count_mask = ECC_SB_ERR_COUNT_MASK;
>> +       reg_data->err_count_shift = ECC_SB_ERR_COUNT_SHIFT;
>> +       reg_data->err_ways_status = DRP_ECC_ERROR_STATUS0;
>> +       reg_data->err_ways_mask = ECC_SB_ERR_WAYS_MASK;
>> +
>> +       /* Initialize register info for LLCC_DRAM_UE */
>> +       reg_data = &edac_reg[LLCC_DRAM_UE];
>> +       reg_data->err_name = "DRAM Double-bit";
>> +       reg_data->reg_cnt = DRP_SYN_REG_CNT;
>> +       reg_data->synd_reg = DRP_ECC_DB_ERR_SYN0;
>> +       reg_data->err_status_reg = DRP_ECC_ERROR_STATUS1;
>> +       reg_data->err_count_mask = ECC_DB_ERR_COUNT_MASK;
>> +       reg_data->err_ways_status = DRP_ECC_ERROR_STATUS0;
>> +       reg_data->err_ways_mask = ECC_DB_ERR_WAYS_MASK;
>> +       reg_data->err_ways_shift = ECC_DB_ERR_WAYS_SHIFT;
>> +
>> +       /* Initialize register info for LLCC_TRAM_CE */
>> +       reg_data = &edac_reg[LLCC_TRAM_CE];
>> +       reg_data->err_name = "TRAM Single-bit";
>> +       reg_data->reg_cnt = TRP_SYN_REG_CNT;
>> +       reg_data->synd_reg = TRP_ECC_SB_ERR_SYN0;
>> +       reg_data->err_status_reg = TRP_ECC_ERROR_STATUS1;
>> +       reg_data->err_count_mask = ECC_SB_ERR_COUNT_MASK;
>> +       reg_data->err_count_shift = ECC_SB_ERR_COUNT_SHIFT;
>> +       reg_data->err_ways_status = TRP_ECC_ERROR_STATUS0;
>> +       reg_data->err_ways_mask = ECC_SB_ERR_WAYS_MASK;
>> +
>> +       /* Initialize register info for LLCC_TRAM_UE */
>> +       reg_data = &edac_reg[LLCC_TRAM_UE];
>> +       reg_data->err_name = "TRAM Double-bit";
>> +       reg_data->reg_cnt = TRP_SYN_REG_CNT;
>> +       reg_data->synd_reg = TRP_ECC_DB_ERR_SYN0;
>> +       reg_data->err_status_reg = TRP_ECC_ERROR_STATUS1;
>> +       reg_data->err_count_mask = ECC_DB_ERR_COUNT_MASK;
>> +       reg_data->err_ways_status = TRP_ECC_ERROR_STATUS0;
>> +       reg_data->err_ways_mask = ECC_DB_ERR_WAYS_MASK;
>> +       reg_data->err_ways_shift = ECC_DB_ERR_WAYS_SHIFT;
> 
> This should all just be a statically initialized const table, there's
> no need to do this in code.

We thought about this, to do it statically or dynamically and went with 
the dynamic approach.
I recollected that it's not recommended to do static initialization and 
went ahead with this one,
but as these values aren't going to be changed per instance it makes 
sense to allocate statically.

> 
>> +}
>> +
>> +static int qcom_llcc_edac_probe(struct platform_device *pdev)
>> +{
>> +       struct llcc_drv_data *llcc_driv_data = 
>> pdev->dev.platform_data;
>> +       struct edac_device_ctl_info *edev_ctl;
>> +       struct device *dev = &pdev->dev;
>> +       int ecc_irq;
>> +       int rc;
>> +
>> +       /* Initialize register set for the error types*/
>> +       llcc_driv_data->edac_reg = devm_kcalloc(dev, 
>> LLCC_ERR_TYPE_MAX,
>> +                                       sizeof(struct 
>> llcc_edac_reg_data),
>> +                                       GFP_KERNEL);
>> +       llcc_edac_reg_data_init(llcc_driv_data->edac_reg);
>> +
>> +       rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
>> +       if (rc)
>> +               return rc;
>> +
>> +       /* Allocate edac control info */
>> +       edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, 
>> "bank",
>> +                                             
>> llcc_driv_data->num_banks, 1,
>> +                                             NULL, 0,
>> +                                             
>> edac_device_alloc_index());
>> +
>> +       if (!edev_ctl)
>> +               return -ENOMEM;
>> +
>> +       edev_ctl->dev = dev;
>> +       edev_ctl->mod_name = dev_name(dev);
>> +       edev_ctl->dev_name = dev_name(dev);
>> +       edev_ctl->ctl_name = "llcc";
>> +       edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
>> +       edev_ctl->pvt_info = llcc_driv_data;
>> +
>> +       rc = edac_device_add_device(edev_ctl);
>> +       if (rc)
>> +               goto out_mem;
>> +
>> +       platform_set_drvdata(pdev, edev_ctl);
>> +
>> +       /* Request for ecc irq */
>> +       ecc_irq = llcc_driv_data->ecc_irq;
>> +       if (ecc_irq < 0) {
>> +               rc = -ENODEV;
>> +               goto out_dev;
>> +       }
>> +       rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
>> +                             IRQF_TRIGGER_HIGH, "llcc_ecc", 
>> edev_ctl);
>> +       if (rc)
>> +               goto out_dev;
>> +
>> +       return rc;
>> +
>> +out_dev:
>> +       edac_device_del_device(edev_ctl->dev);
>> +out_mem:
>> +       edac_device_free_ctl_info(edev_ctl);
>> +
>> +       return rc;
>> +}
>> +
>> +static int qcom_llcc_edac_remove(struct platform_device *pdev)
>> +{
>> +       struct edac_device_ctl_info *edev_ctl = 
>> dev_get_drvdata(&pdev->dev);
>> +
>> +       edac_device_del_device(edev_ctl->dev);
>> +       edac_device_free_ctl_info(edev_ctl);
>> +       platform_set_drvdata(pdev, NULL);
>> +
>> +       return 0;
>> +}
>> +
>> +static const struct of_device_id qcom_llcc_edac_match_table[] = {
>> +#ifdef EDAC_QCOM_LLCC
>> +       { .compatible = "qcom,llcc-edac" },
>> +#endif
>> +       { },
>> +};
>> +
>> +static struct platform_driver qcom_llcc_edac_driver = {
>> +       .probe = qcom_llcc_edac_probe,
>> +       .remove = qcom_llcc_edac_remove,
>> +       .driver = {
>> +               .name = "qcom_llcc_edac",
>> +               .of_match_table = qcom_llcc_edac_match_table,
>> +       },
>> +};
>> +module_platform_driver(qcom_llcc_edac_driver);
>> +
>> +MODULE_DESCRIPTION("QCOM EDAC driver");
>> +MODULE_LICENSE("GPL v2");
>> diff --git a/include/linux/soc/qcom/llcc-qcom.h 
>> b/include/linux/soc/qcom/llcc-qcom.h
>> index 2e4b34d..25096e0 100644
>> --- a/include/linux/soc/qcom/llcc-qcom.h
>> +++ b/include/linux/soc/qcom/llcc-qcom.h
>> @@ -84,6 +84,7 @@ struct llcc_drv_data {
>>         struct regmap *regmap;
>>         struct regmap *bcast_regmap;
>>         const struct llcc_slice_config *cfg;
>> +       struct llcc_edac_reg_data *edac_reg;
> 
> This needs a comment description.
We'll get rid of this one anyway, as we are moving this for static 
initialization.
> 
>>         struct mutex lock;
>>         u32 cfg_size;
>>         u32 max_slices;
>> @@ -93,6 +94,30 @@ struct llcc_drv_data {
>>         int ecc_irq;
>>  };
>> 
>> +/**
>> + * llcc_edac_reg_data - llcc edac registers data for each error type
>> + * @err_name: name of the error
>> + * @reg_cnt: number of registers
>> + * @synd_reg: syndrome register address
>> + * @err_status_reg: Status register address to read the error count
>> + * @err_count_mask: Mask value to get the error count
>> + * @err_count_shift: Shift value to get the error count
>> + * @err_ways_status: Status register address to read error ways
>> + * @err_ways_mask: Mask value to get the error ways
>> + * @err_ways_shift: Shift value to get the error ways
>> + */
>> +struct llcc_edac_reg_data {
>> +       char *err_name;
>> +       int reg_cnt;
>> +       int synd_reg;
>> +       int err_status_reg;
>> +       int err_count_mask;
>> +       int err_count_shift;
>> +       int err_ways_status;
>> +       int err_ways_mask;
>> +       int err_ways_shift;
>> +};
>> +
>>  #if IS_ENABLED(CONFIG_QCOM_LLCC)
>>  /**
>>   * llcc_slice_getd - get llcc slice descriptor
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora 
>> Forum,
>> a Linux Foundation Collaborative Project
>> 

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-23 23:07     ` Evan Green
@ 2018-08-24 18:38       ` vnkgutta
  0 siblings, 0 replies; 19+ messages in thread
From: vnkgutta @ 2018-08-24 18:38 UTC (permalink / raw)
  To: Evan Green
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On 2018-08-23 16:07, Evan Green wrote:
> On Thu, Aug 23, 2018 at 4:04 PM Evan Green <evgreen@chromium.org> 
> wrote:
>> 
>> On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
>> <vnkgutta@codeaurora.org> wrote:
>> >
>> > From: Channagoud Kadabi <ckadabi@codeaurora.org>
> 
> Also checkpatch.pl complains a bit about this patch:
> 
>             WARNING: Non-standard signature: Co-developed-by:
>             #14:
>             Co-developed-by: Venkata Narendra Kumar Gutta
> <vnkgutta@codeaurora.org>

This needs to be there as the original author is Channagoud Kadabi
and I'm the one who is modifying and upstreaming this driver.
It was suggested to have this kind of signature from the earlier 
patchset comments.

Can we do anything about this?

> 
>             WARNING: please write a paragraph that describes the
> config symbol fully
>             #63: FILE: drivers/edac/Kconfig:460:
>             +config EDAC_QCOM

This is also, I will check if I can get rid of this by writing more in 
the description.
I don't really understand why do we need a paragraph here.

> 
>             WARNING: DT compatible string "qcom,llcc-edac" appears
> un-documented -- check ./Documentation/devicetree/bindings/
>             #536: FILE: drivers/edac/qcom_edac.c:430:
>             + { .compatible = "qcom,llcc-edac" },

This file is not added in the dt-bindings as there are no properties 
(like reg-names or interrupts) for this driver
and anyway initialized from llcc driver.

Do we still need to have the Documentation in place?

> 
>             total: 0 errors, 3 warnings, 533 lines checked
> 
> -Evan

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-24 16:11   ` Stephen Boyd
@ 2018-08-24 19:47     ` vnkgutta
  0 siblings, 0 replies; 19+ messages in thread
From: vnkgutta @ 2018-08-24 19:47 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Andy Gross, David Brown, bp, ckadabi, devicetree, evgreen,
	linux-arm-msm, linux-edac, linux-kernel, linux-soc, mark.rutland,
	mchehab, rishabhb, robh+dt, robh, tsoni

On 2018-08-24 09:11, Stephen Boyd wrote:
> Quoting Venkata Narendra Kumar Gutta (2018-08-17 17:08:34)
>> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
>> index 57304b2..da8f150 100644
>> --- a/drivers/edac/Kconfig
>> +++ b/drivers/edac/Kconfig
>> @@ -460,4 +460,32 @@ config EDAC_TI
>>           Support for error detection and correction on the
>>            TI SoCs.
>> 
>> +config EDAC_QCOM
>> +       tristate "QCOM EDAC Controller"
>> +       depends on EDAC
>> +       help
>> +         Support for error detection and correction on the
>> +         QCOM SoCs.
>> +
>> +config EDAC_QCOM_LLCC
>> +       tristate "QCOM EDAC Controller for LLCC Cache"
>> +       depends on EDAC_QCOM && QCOM_LLCC
>> +       help
>> +         Support for error detection and correction on the
>> +         QCOM LLCC cache. Report errors caught by LLCC ECC
>> +         mechanism.
>> +
>> +         For debugging issues having to do with stability and overall 
>> system
>> +          health, you should probably say 'Y' here.
>> +
>> +config EDAC_QCOM_LLCC_PANIC_ON_UE
>> +       bool "Panic on uncorrectable errors - qcom llcc"
> 
> Why isn't this a generic option for all EDAC?

I'm not sure, I'll get back to you on this.

> 
>> +       depends on EDAC_QCOM_LLCC
>> +       help
>> +         Forcibly cause a kernel panic if an uncorrectable error (UE) 
>> is
>> +         detected. This can reduce debugging times on hardware which 
>> may be
>> +         operating at voltages or frequencies outside normal 
>> specification.
>> +
>> +         For production builds, you should probably say 'N' here.
>> +
>>  endif # EDAC
>> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
>> index 02b43a7..716096d 100644
>> --- a/drivers/edac/Makefile
>> +++ b/drivers/edac/Makefile
>> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)             += 
>> altera_edac.o
>>  obj-$(CONFIG_EDAC_SYNOPSYS)            += synopsys_edac.o
>>  obj-$(CONFIG_EDAC_XGENE)               += xgene_edac.o
>>  obj-$(CONFIG_EDAC_TI)                  += ti_edac.o
>> +obj-$(CONFIG_EDAC_QCOM)                        += qcom_edac.o
> 
> Maybe put this in sort of alphabetical order so conflicts don't happen.

None of them are in alphabetical order, so I'm not sure where to start! 
what do you suggest?

> 
>> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
>> new file mode 100644
>> index 0000000..9a8c670
>> --- /dev/null
>> +++ b/drivers/edac/qcom_edac.c
>> @@ -0,0 +1,446 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> + */
>> +
>> +#include <linux/edac.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/kernel.h>
>> +#include <linux/of_device.h>
> 
> Used? Maybe it should just be linux/of.h
Ok, I'll check and update.

> 
>> +#include <linux/platform_device.h>
>> +#include <linux/regmap.h>
>> +#include <linux/smp.h>
> 
> Why?
I'll check if this is being used, otherwise, I'll remove it.

> 
>> +#include <linux/soc/qcom/llcc-qcom.h>
>> +
>> +#include "edac_mc.h"
>> +#include "edac_device.h"
>> +
>> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
>> +#define LLCC_ERP_PANIC_ON_UE            1
>> +#else
>> +#define LLCC_ERP_PANIC_ON_UE            0
>> +#endif
>> +
>> +#define EDAC_LLCC                       "qcom_llcc"
>> +
>> +#define TRP_SYN_REG_CNT                 6
>> +
>> +#define DRP_SYN_REG_CNT                 8
>> +
>> +#define LLCC_COMMON_STATUS0             0x0003000C
>> +#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
>> +#define LLCC_LB_CNT_SHIFT               28
>> +
>> +/* single & Double Bit syndrome register offsets */
>> +#define TRP_ECC_SB_ERR_SYN0             0x0002304C
>> +#define TRP_ECC_DB_ERR_SYN0             0x00020370
>> +#define DRP_ECC_SB_ERR_SYN0             0x0004204C
>> +#define DRP_ECC_DB_ERR_SYN0             0x00042070
>> +
>> +/* Error register offsets */
>> +#define TRP_ECC_ERROR_STATUS1           0x00020348
>> +#define TRP_ECC_ERROR_STATUS0           0x00020344
>> +#define DRP_ECC_ERROR_STATUS1           0x00042048
>> +#define DRP_ECC_ERROR_STATUS0           0x00042044
>> +
>> +/* TRP, DRP interrupt register offsets */
>> +#define DRP_INTERRUPT_STATUS            0x00041000
>> +#define TRP_INTERRUPT_0_STATUS          0x00020480
>> +#define DRP_INTERRUPT_CLEAR             0x00041008
>> +#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
>> +#define TRP_INTERRUPT_0_CLEAR           0x00020484
>> +#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
>> +
>> +/* Mask and shift macros */
>> +#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
>> +#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
>> +#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
>> +
>> +#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
>> +#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
>> +#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
>> +
>> +#define SB_ECC_ERROR                    BIT(0)
>> +#define DB_ECC_ERROR                    BIT(1)
>> +
>> +#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
>> +#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
>> +
>> +/* Config registers offsets*/
>> +#define DRP_ECC_ERROR_CFG               0x00040000
>> +
>> +/* TRP, DRP interrupt register offsets */
>> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
>> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
>> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
>> +#define DRP_INTERRUPT_ENABLE            0x0004100C
>> +
>> +#define SB_ERROR_THRESHOLD              0x1
>> +#define SB_ERROR_THRESHOLD_SHIFT        24
>> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
>> +#define TRP0_INTERRUPT_ENABLE           0x1
>> +#define DRP0_INTERRUPT_ENABLE           BIT(6)
>> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
>> +
>> +enum {
>> +       LLCC_DRAM_CE = 0,
>> +       LLCC_DRAM_UE,
>> +       LLCC_TRAM_CE,
>> +       LLCC_TRAM_UE,
>> +       LLCC_ERR_TYPE_MAX = LLCC_TRAM_UE + 1,
> 
> What's the point?

I was using this to have a sentinel value for this enum, which can be 
used
initially to allocate the memory and later for any kind of error checks.

I'll remove this as we are anyway getting rid of this allocation and I'm 
not doing any error checks for now.

> 
>> +};
>> +
>> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
>> +{
>> +       u32 sb_err_threshold;
>> +       int ret;
>> +
>> +       /* Enable TRP in instance 2 of common interrupt enable 
>> register */
> 
> What is TRP?

This is in reference to Tag Ram, I'll expand this one.

> 
>> +       ret = regmap_update_bits(llcc_bcast_regmap, 
>> CMN_INTERRUPT_2_ENABLE,
>> +                                TRP0_INTERRUPT_ENABLE,
>> +                                TRP0_INTERRUPT_ENABLE);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Enable ECC interrupts on Tag Ram */
>> +       ret = regmap_update_bits(llcc_bcast_regmap, 
>> TRP_INTERRUPT_0_ENABLE,
>> +                                SB_DB_TRP_INTERRUPT_ENABLE,
>> +                                SB_DB_TRP_INTERRUPT_ENABLE);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Enable SB error for Data RAM */
> 
> SB is single bit?

Yes, Single bit, I'll expand this one.

> 
>> +       sb_err_threshold = (SB_ERROR_THRESHOLD << 
>> SB_ERROR_THRESHOLD_SHIFT);
>> +       ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
>> +                          sb_err_threshold);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Enable DRP in instance 2 of common interrupt enable 
>> register */
> 
> DRP is double bit?

No, This is in reference to Data Ram, May be I should expand this one 
too.

> 
>> +       ret = regmap_update_bits(llcc_bcast_regmap, 
>> CMN_INTERRUPT_2_ENABLE,
>> +                                DRP0_INTERRUPT_ENABLE,
>> +                                DRP0_INTERRUPT_ENABLE);
>> +       if (ret)
>> +               return ret;
>> +
>> +       /* Enable ECC interrupts on Data Ram */
>> +       ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
>> +                          SB_DB_DRP_INTERRUPT_ENABLE);
>> +       return ret;
>> +}
>> +
>> +/* Clear the error interrupt and counter registers */
>> +static int
>> +qcom_llcc_clear_errors_status(int err_type, struct llcc_drv_data 
>> *drv)
>> +{
>> +       int ret = 0;
>> +
>> +       switch (err_type) {
>> +       case LLCC_DRAM_CE:
>> +       case LLCC_DRAM_UE:
>> +               /* Clear the interrupt */
>> +               ret = regmap_write(drv->bcast_regmap, 
>> DRP_INTERRUPT_CLEAR,
>> +                                  DRP_TRP_INT_CLEAR);
>> +               if (ret)
>> +                       return ret;
>> +
>> +               /* Clear the counters */
> 
> A lot of these comments are just saying what the register write is 
> doing
> which is fairly obvious from the register names. Can you remove these
> obvious comments?

Ok, Done. I'll update this in the next patchset.

> 
>> +               ret = regmap_write(drv->bcast_regmap, 
>> DRP_ECC_ERROR_CNTR_CLEAR,
>> +                                  DRP_TRP_CNT_CLEAR);
>> +               if (ret)
>> +                       return ret;
>> +               break;
>> +       case LLCC_TRAM_CE:
>> +       case LLCC_TRAM_UE:
>> +               ret = regmap_write(drv->bcast_regmap, 
>> TRP_INTERRUPT_0_CLEAR,
>> +                                  DRP_TRP_INT_CLEAR);
>> +               if (ret)
>> +                       return ret;
>> +
>> +               ret = regmap_write(drv->bcast_regmap, 
>> TRP_ECC_ERROR_CNTR_CLEAR,
>> +                                  DRP_TRP_CNT_CLEAR);
>> +               if (ret)
>> +                       return ret;
>> +               break;
>> +       }
>> +       return ret;
>> +}
>> +
>> +/* Dump Syndrome registers data for Tag RAM, Data RAM bit errors*/
>> +static int
>> +dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int 
>> err_type)
>> +{
>> +       struct llcc_edac_reg_data *reg_data = 
>> &(drv->edac_reg[err_type]);
> 
> const? Also, drop the useless parenthesis.

Ok, done.

> 
>> +       int err_cnt, err_ways, ret, i;
>> +       u32 synd_reg, synd_val;
>> +
>> +       for (i = 0; i < reg_data->reg_cnt; i++) {
>> +               synd_reg = reg_data->synd_reg + (i * 4);
>> +               ret = regmap_read(drv->regmap, drv->offsets[bank] + 
>> synd_reg,
>> +                                 &synd_val);
>> +               if (ret)
>> +                       goto clear;
>> +               edac_printk(KERN_CRIT, EDAC_LLCC, "%s: ECC_SYN%d: 
>> 0x%8x\n",
>> +                           reg_data->err_name, i, synd_val);
>> +       }
>> +
>> +       ret = regmap_read(drv->regmap,
>> +                         drv->offsets[bank] + 
>> reg_data->err_status_reg,
>> +                         &err_cnt);
>> +       if (ret)
>> +               goto clear;
>> +
>> +       err_cnt &= reg_data->err_count_mask;
>> +       err_cnt >>= reg_data->err_count_shift;
>> +       edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error count: 0x%4x\n",
>> +                   reg_data->err_name, err_cnt);
>> +
>> +       ret = regmap_read(drv->regmap,
>> +                         drv->offsets[bank] + 
>> reg_data->err_ways_status,
>> +                         &err_ways);
>> +       if (ret)
>> +               goto clear;
>> +
>> +       err_ways &= reg_data->err_ways_mask;
>> +       err_ways >>= reg_data->err_ways_shift;
>> +
>> +       edac_printk(KERN_CRIT, EDAC_LLCC, "%s: error ways: 0x%4x\n",
>> +                   reg_data->err_name, err_ways);
>> +
>> +clear:
>> +       ret = qcom_llcc_clear_errors_status(err_type, drv);
>> +       return ret;
> 
> Just 'return qcom_llcc_clear_errors_status(...)'

Done.

> 
>> +}
>> +
>> +static int
>> +dump_syn_reg(struct edac_device_ctl_info *edev_ctl, int err_type, u32 
>> bank)
>> +{
>> +       struct llcc_drv_data *drv = edev_ctl->pvt_info;
>> +       int ret = 0;
> 
> Please don't assign local variables at the start of a function and then
> reassign them again immediately after. It hides initialization 
> problems.

I did this because the compiler was throwing some warnings, I'll try to 
get that
and see if this is really needed.

> 
>> +
>> +       ret = dump_syn_reg_values(drv, bank, err_type);
>> +       if (ret)
>> +               return ret;
>> +
>> +       switch (err_type) {
>> +       case LLCC_DRAM_CE:
>> +               edac_device_handle_ce(edev_ctl, 0, bank,
>> +                                     "LLCC Data RAM correctable 
>> Error");
>> +               break;
>> +       case LLCC_DRAM_UE:
>> +               edac_device_handle_ue(edev_ctl, 0, bank,
>> +                                     "LLCC Data RAM uncorrectable 
>> Error");
>> +               break;
>> +       case LLCC_TRAM_CE:
>> +               edac_device_handle_ce(edev_ctl, 0, bank,
>> +                                     "LLCC Tag RAM correctable 
>> Error");
>> +               break;
>> +       case LLCC_TRAM_UE:
>> +               edac_device_handle_ue(edev_ctl, 0, bank,
>> +                                     "LLCC Tag RAM uncorrectable 
>> Error");
>> +               break;
>> +       }
>> +
>> +       return ret;
>> +}
>> +
>> +static irqreturn_t
>> +llcc_ecc_irq_handler(int irq, void *edev_ctl)
>> +{
>> +       struct edac_device_ctl_info *edac_dev_ctl;
>> +       irqreturn_t irq_rc = IRQ_NONE;
>> +       u32 drp_error, trp_error, i;
>> +       struct llcc_drv_data *drv;
>> +       int ret;
>> +
>> +       edac_dev_ctl = (struct edac_device_ctl_info *)edev_ctl;
> 
> Remove useless cast please.

Forgot to update this, I'll do it.

> 
>> +       drv = edac_dev_ctl->pvt_info;
>> +
>> +       for (i = 0; i < drv->num_banks; i++) {
>> +               /* Look for Data RAM errors */
>> +               ret = regmap_read(drv->regmap,
>> +                                 drv->offsets[i] + 
>> DRP_INTERRUPT_STATUS,
>> +                                 &drp_error);
>> +               if (ret)
>> +                       return irq_rc;
>> +
>> +               if (drp_error & SB_ECC_ERROR) {
>> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
>> +                                   "Single Bit Error detected in Data 
>> Ram\n");
>> +                       ret = dump_syn_reg(edev_ctl, LLCC_DRAM_CE, i);
>> +                       if (!ret)
>> +                               irq_rc = IRQ_HANDLED;
> 
> Rename 'irq_rc' to 'handled' and make it a bool and then break from all
> these 'return irq_rc' places and 'if (handled) return IRQ_HANDLED;
> return IRQ_NONE;' at the end of this function so we have one exit point
> from the irq handler.

Ok, I'll try to optimize the logic here.

> 
>> +               } else if (drp_error & DB_ECC_ERROR) {
>> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
>> +                                   "Double Bit Error detected in Data 
>> Ram\n");
>> +                       ret = dump_syn_reg(edev_ctl, LLCC_DRAM_UE, i);
>> +                       if (!ret)
>> +                               irq_rc = IRQ_HANDLED;
>> +               }
>> +
>> +               /* Look for Tag RAM errors */
>> +               ret = regmap_read(drv->regmap,
>> +                                 drv->offsets[i] + 
>> TRP_INTERRUPT_0_STATUS,
>> +                                 &trp_error);
>> +               if (ret)
>> +                       return irq_rc;
>> +
>> +               if (trp_error & SB_ECC_ERROR) {
>> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
>> +                                   "Single Bit Error detected in Tag 
>> Ram\n");
>> +                       ret = dump_syn_reg(edev_ctl, LLCC_TRAM_CE, i);
>> +                       if (!ret)
>> +                               irq_rc = IRQ_HANDLED;
>> +               } else if (trp_error & DB_ECC_ERROR) {
>> +                       edac_printk(KERN_CRIT, EDAC_LLCC,
>> +                                   "Double Bit Error detected in Tag 
>> Ram\n");
>> +                       ret = dump_syn_reg(edev_ctl, LLCC_TRAM_UE, i);
>> +                       if (!ret)
>> +                               irq_rc = IRQ_HANDLED;
>> +               }
>> +       }
>> +
>> +       return irq_rc;
>> +}
>> +
>> +static void llcc_edac_reg_data_init(struct llcc_edac_reg_data 
>> *edac_reg)
>> +{
>> +
>> +       struct llcc_edac_reg_data *reg_data;
>> +
>> +       /* Initialize register info for LLCC_DRAM_CE */
>> +       reg_data = &edac_reg[LLCC_DRAM_CE];
>> +       reg_data->err_name = "DRAM Single-bit";
>> +       reg_data->reg_cnt = DRP_SYN_REG_CNT;
>> +       reg_data->synd_reg = DRP_ECC_SB_ERR_SYN0;
>> +       reg_data->err_status_reg = DRP_ECC_ERROR_STATUS1;
>> +       reg_data->err_count_mask = ECC_SB_ERR_COUNT_MASK;
>> +       reg_data->err_count_shift = ECC_SB_ERR_COUNT_SHIFT;
>> +       reg_data->err_ways_status = DRP_ECC_ERROR_STATUS0;
>> +       reg_data->err_ways_mask = ECC_SB_ERR_WAYS_MASK;
>> +
>> +       /* Initialize register info for LLCC_DRAM_UE */
>> +       reg_data = &edac_reg[LLCC_DRAM_UE];
>> +       reg_data->err_name = "DRAM Double-bit";
>> +       reg_data->reg_cnt = DRP_SYN_REG_CNT;
>> +       reg_data->synd_reg = DRP_ECC_DB_ERR_SYN0;
>> +       reg_data->err_status_reg = DRP_ECC_ERROR_STATUS1;
>> +       reg_data->err_count_mask = ECC_DB_ERR_COUNT_MASK;
>> +       reg_data->err_ways_status = DRP_ECC_ERROR_STATUS0;
>> +       reg_data->err_ways_mask = ECC_DB_ERR_WAYS_MASK;
>> +       reg_data->err_ways_shift = ECC_DB_ERR_WAYS_SHIFT;
>> +
>> +       /* Initialize register info for LLCC_TRAM_CE */
>> +       reg_data = &edac_reg[LLCC_TRAM_CE];
>> +       reg_data->err_name = "TRAM Single-bit";
>> +       reg_data->reg_cnt = TRP_SYN_REG_CNT;
>> +       reg_data->synd_reg = TRP_ECC_SB_ERR_SYN0;
>> +       reg_data->err_status_reg = TRP_ECC_ERROR_STATUS1;
>> +       reg_data->err_count_mask = ECC_SB_ERR_COUNT_MASK;
>> +       reg_data->err_count_shift = ECC_SB_ERR_COUNT_SHIFT;
>> +       reg_data->err_ways_status = TRP_ECC_ERROR_STATUS0;
>> +       reg_data->err_ways_mask = ECC_SB_ERR_WAYS_MASK;
>> +
>> +       /* Initialize register info for LLCC_TRAM_UE */
>> +       reg_data = &edac_reg[LLCC_TRAM_UE];
>> +       reg_data->err_name = "TRAM Double-bit";
>> +       reg_data->reg_cnt = TRP_SYN_REG_CNT;
>> +       reg_data->synd_reg = TRP_ECC_DB_ERR_SYN0;
>> +       reg_data->err_status_reg = TRP_ECC_ERROR_STATUS1;
>> +       reg_data->err_count_mask = ECC_DB_ERR_COUNT_MASK;
>> +       reg_data->err_ways_status = TRP_ECC_ERROR_STATUS0;
>> +       reg_data->err_ways_mask = ECC_DB_ERR_WAYS_MASK;
>> +       reg_data->err_ways_shift = ECC_DB_ERR_WAYS_SHIFT;
> 
> Why can't these things be a static const array that the driver looks up
> in? What's the point of it being per-device instance?

Yeah, we don't need this struct to be populated per device. That makes 
sense.
I'll make this initialization static.

> 
>> +}
>> +
>> +static int qcom_llcc_edac_probe(struct platform_device *pdev)
>> +{
>> +       struct llcc_drv_data *llcc_driv_data = 
>> pdev->dev.platform_data;
>> +       struct edac_device_ctl_info *edev_ctl;
>> +       struct device *dev = &pdev->dev;
>> +       int ecc_irq;
>> +       int rc;
>> +
>> +       /* Initialize register set for the error types*/
>> +       llcc_driv_data->edac_reg = devm_kcalloc(dev, 
>> LLCC_ERR_TYPE_MAX,
>> +                                       sizeof(struct 
>> llcc_edac_reg_data),
>> +                                       GFP_KERNEL);
>> +       llcc_edac_reg_data_init(llcc_driv_data->edac_reg);
>> +
>> +       rc = qcom_llcc_core_setup(llcc_driv_data->bcast_regmap);
>> +       if (rc)
>> +               return rc;
>> +
>> +       /* Allocate edac control info */
>> +       edev_ctl = edac_device_alloc_ctl_info(0, "qcom-llcc", 1, 
>> "bank",
>> +                                             
>> llcc_driv_data->num_banks, 1,
>> +                                             NULL, 0,
>> +                                             
>> edac_device_alloc_index());
>> +
>> +       if (!edev_ctl)
>> +               return -ENOMEM;
>> +
>> +       edev_ctl->dev = dev;
>> +       edev_ctl->mod_name = dev_name(dev);
>> +       edev_ctl->dev_name = dev_name(dev);
>> +       edev_ctl->ctl_name = "llcc";
>> +       edev_ctl->panic_on_ue = LLCC_ERP_PANIC_ON_UE;
>> +       edev_ctl->pvt_info = llcc_driv_data;
>> +
>> +       rc = edac_device_add_device(edev_ctl);
>> +       if (rc)
>> +               goto out_mem;
>> +
>> +       platform_set_drvdata(pdev, edev_ctl);
>> +
>> +       /* Request for ecc irq */
>> +       ecc_irq = llcc_driv_data->ecc_irq;
>> +       if (ecc_irq < 0) {
>> +               rc = -ENODEV;
> 
> Return error code from platform_get_irq()? Oh, that's weird. Why is 
> some/
> other driver getting and storing the irq away? Hopefully it isn't a
> shared IRQ.

No, it isn't a shared irq. LLCC EDAC platform driver is registered from 
LLCC
and the interrupt values are populated there.
Check this patch  [[PATCH v2 2/4] drivers: soc: Add support to register 
LLCC EDAC driver]


> 
>> +               goto out_dev;
>> +       }
>> +       rc = devm_request_irq(dev, ecc_irq, llcc_ecc_irq_handler,
>> +                             IRQF_TRIGGER_HIGH, "llcc_ecc", 
>> edev_ctl);
>> +       if (rc)
>> +               goto out_dev;
>> +
>> +       return rc;
>> +
>> +out_dev:
>> +       edac_device_del_device(edev_ctl->dev);
>> +out_mem:
>> +       edac_device_free_ctl_info(edev_ctl);
>> +
>> +       return rc;
>> +}
>> +
>> +static int qcom_llcc_edac_remove(struct platform_device *pdev)
>> +{
>> +       struct edac_device_ctl_info *edev_ctl = 
>> dev_get_drvdata(&pdev->dev);
>> +
>> +       edac_device_del_device(edev_ctl->dev);
>> +       edac_device_free_ctl_info(edev_ctl);
>> +       platform_set_drvdata(pdev, NULL);
> 
> No need. Don't set platform data to NULL.

Why?  I was asked to set this explicitly.
It'd be good to know why I don't need this. Is it taken care of by 
framework explicitly?

> 
>> +
>> +       return 0;
>> +}
>> +
>> +static const struct of_device_id qcom_llcc_edac_match_table[] = {
>> +#ifdef EDAC_QCOM_LLCC
> 
> Huh? Shouldn't this driver only be compiled when this config is 
> enabled?

No this driver is a generic qcom edac driver, and the llcc-edac will 
come into
picture only when this config is enabled.


We updated this as per the initial comments on to maintain this driver 
generically

> 
>> +       { .compatible = "qcom,llcc-edac" },
>> +#endif
>> +       { },
>> +};
>> +
>> +static struct platform_driver qcom_llcc_edac_driver = {
>> +       .probe = qcom_llcc_edac_probe,
>> +       .remove = qcom_llcc_edac_remove,
>> +       .driver = {
>> +               .name = "qcom_llcc_edac",
>> +               .of_match_table = qcom_llcc_edac_match_table,
>> +       },
>> +};
>> +module_platform_driver(qcom_llcc_edac_driver);
>> +
>> +MODULE_DESCRIPTION("QCOM EDAC driver");
>> +MODULE_LICENSE("GPL v2");
>> diff --git a/include/linux/soc/qcom/llcc-qcom.h 
>> b/include/linux/soc/qcom/llcc-qcom.h
>> index 2e4b34d..25096e0 100644
>> --- a/include/linux/soc/qcom/llcc-qcom.h
>> +++ b/include/linux/soc/qcom/llcc-qcom.h
>> @@ -84,6 +84,7 @@ struct llcc_drv_data {
>>         struct regmap *regmap;
>>         struct regmap *bcast_regmap;
>>         const struct llcc_slice_config *cfg;
>> +       struct llcc_edac_reg_data *edac_reg;
> 
> Why a pointer instead of an array of proper size?

I wanted to have it dynamic, so that if you want to add more error types 
you don't need to update this one.

Anyhow, I'm removing this one to make this struct initialization static.

> 
>>         struct mutex lock;
>>         u32 cfg_size;
>>         u32 max_slices;
>> @@ -93,6 +94,30 @@ struct llcc_drv_data {
>>         int ecc_irq;
>>  };
>> 
>> +/**
>> + * llcc_edac_reg_data - llcc edac registers data for each error type
>> + * @err_name: name of the error
>> + * @reg_cnt: number of registers
>> + * @synd_reg: syndrome register address
>> + * @err_status_reg: Status register address to read the error count
>> + * @err_count_mask: Mask value to get the error count
>> + * @err_count_shift: Shift value to get the error count
>> + * @err_ways_status: Status register address to read error ways
>> + * @err_ways_mask: Mask value to get the error ways
>> + * @err_ways_shift: Shift value to get the error ways
>> + */
>> +struct llcc_edac_reg_data {
>> +       char *err_name;
> 
> Just name instead?

I don't think "name" itself doesn't convey anything. I wanted to have 
better convention, hence this variable.

> 
>> +       int reg_cnt;
>> +       int synd_reg;
>> +       int err_status_reg;
>> +       int err_count_mask;
>> +       int err_count_shift;
>> +       int err_ways_status;
>> +       int err_ways_mask;
>> +       int err_ways_shift;
> 
> Do any of these need to be signed types? Use u8 for register offsets 
> and
> shifts, u32 for masks and unsigned ints for counts please.

Sure, that makes sense, I'll update the data types.

> 
>> +};

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-24 18:32     ` vnkgutta
@ 2018-08-24 20:18       ` Evan Green
  2018-08-24 21:05         ` vnkgutta
  0 siblings, 1 reply; 19+ messages in thread
From: Evan Green @ 2018-08-24 20:18 UTC (permalink / raw)
  To: vnkgutta
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On Fri, Aug 24, 2018 at 11:32 AM <vnkgutta@codeaurora.org> wrote:
>
> On 2018-08-23 16:04, Evan Green wrote:
> > On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
> > <vnkgutta@codeaurora.org> wrote:
> >>
> >> From: Channagoud Kadabi <ckadabi@codeaurora.org>
> >>
> >> Add error reporting driver for Single Bit Errors (SBEs) and Double Bit
> >> Errors (DBEs). As of now, this driver supports erp for Last Level
> >> Cache
> >> Controller (LLCC). This driver takes care of dumping registers and
> >> adding
> >> config options to enable and disable panic when the errors happen in
> >> cache.
> >>
> >> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
> >> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> >> Co-developed-by: Venkata Narendra Kumar Gutta
> >> <vnkgutta@codeaurora.org>
> >> ---
> >>  MAINTAINERS                        |   8 +
> >>  drivers/edac/Kconfig               |  28 +++
> >>  drivers/edac/Makefile              |   1 +
> >>  drivers/edac/qcom_edac.c           | 446
> >> +++++++++++++++++++++++++++++++++++++
> >>  include/linux/soc/qcom/llcc-qcom.h |  25 +++
> >>  5 files changed, 508 insertions(+)
> >>  create mode 100644 drivers/edac/qcom_edac.c
> >>
> >> diff --git a/MAINTAINERS b/MAINTAINERS
> >> index 0a23427..0bff713 100644
> >> --- a/MAINTAINERS
> >> +++ b/MAINTAINERS
> >> @@ -5227,6 +5227,14 @@ L:       linux-edac@vger.kernel.org
> >>  S:     Maintained
> >>  F:     drivers/edac/ti_edac.c
> >>
> >> +EDAC-QUALCOMM
> >> +M:     Channagoud Kadabi <ckadabi@codeaurora.org>
> >> +M:     Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
> >> +L:     linux-arm-msm@vger.kernel.org
> >> +L:     linux-edac@vger.kernel.org
> >> +S:     Maintained
> >> +F:     drivers/edac/qcom_edac.c
> >> +
> >>  EDIROL UA-101/UA-1000 DRIVER
> >>  M:     Clemens Ladisch <clemens@ladisch.de>
> >>  L:     alsa-devel@alsa-project.org (moderated for non-subscribers)
> >> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
> >> index 57304b2..da8f150 100644
> >> --- a/drivers/edac/Kconfig
> >> +++ b/drivers/edac/Kconfig
> >> @@ -460,4 +460,32 @@ config EDAC_TI
> >>           Support for error detection and correction on the
> >>            TI SoCs.
> >>
> >> +config EDAC_QCOM
> >> +       tristate "QCOM EDAC Controller"
> >> +       depends on EDAC
> >> +       help
> >> +         Support for error detection and correction on the
> >> +         QCOM SoCs.
> >> +
> >> +config EDAC_QCOM_LLCC
> >> +       tristate "QCOM EDAC Controller for LLCC Cache"
> >> +       depends on EDAC_QCOM && QCOM_LLCC
> >> +       help
> >> +         Support for error detection and correction on the
> >> +         QCOM LLCC cache. Report errors caught by LLCC ECC
> >> +         mechanism.
> >> +
> >> +         For debugging issues having to do with stability and overall
> >> system
> >> +          health, you should probably say 'Y' here.
> >> +
> >> +config EDAC_QCOM_LLCC_PANIC_ON_UE
> >> +       bool "Panic on uncorrectable errors - qcom llcc"
> >> +       depends on EDAC_QCOM_LLCC
> >> +       help
> >> +         Forcibly cause a kernel panic if an uncorrectable error (UE)
> >> is
> >> +         detected. This can reduce debugging times on hardware which
> >> may be
> >> +         operating at voltages or frequencies outside normal
> >> specification.
> >> +
> >> +         For production builds, you should probably say 'N' here.
> >> +
> >>  endif # EDAC
> >> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
> >> index 02b43a7..716096d 100644
> >> --- a/drivers/edac/Makefile
> >> +++ b/drivers/edac/Makefile
> >> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)             +=
> >> altera_edac.o
> >>  obj-$(CONFIG_EDAC_SYNOPSYS)            += synopsys_edac.o
> >>  obj-$(CONFIG_EDAC_XGENE)               += xgene_edac.o
> >>  obj-$(CONFIG_EDAC_TI)                  += ti_edac.o
> >> +obj-$(CONFIG_EDAC_QCOM)                        += qcom_edac.o
> >> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
> >> new file mode 100644
> >> index 0000000..9a8c670
> >> --- /dev/null
> >> +++ b/drivers/edac/qcom_edac.c
> >> @@ -0,0 +1,446 @@
> >> +// SPDX-License-Identifier: GPL-2.0
> >> +/*
> >> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> >> + */
> >> +
> >> +#include <linux/edac.h>
> >> +#include <linux/interrupt.h>
> >> +#include <linux/kernel.h>
> >> +#include <linux/of_device.h>
> >> +#include <linux/platform_device.h>
> >> +#include <linux/regmap.h>
> >> +#include <linux/smp.h>
> >> +#include <linux/soc/qcom/llcc-qcom.h>
> >> +
> >> +#include "edac_mc.h"
> >> +#include "edac_device.h"
> >> +
> >> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
> >> +#define LLCC_ERP_PANIC_ON_UE            1
> >> +#else
> >> +#define LLCC_ERP_PANIC_ON_UE            0
> >> +#endif
> >> +
> >> +#define EDAC_LLCC                       "qcom_llcc"
> >> +
> >> +#define TRP_SYN_REG_CNT                 6
> >> +
> >> +#define DRP_SYN_REG_CNT                 8
> >> +
> >> +#define LLCC_COMMON_STATUS0             0x0003000C
> >> +#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
> >> +#define LLCC_LB_CNT_SHIFT               28
> >> +
> >> +/* single & Double Bit syndrome register offsets */
> >
> > Strange capitalization going on here.
> I'll fix this.
>
> >
> >> +#define TRP_ECC_SB_ERR_SYN0             0x0002304C
> >> +#define TRP_ECC_DB_ERR_SYN0             0x00020370
> >> +#define DRP_ECC_SB_ERR_SYN0             0x0004204C
> >> +#define DRP_ECC_DB_ERR_SYN0             0x00042070
> >
> > I think the convention is to use lowercase hex everywhere.
>
> I didn't get you. Do you mean, the Macros should be in lower case or the
> comments?

I mean 0x0002304C should be 0x0002304c.

>
> >
> >> +
> >> +/* Error register offsets */
> >> +#define TRP_ECC_ERROR_STATUS1           0x00020348
> >> +#define TRP_ECC_ERROR_STATUS0           0x00020344
> >> +#define DRP_ECC_ERROR_STATUS1           0x00042048
> >> +#define DRP_ECC_ERROR_STATUS0           0x00042044
> >> +
> >> +/* TRP, DRP interrupt register offsets */
> >> +#define DRP_INTERRUPT_STATUS            0x00041000
> >> +#define TRP_INTERRUPT_0_STATUS          0x00020480
> >> +#define DRP_INTERRUPT_CLEAR             0x00041008
> >> +#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
> >> +#define TRP_INTERRUPT_0_CLEAR           0x00020484
> >> +#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
> >> +
> >> +/* Mask and shift macros */
> >> +#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
> >> +#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
> >> +#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
> >> +
> >> +#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
> >> +#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
> >> +#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
> >> +
> >> +#define SB_ECC_ERROR                    BIT(0)
> >> +#define DB_ECC_ERROR                    BIT(1)
> >> +
> >> +#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
> >> +#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
> >> +
> >> +/* Config registers offsets*/
> >> +#define DRP_ECC_ERROR_CFG               0x00040000
> >> +
> >> +/* TRP, DRP interrupt register offsets */
> >> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
> >> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
> >> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
> >> +#define DRP_INTERRUPT_ENABLE            0x0004100C
> >> +
> >> +#define SB_ERROR_THRESHOLD              0x1
> >> +#define SB_ERROR_THRESHOLD_SHIFT        24
> >> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
> >> +#define TRP0_INTERRUPT_ENABLE           0x1
> >> +#define DRP0_INTERRUPT_ENABLE           BIT(6)
> >> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
> >> +
> >> +enum {
> >> +       LLCC_DRAM_CE = 0,
> >> +       LLCC_DRAM_UE,
> >> +       LLCC_TRAM_CE,
> >> +       LLCC_TRAM_UE,
> >> +       LLCC_ERR_TYPE_MAX = LLCC_TRAM_UE + 1,
> >
> > This is a nit, or perhaps personal preference, but I prefer to not
> > have initializers for sentinel values, since it's one more thing
> > someone could forget to update when adding new values.
>
> I'll get rid of this, I was using this one to allocate the memory for
> llcc_driv_data->edac_reg, (struct llcc_edac_reg_data).
> But the suggestion was to initialize that one statically.

Sounds good.

>
>
> >
> >> +};
> >> +
> >> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
> >> +{
> >> +       u32 sb_err_threshold;
> >> +       int ret;
> >> +
> >> +       /* Enable TRP in instance 2 of common interrupt enable
> >> register */
> >
> > Can we get a comment explaining what's so special about instance 2?
> > Instances 1 and 3 get no love?
>
> I'll try to elaborate on this.
>
> >
> >> +       ret = regmap_update_bits(llcc_bcast_regmap,
> >> CMN_INTERRUPT_2_ENABLE,
> >> +                                TRP0_INTERRUPT_ENABLE,
> >> +                                TRP0_INTERRUPT_ENABLE);
> >> +       if (ret)
> >> +               return ret;
> >> +
> >> +       /* Enable ECC interrupts on Tag Ram */
> >> +       ret = regmap_update_bits(llcc_bcast_regmap,
> >> TRP_INTERRUPT_0_ENABLE,
> >> +                                SB_DB_TRP_INTERRUPT_ENABLE,
> >> +                                SB_DB_TRP_INTERRUPT_ENABLE);
> >> +       if (ret)
> >> +               return ret;
> >> +
> >> +       /* Enable SB error for Data RAM */
> >> +       sb_err_threshold = (SB_ERROR_THRESHOLD <<
> >> SB_ERROR_THRESHOLD_SHIFT);
> >> +       ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
> >> +                          sb_err_threshold);
> >> +       if (ret)
> >> +               return ret;
> >> +
> >> +       /* Enable DRP in instance 2 of common interrupt enable
> >> register */
> >> +       ret = regmap_update_bits(llcc_bcast_regmap,
> >> CMN_INTERRUPT_2_ENABLE,
> >> +                                DRP0_INTERRUPT_ENABLE,
> >> +                                DRP0_INTERRUPT_ENABLE);
> >> +       if (ret)
> >> +               return ret;
> >> +
> >> +       /* Enable ECC interrupts on Data Ram */
> >> +       ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
> >> +                          SB_DB_DRP_INTERRUPT_ENABLE);
> >> +       return ret;
> >> +}
> >> +
> >> +/* Clear the error interrupt and counter registers */
> >> +static int
> >> +qcom_llcc_clear_errors_status(int err_type, struct llcc_drv_data
> >> *drv)
> >
> > Another nit: errors_status is kind of weird. Maybe
> > qcom_llcc_clear_errors or qcom_llcc_clear_error_status?
>
> I'll update the name.
>
> >
> >> +{
> >> +       int ret = 0;
> >> +
> >> +       switch (err_type) {
> >> +       case LLCC_DRAM_CE:
> >> +       case LLCC_DRAM_UE:
> >> +               /* Clear the interrupt */
> >> +               ret = regmap_write(drv->bcast_regmap,
> >> DRP_INTERRUPT_CLEAR,
> >> +                                  DRP_TRP_INT_CLEAR);
> >> +               if (ret)
> >> +                       return ret;
> >> +
> >> +               /* Clear the counters */
> >> +               ret = regmap_write(drv->bcast_regmap,
> >> DRP_ECC_ERROR_CNTR_CLEAR,
> >> +                                  DRP_TRP_CNT_CLEAR);
> >> +               if (ret)
> >> +                       return ret;
> >> +               break;
> >> +       case LLCC_TRAM_CE:
> >> +       case LLCC_TRAM_UE:
> >> +               ret = regmap_write(drv->bcast_regmap,
> >> TRP_INTERRUPT_0_CLEAR,
> >> +                                  DRP_TRP_INT_CLEAR);
> >> +               if (ret)
> >> +                       return ret;
> >> +
> >> +               ret = regmap_write(drv->bcast_regmap,
> >> TRP_ECC_ERROR_CNTR_CLEAR,
> >> +                                  DRP_TRP_CNT_CLEAR);
> >> +               if (ret)
> >> +                       return ret;
> >> +               break;
> >
> > A default case that errors or complains or both would be nice.
>
> Ok, I had this thought too, but we never run into that scenario,
> that's we don't ever call this function with any other types,
> Had it been an API it makes sense to have a default case.
> The internal functions require them too! I don't know!!
> What do you think?
> As we say, if it's good to have it, I'll add it.

I personally like the default case, I find it to be defensive against
someone adding code later who passes the wrong value or type down.
Others might disagree. It's up to you.

^ permalink raw reply	[flat|nested] 19+ messages in thread

* Re: [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs
  2018-08-24 20:18       ` Evan Green
@ 2018-08-24 21:05         ` vnkgutta
  0 siblings, 0 replies; 19+ messages in thread
From: vnkgutta @ 2018-08-24 21:05 UTC (permalink / raw)
  To: Evan Green
  Cc: robh, mchehab, linux-edac, linux-kernel, Andy Gross, David Brown,
	linux-arm-msm, linux-soc, robh+dt, mark.rutland, devicetree,
	tsoni, ckadabi, rishabhb, bp

On 2018-08-24 13:18, Evan Green wrote:
> On Fri, Aug 24, 2018 at 11:32 AM <vnkgutta@codeaurora.org> wrote:
>> 
>> On 2018-08-23 16:04, Evan Green wrote:
>> > On Fri, Aug 17, 2018 at 5:08 PM Venkata Narendra Kumar Gutta
>> > <vnkgutta@codeaurora.org> wrote:
>> >>
>> >> From: Channagoud Kadabi <ckadabi@codeaurora.org>
>> >>
>> >> Add error reporting driver for Single Bit Errors (SBEs) and Double Bit
>> >> Errors (DBEs). As of now, this driver supports erp for Last Level
>> >> Cache
>> >> Controller (LLCC). This driver takes care of dumping registers and
>> >> adding
>> >> config options to enable and disable panic when the errors happen in
>> >> cache.
>> >>
>> >> Signed-off-by: Channagoud Kadabi <ckadabi@codeaurora.org>
>> >> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
>> >> Co-developed-by: Venkata Narendra Kumar Gutta
>> >> <vnkgutta@codeaurora.org>
>> >> ---
>> >>  MAINTAINERS                        |   8 +
>> >>  drivers/edac/Kconfig               |  28 +++
>> >>  drivers/edac/Makefile              |   1 +
>> >>  drivers/edac/qcom_edac.c           | 446
>> >> +++++++++++++++++++++++++++++++++++++
>> >>  include/linux/soc/qcom/llcc-qcom.h |  25 +++
>> >>  5 files changed, 508 insertions(+)
>> >>  create mode 100644 drivers/edac/qcom_edac.c
>> >>
>> >> diff --git a/MAINTAINERS b/MAINTAINERS
>> >> index 0a23427..0bff713 100644
>> >> --- a/MAINTAINERS
>> >> +++ b/MAINTAINERS
>> >> @@ -5227,6 +5227,14 @@ L:       linux-edac@vger.kernel.org
>> >>  S:     Maintained
>> >>  F:     drivers/edac/ti_edac.c
>> >>
>> >> +EDAC-QUALCOMM
>> >> +M:     Channagoud Kadabi <ckadabi@codeaurora.org>
>> >> +M:     Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org>
>> >> +L:     linux-arm-msm@vger.kernel.org
>> >> +L:     linux-edac@vger.kernel.org
>> >> +S:     Maintained
>> >> +F:     drivers/edac/qcom_edac.c
>> >> +
>> >>  EDIROL UA-101/UA-1000 DRIVER
>> >>  M:     Clemens Ladisch <clemens@ladisch.de>
>> >>  L:     alsa-devel@alsa-project.org (moderated for non-subscribers)
>> >> diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
>> >> index 57304b2..da8f150 100644
>> >> --- a/drivers/edac/Kconfig
>> >> +++ b/drivers/edac/Kconfig
>> >> @@ -460,4 +460,32 @@ config EDAC_TI
>> >>           Support for error detection and correction on the
>> >>            TI SoCs.
>> >>
>> >> +config EDAC_QCOM
>> >> +       tristate "QCOM EDAC Controller"
>> >> +       depends on EDAC
>> >> +       help
>> >> +         Support for error detection and correction on the
>> >> +         QCOM SoCs.
>> >> +
>> >> +config EDAC_QCOM_LLCC
>> >> +       tristate "QCOM EDAC Controller for LLCC Cache"
>> >> +       depends on EDAC_QCOM && QCOM_LLCC
>> >> +       help
>> >> +         Support for error detection and correction on the
>> >> +         QCOM LLCC cache. Report errors caught by LLCC ECC
>> >> +         mechanism.
>> >> +
>> >> +         For debugging issues having to do with stability and overall
>> >> system
>> >> +          health, you should probably say 'Y' here.
>> >> +
>> >> +config EDAC_QCOM_LLCC_PANIC_ON_UE
>> >> +       bool "Panic on uncorrectable errors - qcom llcc"
>> >> +       depends on EDAC_QCOM_LLCC
>> >> +       help
>> >> +         Forcibly cause a kernel panic if an uncorrectable error (UE)
>> >> is
>> >> +         detected. This can reduce debugging times on hardware which
>> >> may be
>> >> +         operating at voltages or frequencies outside normal
>> >> specification.
>> >> +
>> >> +         For production builds, you should probably say 'N' here.
>> >> +
>> >>  endif # EDAC
>> >> diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
>> >> index 02b43a7..716096d 100644
>> >> --- a/drivers/edac/Makefile
>> >> +++ b/drivers/edac/Makefile
>> >> @@ -77,3 +77,4 @@ obj-$(CONFIG_EDAC_ALTERA)             +=
>> >> altera_edac.o
>> >>  obj-$(CONFIG_EDAC_SYNOPSYS)            += synopsys_edac.o
>> >>  obj-$(CONFIG_EDAC_XGENE)               += xgene_edac.o
>> >>  obj-$(CONFIG_EDAC_TI)                  += ti_edac.o
>> >> +obj-$(CONFIG_EDAC_QCOM)                        += qcom_edac.o
>> >> diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c
>> >> new file mode 100644
>> >> index 0000000..9a8c670
>> >> --- /dev/null
>> >> +++ b/drivers/edac/qcom_edac.c
>> >> @@ -0,0 +1,446 @@
>> >> +// SPDX-License-Identifier: GPL-2.0
>> >> +/*
>> >> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
>> >> + */
>> >> +
>> >> +#include <linux/edac.h>
>> >> +#include <linux/interrupt.h>
>> >> +#include <linux/kernel.h>
>> >> +#include <linux/of_device.h>
>> >> +#include <linux/platform_device.h>
>> >> +#include <linux/regmap.h>
>> >> +#include <linux/smp.h>
>> >> +#include <linux/soc/qcom/llcc-qcom.h>
>> >> +
>> >> +#include "edac_mc.h"
>> >> +#include "edac_device.h"
>> >> +
>> >> +#ifdef CONFIG_EDAC_QCOM_LLCC_PANIC_ON_UE
>> >> +#define LLCC_ERP_PANIC_ON_UE            1
>> >> +#else
>> >> +#define LLCC_ERP_PANIC_ON_UE            0
>> >> +#endif
>> >> +
>> >> +#define EDAC_LLCC                       "qcom_llcc"
>> >> +
>> >> +#define TRP_SYN_REG_CNT                 6
>> >> +
>> >> +#define DRP_SYN_REG_CNT                 8
>> >> +
>> >> +#define LLCC_COMMON_STATUS0             0x0003000C
>> >> +#define LLCC_LB_CNT_MASK                GENMASK(31, 28)
>> >> +#define LLCC_LB_CNT_SHIFT               28
>> >> +
>> >> +/* single & Double Bit syndrome register offsets */
>> >
>> > Strange capitalization going on here.
>> I'll fix this.
>> 
>> >
>> >> +#define TRP_ECC_SB_ERR_SYN0             0x0002304C
>> >> +#define TRP_ECC_DB_ERR_SYN0             0x00020370
>> >> +#define DRP_ECC_SB_ERR_SYN0             0x0004204C
>> >> +#define DRP_ECC_DB_ERR_SYN0             0x00042070
>> >
>> > I think the convention is to use lowercase hex everywhere.
>> 
>> I didn't get you. Do you mean, the Macros should be in lower case or 
>> the
>> comments?
> 
> I mean 0x0002304C should be 0x0002304c.

Oh, I see. I'll update it, Thanks.

> 
>> 
>> >
>> >> +
>> >> +/* Error register offsets */
>> >> +#define TRP_ECC_ERROR_STATUS1           0x00020348
>> >> +#define TRP_ECC_ERROR_STATUS0           0x00020344
>> >> +#define DRP_ECC_ERROR_STATUS1           0x00042048
>> >> +#define DRP_ECC_ERROR_STATUS0           0x00042044
>> >> +
>> >> +/* TRP, DRP interrupt register offsets */
>> >> +#define DRP_INTERRUPT_STATUS            0x00041000
>> >> +#define TRP_INTERRUPT_0_STATUS          0x00020480
>> >> +#define DRP_INTERRUPT_CLEAR             0x00041008
>> >> +#define DRP_ECC_ERROR_CNTR_CLEAR        0x00040004
>> >> +#define TRP_INTERRUPT_0_CLEAR           0x00020484
>> >> +#define TRP_ECC_ERROR_CNTR_CLEAR        0x00020440
>> >> +
>> >> +/* Mask and shift macros */
>> >> +#define ECC_DB_ERR_COUNT_MASK           GENMASK(4, 0)
>> >> +#define ECC_DB_ERR_WAYS_MASK            GENMASK(31, 16)
>> >> +#define ECC_DB_ERR_WAYS_SHIFT           BIT(4)
>> >> +
>> >> +#define ECC_SB_ERR_COUNT_MASK           GENMASK(23, 16)
>> >> +#define ECC_SB_ERR_COUNT_SHIFT          BIT(4)
>> >> +#define ECC_SB_ERR_WAYS_MASK            GENMASK(15, 0)
>> >> +
>> >> +#define SB_ECC_ERROR                    BIT(0)
>> >> +#define DB_ECC_ERROR                    BIT(1)
>> >> +
>> >> +#define DRP_TRP_INT_CLEAR               GENMASK(1, 0)
>> >> +#define DRP_TRP_CNT_CLEAR               GENMASK(1, 0)
>> >> +
>> >> +/* Config registers offsets*/
>> >> +#define DRP_ECC_ERROR_CFG               0x00040000
>> >> +
>> >> +/* TRP, DRP interrupt register offsets */
>> >> +#define CMN_INTERRUPT_0_ENABLE          0x0003001C
>> >> +#define CMN_INTERRUPT_2_ENABLE          0x0003003C
>> >> +#define TRP_INTERRUPT_0_ENABLE          0x00020488
>> >> +#define DRP_INTERRUPT_ENABLE            0x0004100C
>> >> +
>> >> +#define SB_ERROR_THRESHOLD              0x1
>> >> +#define SB_ERROR_THRESHOLD_SHIFT        24
>> >> +#define SB_DB_TRP_INTERRUPT_ENABLE      0x3
>> >> +#define TRP0_INTERRUPT_ENABLE           0x1
>> >> +#define DRP0_INTERRUPT_ENABLE           BIT(6)
>> >> +#define SB_DB_DRP_INTERRUPT_ENABLE      0x3
>> >> +
>> >> +enum {
>> >> +       LLCC_DRAM_CE = 0,
>> >> +       LLCC_DRAM_UE,
>> >> +       LLCC_TRAM_CE,
>> >> +       LLCC_TRAM_UE,
>> >> +       LLCC_ERR_TYPE_MAX = LLCC_TRAM_UE + 1,
>> >
>> > This is a nit, or perhaps personal preference, but I prefer to not
>> > have initializers for sentinel values, since it's one more thing
>> > someone could forget to update when adding new values.
>> 
>> I'll get rid of this, I was using this one to allocate the memory for
>> llcc_driv_data->edac_reg, (struct llcc_edac_reg_data).
>> But the suggestion was to initialize that one statically.
> 
> Sounds good.
> 
>> 
>> 
>> >
>> >> +};
>> >> +
>> >> +static int qcom_llcc_core_setup(struct regmap *llcc_bcast_regmap)
>> >> +{
>> >> +       u32 sb_err_threshold;
>> >> +       int ret;
>> >> +
>> >> +       /* Enable TRP in instance 2 of common interrupt enable
>> >> register */
>> >
>> > Can we get a comment explaining what's so special about instance 2?
>> > Instances 1 and 3 get no love?
>> 
>> I'll try to elaborate on this.
>> 
>> >
>> >> +       ret = regmap_update_bits(llcc_bcast_regmap,
>> >> CMN_INTERRUPT_2_ENABLE,
>> >> +                                TRP0_INTERRUPT_ENABLE,
>> >> +                                TRP0_INTERRUPT_ENABLE);
>> >> +       if (ret)
>> >> +               return ret;
>> >> +
>> >> +       /* Enable ECC interrupts on Tag Ram */
>> >> +       ret = regmap_update_bits(llcc_bcast_regmap,
>> >> TRP_INTERRUPT_0_ENABLE,
>> >> +                                SB_DB_TRP_INTERRUPT_ENABLE,
>> >> +                                SB_DB_TRP_INTERRUPT_ENABLE);
>> >> +       if (ret)
>> >> +               return ret;
>> >> +
>> >> +       /* Enable SB error for Data RAM */
>> >> +       sb_err_threshold = (SB_ERROR_THRESHOLD <<
>> >> SB_ERROR_THRESHOLD_SHIFT);
>> >> +       ret = regmap_write(llcc_bcast_regmap, DRP_ECC_ERROR_CFG,
>> >> +                          sb_err_threshold);
>> >> +       if (ret)
>> >> +               return ret;
>> >> +
>> >> +       /* Enable DRP in instance 2 of common interrupt enable
>> >> register */
>> >> +       ret = regmap_update_bits(llcc_bcast_regmap,
>> >> CMN_INTERRUPT_2_ENABLE,
>> >> +                                DRP0_INTERRUPT_ENABLE,
>> >> +                                DRP0_INTERRUPT_ENABLE);
>> >> +       if (ret)
>> >> +               return ret;
>> >> +
>> >> +       /* Enable ECC interrupts on Data Ram */
>> >> +       ret = regmap_write(llcc_bcast_regmap, DRP_INTERRUPT_ENABLE,
>> >> +                          SB_DB_DRP_INTERRUPT_ENABLE);
>> >> +       return ret;
>> >> +}
>> >> +
>> >> +/* Clear the error interrupt and counter registers */
>> >> +static int
>> >> +qcom_llcc_clear_errors_status(int err_type, struct llcc_drv_data
>> >> *drv)
>> >
>> > Another nit: errors_status is kind of weird. Maybe
>> > qcom_llcc_clear_errors or qcom_llcc_clear_error_status?
>> 
>> I'll update the name.
>> 
>> >
>> >> +{
>> >> +       int ret = 0;
>> >> +
>> >> +       switch (err_type) {
>> >> +       case LLCC_DRAM_CE:
>> >> +       case LLCC_DRAM_UE:
>> >> +               /* Clear the interrupt */
>> >> +               ret = regmap_write(drv->bcast_regmap,
>> >> DRP_INTERRUPT_CLEAR,
>> >> +                                  DRP_TRP_INT_CLEAR);
>> >> +               if (ret)
>> >> +                       return ret;
>> >> +
>> >> +               /* Clear the counters */
>> >> +               ret = regmap_write(drv->bcast_regmap,
>> >> DRP_ECC_ERROR_CNTR_CLEAR,
>> >> +                                  DRP_TRP_CNT_CLEAR);
>> >> +               if (ret)
>> >> +                       return ret;
>> >> +               break;
>> >> +       case LLCC_TRAM_CE:
>> >> +       case LLCC_TRAM_UE:
>> >> +               ret = regmap_write(drv->bcast_regmap,
>> >> TRP_INTERRUPT_0_CLEAR,
>> >> +                                  DRP_TRP_INT_CLEAR);
>> >> +               if (ret)
>> >> +                       return ret;
>> >> +
>> >> +               ret = regmap_write(drv->bcast_regmap,
>> >> TRP_ECC_ERROR_CNTR_CLEAR,
>> >> +                                  DRP_TRP_CNT_CLEAR);
>> >> +               if (ret)
>> >> +                       return ret;
>> >> +               break;
>> >
>> > A default case that errors or complains or both would be nice.
>> 
>> Ok, I had this thought too, but we never run into that scenario,
>> that's we don't ever call this function with any other types,
>> Had it been an API it makes sense to have a default case.
>> The internal functions require them too! I don't know!!
>> What do you think?
>> As we say, if it's good to have it, I'll add it.
> 
> I personally like the default case, I find it to be defensive against
> someone adding code later who passes the wrong value or type down.
> Others might disagree. It's up to you.

It makes sense to have a defensive code against someone adding the code 
later,
I'll add it.

^ permalink raw reply	[flat|nested] 19+ messages in thread

end of thread, other threads:[~2018-08-24 21:05 UTC | newest]

Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-18  0:08 [PATCH v2 0/4] Add EDAC driver for QCOM SoCs Venkata Narendra Kumar Gutta
2018-08-18  0:08 ` [PATCH v2 1/4] drivers: soc: Add broadcast base for Last Level Cache Controller (LLCC) Venkata Narendra Kumar Gutta
2018-08-23 23:01   ` Evan Green
2018-08-24 17:58     ` vnkgutta
2018-08-18  0:08 ` [PATCH v2 2/4] drivers: soc: Add support to register LLCC EDAC driver Venkata Narendra Kumar Gutta
2018-08-23 23:01   ` Evan Green
2018-08-24 17:57     ` vnkgutta
2018-08-18  0:08 ` [PATCH v2 3/4] drivers: edac: Add EDAC driver support for QCOM SoCs Venkata Narendra Kumar Gutta
2018-08-23 23:04   ` Evan Green
2018-08-23 23:07     ` Evan Green
2018-08-24 18:38       ` vnkgutta
2018-08-24 18:32     ` vnkgutta
2018-08-24 20:18       ` Evan Green
2018-08-24 21:05         ` vnkgutta
2018-08-24 16:11   ` Stephen Boyd
2018-08-24 19:47     ` vnkgutta
2018-08-18  0:08 ` [PATCH v2 4/4] dt-bindigs: msm: Update documentation of qcom,llcc Venkata Narendra Kumar Gutta
2018-08-20 19:53   ` Rob Herring
2018-08-22 21:46     ` vnkgutta

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).