From: "Isaac J. Manjarres" <isaacm@codeaurora.org>
To: iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org
Cc: "Isaac J. Manjarres" <isaacm@codeaurora.org>,
joro@8bytes.org, hch@lst.de, m.szyprowski@samsung.com,
robin.murphy@arm.com, will@kernel.org, pratikp@codeaurora.org,
lmark@codeaurora.org
Subject: [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE
Date: Fri, 25 Oct 2019 17:43:36 -0700 [thread overview]
Message-ID: <1572050616-6143-1-git-send-email-isaacm@codeaurora.org> (raw)
Currently, IOMMU_QCOM_SYS_CACHE exists to allow non-coherent
I/O masters on Qualcomm SoCs to upgrade to caching their
buffers in the outer-level/system cache on these platforms.
However, these masters are limited to managing the mapping
of these buffers themselves through the IOMMU framework,
as opposed to allowing the DMA-IOMMU framework to handle it,
since there is no DMA attribute that maps to the
IOMMU_QCOM_SYS_CACHE protection bit.
Thus, introduce DMA_ATTR_SYS_CACHE so that clients
can use the DMA-IOMMU layer to map their DMA buffers with
the correct memory attributes to allow the buffers to be
cached in the outer-level/system cache.
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
---
drivers/iommu/dma-iommu.c | 2 ++
include/linux/dma-mapping.h | 8 ++++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c
index f321279..c433ece 100644
--- a/drivers/iommu/dma-iommu.c
+++ b/drivers/iommu/dma-iommu.c
@@ -369,6 +369,8 @@ static int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
if (attrs & DMA_ATTR_PRIVILEGED)
prot |= IOMMU_PRIV;
+ if (attrs & DMA_ATTR_SYS_CACHE)
+ prot |= IOMMU_QCOM_SYS_CACHE;
switch (dir) {
case DMA_BIDIRECTIONAL:
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 4a1c4fc..bdd4dcf 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -71,6 +71,14 @@
#define DMA_ATTR_PRIVILEGED (1UL << 9)
/*
+ * DMA_ATTR_SYS_CACHE: This is a hint that non-coherent masters can use to
+ * tell the DMA-IOMMU layer to map their DMA buffers with the correct memory
+ * attributes that allow these buffers to be cached in an outer-level/system
+ * cache.
+ */
+#define DMA_ATTR_SYS_CACHE (1UL << 10)
+
+/*
* A dma_addr_t can hold any valid DMA or bus address for the platform.
* It can be given to a device to use as a DMA source or target. A CPU cannot
* reference a dma_addr_t directly because there may be translation between
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next reply other threads:[~2019-10-26 0:43 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-26 0:43 Isaac J. Manjarres [this message]
2019-10-26 5:30 ` [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE Christoph Hellwig
2019-10-26 10:12 ` isaacm
2019-10-28 7:41 ` Christoph Hellwig
2019-10-28 11:24 ` Will Deacon
2019-10-28 11:37 ` Christoph Hellwig
2019-10-28 15:44 ` Will Deacon
2019-10-28 11:59 ` Robin Murphy
2019-10-28 15:34 ` Jordan Crouse
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