From: Will Deacon <will@kernel.org>
To: Christoph Hellwig <hch@lst.de>
Cc: isaacm@codeaurora.org, iommu@lists.linux-foundation.org,
linux-kernel@vger.kernel.org, joro@8bytes.org,
m.szyprowski@samsung.com, robin.murphy@arm.com,
pratikp@codeaurora.org, lmark@codeaurora.org,
jcrouse@codeaurora.org
Subject: Re: [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE
Date: Mon, 28 Oct 2019 15:44:20 +0000 [thread overview]
Message-ID: <20191028154420.GD5576@willie-the-truck> (raw)
In-Reply-To: <20191028113728.GA24055@lst.de>
On Mon, Oct 28, 2019 at 12:37:28PM +0100, Christoph Hellwig wrote:
> On Mon, Oct 28, 2019 at 11:24:58AM +0000, Will Deacon wrote:
> > Agreed. The way I /think/ it works is that on many SoCs there is a
> > system/last-level cache (LLC) which effectively sits in front of memory for
> > all masters. Even if a device isn't coherent with the CPU caches, we still
> > want to be able to allocate into the LLC. Why this doesn't happen
> > automatically is beyond me, but it appears that on these Qualcomm designs
> > you actually have to set the memory attributes up in the page-table to
> > ensure that the resulting memory transactions are non-cacheable for the CPU
> > but cacheable for the LLC. Without any changes, the transactions are
> > non-cacheable in both of them which assumedly has a performance cost.
> >
> > But you can see that I'm piecing things together myself here. Isaac?
>
> If that is the case it sounds like we'd want to drive this through
> DT properties, not the driver API. But again, without an actual consumer
> it pretty much is a moot point anyway.
I think there's certainly a DT aspect to it so that the driver knows that
the SoC is hooked up this way, but I agree that we need a consumer so that
we can figure out how dynamic this needs to be. If it's just a
fire-and-forget thing then it needn't escape the IOMMU layer, but I fear
that it's probably more flexible than that.
If nothing shows up for 5.6, I'll send a patch to remove it (since Jordan
said there was something coming soon [1])
Will
[1] http://lkml.kernel.org/r/20191024153832.GA7966@jcrouse1-lnx.qualcomm.com
next prev parent reply other threads:[~2019-10-28 15:44 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-26 0:43 [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE Isaac J. Manjarres
2019-10-26 5:30 ` Christoph Hellwig
2019-10-26 10:12 ` isaacm
2019-10-28 7:41 ` Christoph Hellwig
2019-10-28 11:24 ` Will Deacon
2019-10-28 11:37 ` Christoph Hellwig
2019-10-28 15:44 ` Will Deacon [this message]
2019-10-28 11:59 ` Robin Murphy
2019-10-28 15:34 ` Jordan Crouse
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