From: Christoph Hellwig <hch@lst.de>
To: Will Deacon <will@kernel.org>
Cc: Christoph Hellwig <hch@lst.de>,
isaacm@codeaurora.org, iommu@lists.linux-foundation.org,
linux-kernel@vger.kernel.org, joro@8bytes.org,
m.szyprowski@samsung.com, robin.murphy@arm.com,
pratikp@codeaurora.org, lmark@codeaurora.org
Subject: Re: [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE
Date: Mon, 28 Oct 2019 12:37:28 +0100 [thread overview]
Message-ID: <20191028113728.GA24055@lst.de> (raw)
In-Reply-To: <20191028112457.GB4122@willie-the-truck>
On Mon, Oct 28, 2019 at 11:24:58AM +0000, Will Deacon wrote:
> Agreed. The way I /think/ it works is that on many SoCs there is a
> system/last-level cache (LLC) which effectively sits in front of memory for
> all masters. Even if a device isn't coherent with the CPU caches, we still
> want to be able to allocate into the LLC. Why this doesn't happen
> automatically is beyond me, but it appears that on these Qualcomm designs
> you actually have to set the memory attributes up in the page-table to
> ensure that the resulting memory transactions are non-cacheable for the CPU
> but cacheable for the LLC. Without any changes, the transactions are
> non-cacheable in both of them which assumedly has a performance cost.
>
> But you can see that I'm piecing things together myself here. Isaac?
If that is the case it sounds like we'd want to drive this through
DT properties, not the driver API. But again, without an actual consumer
it pretty much is a moot point anyway.
next prev parent reply other threads:[~2019-10-28 11:37 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-26 0:43 [PATCH] iommu/dma: Add support for DMA_ATTR_SYS_CACHE Isaac J. Manjarres
2019-10-26 5:30 ` Christoph Hellwig
2019-10-26 10:12 ` isaacm
2019-10-28 7:41 ` Christoph Hellwig
2019-10-28 11:24 ` Will Deacon
2019-10-28 11:37 ` Christoph Hellwig [this message]
2019-10-28 15:44 ` Will Deacon
2019-10-28 11:59 ` Robin Murphy
2019-10-28 15:34 ` Jordan Crouse
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