* [PATCH 1/2] iommu/amd: Check feature support bit before accessing MSI capability registers
2019-11-20 13:55 [PATCH 0/2] iommu/amd: Fixes for x2APIC support Suravee Suthikulpanit
@ 2019-11-20 13:55 ` Suravee Suthikulpanit
2019-11-20 13:55 ` [PATCH 2/2] iommu/amd: Only support x2APIC with IVHD type 11h/40h Suravee Suthikulpanit
2019-12-17 9:34 ` [PATCH 0/2] iommu/amd: Fixes for x2APIC support Joerg Roedel
2 siblings, 0 replies; 4+ messages in thread
From: Suravee Suthikulpanit @ 2019-11-20 13:55 UTC (permalink / raw)
To: linux-kernel, iommu; +Cc: joro, Suravee Suthikulpanit
The IOMMU MMIO access to MSI capability registers is available only if
the EFR[MsiCapMmioSup] is set. Current implementation assumes this bit
is set if the EFR[XtSup] is set, which might not be the case.
Fix by checking the EFR[MsiCapMmioSup] before accessing the MSI address
low/high and MSI data registers via the MMIO.
Fixes: 66929812955b ('iommu/amd: Add support for X2APIC IOMMU interrupts')
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
drivers/iommu/amd_iommu_init.c | 17 ++++++++++++-----
drivers/iommu/amd_iommu_types.h | 1 +
2 files changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index 4413aa6..1dcc0b3 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -146,7 +146,7 @@ struct ivmd_header {
bool amd_iommu_irq_remap __read_mostly;
int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
-static int amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE;
+static int amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
static bool amd_iommu_detected;
static bool __initdata amd_iommu_disabled;
@@ -1531,8 +1531,15 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
- if (((h->efr_reg & (0x1 << IOMMU_EFR_XTSUP_SHIFT)) == 0))
- amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
+ /*
+ * Note: Since iommu_update_intcapxt() leverages
+ * the IOMMU MMIO access to MSI capability block registers
+ * for MSI address lo/hi/data, we need to check both
+ * EFR[XtSup] and EFR[MsiCapMmioSup] for x2APIC support.
+ */
+ if ((h->efr_reg & BIT(IOMMU_EFR_XTSUP_SHIFT)) &&
+ (h->efr_reg & BIT(IOMMU_EFR_MSICAPMMIOSUP_SHIFT)))
+ amd_iommu_xt_mode = IRQ_REMAP_X2APIC_MODE;
break;
default:
return -EINVAL;
@@ -1981,8 +1988,8 @@ static int iommu_init_intcapxt(struct amd_iommu *iommu)
struct irq_affinity_notify *notify = &iommu->intcapxt_notify;
/**
- * IntCapXT requires XTSup=1, which can be inferred
- * amd_iommu_xt_mode.
+ * IntCapXT requires XTSup=1 and MsiCapMmioSup=1,
+ * which can be inferred from amd_iommu_xt_mode.
*/
if (amd_iommu_xt_mode != IRQ_REMAP_X2APIC_MODE)
return 0;
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index 34d63af..89b0c6e 100644
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -383,6 +383,7 @@
/* IOMMU Extended Feature Register (EFR) */
#define IOMMU_EFR_XTSUP_SHIFT 2
#define IOMMU_EFR_GASUP_SHIFT 7
+#define IOMMU_EFR_MSICAPMMIOSUP_SHIFT 46
#define MAX_DOMAIN_ID 65536
--
1.8.3.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] iommu/amd: Only support x2APIC with IVHD type 11h/40h
2019-11-20 13:55 [PATCH 0/2] iommu/amd: Fixes for x2APIC support Suravee Suthikulpanit
2019-11-20 13:55 ` [PATCH 1/2] iommu/amd: Check feature support bit before accessing MSI capability registers Suravee Suthikulpanit
@ 2019-11-20 13:55 ` Suravee Suthikulpanit
2019-12-17 9:34 ` [PATCH 0/2] iommu/amd: Fixes for x2APIC support Joerg Roedel
2 siblings, 0 replies; 4+ messages in thread
From: Suravee Suthikulpanit @ 2019-11-20 13:55 UTC (permalink / raw)
To: linux-kernel, iommu; +Cc: joro, Suravee Suthikulpanit
Current implementation for IOMMU x2APIC support makes use of
the MMIO access to MSI capability block registers, which requires
checking EFR[MsiCapMmioSup]. However, only IVHD type 11h/40h contain
the information, and not in the IVHD type 10h IOMMU feature reporting
field. Since the BIOS in newer systems, which supports x2APIC, would
normally contain IVHD type 11h/40h, remove the IOMMU_FEAT_XTSUP_SHIFT
check for IVHD type 10h, and only support x2APIC with IVHD type 11h/40h.
Fixes: 66929812955b ('iommu/amd: Add support for X2APIC IOMMU interrupts')
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
drivers/iommu/amd_iommu_init.c | 2 --
drivers/iommu/amd_iommu_types.h | 1 -
2 files changed, 3 deletions(-)
diff --git a/drivers/iommu/amd_iommu_init.c b/drivers/iommu/amd_iommu_init.c
index 1dcc0b3..2be4020 100644
--- a/drivers/iommu/amd_iommu_init.c
+++ b/drivers/iommu/amd_iommu_init.c
@@ -1520,8 +1520,6 @@ static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
- if (((h->efr_attr & (0x1 << IOMMU_FEAT_XTSUP_SHIFT)) == 0))
- amd_iommu_xt_mode = IRQ_REMAP_XAPIC_MODE;
break;
case 0x11:
case 0x40:
diff --git a/drivers/iommu/amd_iommu_types.h b/drivers/iommu/amd_iommu_types.h
index 89b0c6e..3a94169 100644
--- a/drivers/iommu/amd_iommu_types.h
+++ b/drivers/iommu/amd_iommu_types.h
@@ -377,7 +377,6 @@
#define IOMMU_CAP_EFR 27
/* IOMMU Feature Reporting Field (for IVHD type 10h */
-#define IOMMU_FEAT_XTSUP_SHIFT 0
#define IOMMU_FEAT_GASUP_SHIFT 6
/* IOMMU Extended Feature Register (EFR) */
--
1.8.3.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH 0/2] iommu/amd: Fixes for x2APIC support
2019-11-20 13:55 [PATCH 0/2] iommu/amd: Fixes for x2APIC support Suravee Suthikulpanit
2019-11-20 13:55 ` [PATCH 1/2] iommu/amd: Check feature support bit before accessing MSI capability registers Suravee Suthikulpanit
2019-11-20 13:55 ` [PATCH 2/2] iommu/amd: Only support x2APIC with IVHD type 11h/40h Suravee Suthikulpanit
@ 2019-12-17 9:34 ` Joerg Roedel
2 siblings, 0 replies; 4+ messages in thread
From: Joerg Roedel @ 2019-12-17 9:34 UTC (permalink / raw)
To: Suravee Suthikulpanit; +Cc: linux-kernel, iommu
On Wed, Nov 20, 2019 at 07:55:47AM -0600, Suravee Suthikulpanit wrote:
> Adding feature support check for MMIO access to MSI capability
> block registers when enabling x2APIC (XT) mode. Also fix up logic
> for checking XT feature support for IVHD type 10h.
>
> Suravee Suthikulpanit (2):
> iommu/amd: Check feature support bit before accessing MSI capability
> registers
> iommu/amd: Only support x2APIC with IVHD type 11h/40h
Applied both, thanks Suravee.
^ permalink raw reply [flat|nested] 4+ messages in thread