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From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org
Cc: acme@kernel.org, tglx@linutronix.de, bp@alien8.de,
	namhyung@kernel.org, jolsa@redhat.com, ak@linux.intel.com,
	yao.jin@linux.intel.com, alexander.shishkin@linux.intel.com,
	adrian.hunter@intel.com, ricardo.neri-calderon@linux.intel.com,
	Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V6 06/25] perf/x86: Hybrid PMU support for counters
Date: Mon, 12 Apr 2021 07:30:46 -0700	[thread overview]
Message-ID: <1618237865-33448-7-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1618237865-33448-1-git-send-email-kan.liang@linux.intel.com>

From: Kan Liang <kan.liang@linux.intel.com>

The number of GP and fixed counters are different among hybrid PMUs.
Each hybrid PMU should use its own counter related information.

When handling a certain hybrid PMU, apply the number of counters from
the corresponding hybrid PMU.

When reserving the counters in the initialization of a new event,
reserve all possible counters.

The number of counter recored in the global x86_pmu is for the
architecture counters which are available for all hybrid PMUs. KVM
doesn't support the hybrid PMU yet. Return the number of the
architecture counters for now.

For the functions only available for the old platforms, e.g.,
intel_pmu_drain_pebs_nhm(), nothing is changed.

Reviewed-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
 arch/x86/events/core.c       | 55 ++++++++++++++++++++++++++++++--------------
 arch/x86/events/intel/core.c |  8 ++++---
 arch/x86/events/intel/ds.c   | 14 +++++++----
 arch/x86/events/perf_event.h |  4 ++++
 4 files changed, 56 insertions(+), 25 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 2382ace..3b99864 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -185,16 +185,29 @@ static DEFINE_MUTEX(pmc_reserve_mutex);
 
 #ifdef CONFIG_X86_LOCAL_APIC
 
+static inline int get_possible_num_counters(void)
+{
+	int i, num_counters = x86_pmu.num_counters;
+
+	if (!is_hybrid())
+		return num_counters;
+
+	for (i = 0; i < x86_pmu.num_hybrid_pmus; i++)
+		num_counters = max_t(int, num_counters, x86_pmu.hybrid_pmu[i].num_counters);
+
+	return num_counters;
+}
+
 static bool reserve_pmc_hardware(void)
 {
-	int i;
+	int i, num_counters = get_possible_num_counters();
 
-	for (i = 0; i < x86_pmu.num_counters; i++) {
+	for (i = 0; i < num_counters; i++) {
 		if (!reserve_perfctr_nmi(x86_pmu_event_addr(i)))
 			goto perfctr_fail;
 	}
 
-	for (i = 0; i < x86_pmu.num_counters; i++) {
+	for (i = 0; i < num_counters; i++) {
 		if (!reserve_evntsel_nmi(x86_pmu_config_addr(i)))
 			goto eventsel_fail;
 	}
@@ -205,7 +218,7 @@ static bool reserve_pmc_hardware(void)
 	for (i--; i >= 0; i--)
 		release_evntsel_nmi(x86_pmu_config_addr(i));
 
-	i = x86_pmu.num_counters;
+	i = num_counters;
 
 perfctr_fail:
 	for (i--; i >= 0; i--)
@@ -216,9 +229,9 @@ static bool reserve_pmc_hardware(void)
 
 static void release_pmc_hardware(void)
 {
-	int i;
+	int i, num_counters = get_possible_num_counters();
 
-	for (i = 0; i < x86_pmu.num_counters; i++) {
+	for (i = 0; i < num_counters; i++) {
 		release_perfctr_nmi(x86_pmu_event_addr(i));
 		release_evntsel_nmi(x86_pmu_config_addr(i));
 	}
@@ -946,6 +959,7 @@ EXPORT_SYMBOL_GPL(perf_assign_events);
 
 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 {
+	int num_counters = hybrid(cpuc->pmu, num_counters);
 	struct event_constraint *c;
 	struct perf_event *e;
 	int n0, i, wmin, wmax, unsched = 0;
@@ -1021,7 +1035,7 @@ int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 
 	/* slow path */
 	if (i != n) {
-		int gpmax = x86_pmu.num_counters;
+		int gpmax = num_counters;
 
 		/*
 		 * Do not allow scheduling of more than half the available
@@ -1042,7 +1056,7 @@ int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign)
 		 * the extra Merge events needed by large increment events.
 		 */
 		if (x86_pmu.flags & PMU_FL_PAIR) {
-			gpmax = x86_pmu.num_counters - cpuc->n_pair;
+			gpmax = num_counters - cpuc->n_pair;
 			WARN_ON(gpmax <= 0);
 		}
 
@@ -1129,10 +1143,12 @@ static int collect_event(struct cpu_hw_events *cpuc, struct perf_event *event,
  */
 static int collect_events(struct cpu_hw_events *cpuc, struct perf_event *leader, bool dogrp)
 {
+	int num_counters = hybrid(cpuc->pmu, num_counters);
+	int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
 	struct perf_event *event;
 	int n, max_count;
 
-	max_count = x86_pmu.num_counters + x86_pmu.num_counters_fixed;
+	max_count = num_counters + num_counters_fixed;
 
 	/* current number of events already accepted */
 	n = cpuc->n_events;
@@ -1500,18 +1516,18 @@ void perf_event_print_debug(void)
 {
 	u64 ctrl, status, overflow, pmc_ctrl, pmc_count, prev_left, fixed;
 	u64 pebs, debugctl;
-	struct cpu_hw_events *cpuc;
+	int cpu = smp_processor_id();
+	struct cpu_hw_events *cpuc = &per_cpu(cpu_hw_events, cpu);
+	int num_counters = hybrid(cpuc->pmu, num_counters);
+	int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
 	unsigned long flags;
-	int cpu, idx;
+	int idx;
 
-	if (!x86_pmu.num_counters)
+	if (!num_counters)
 		return;
 
 	local_irq_save(flags);
 
-	cpu = smp_processor_id();
-	cpuc = &per_cpu(cpu_hw_events, cpu);
-
 	if (x86_pmu.version >= 2) {
 		rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
 		rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
@@ -1534,7 +1550,7 @@ void perf_event_print_debug(void)
 	}
 	pr_info("CPU#%d: active:     %016llx\n", cpu, *(u64 *)cpuc->active_mask);
 
-	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
+	for (idx = 0; idx < num_counters; idx++) {
 		rdmsrl(x86_pmu_config_addr(idx), pmc_ctrl);
 		rdmsrl(x86_pmu_event_addr(idx), pmc_count);
 
@@ -1547,7 +1563,7 @@ void perf_event_print_debug(void)
 		pr_info("CPU#%d:   gen-PMC%d left:  %016llx\n",
 			cpu, idx, prev_left);
 	}
-	for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
+	for (idx = 0; idx < num_counters_fixed; idx++) {
 		if (fixed_counter_disabled(idx, cpuc->pmu))
 			continue;
 		rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, pmc_count);
@@ -2782,6 +2798,11 @@ unsigned long perf_misc_flags(struct pt_regs *regs)
 void perf_get_x86_pmu_capability(struct x86_pmu_capability *cap)
 {
 	cap->version		= x86_pmu.version;
+	/*
+	 * KVM doesn't support the hybrid PMU yet.
+	 * Return the common value in global x86_pmu,
+	 * which available for all cores.
+	 */
 	cap->num_counters_gp	= x86_pmu.num_counters;
 	cap->num_counters_fixed	= x86_pmu.num_counters_fixed;
 	cap->bit_width_gp	= x86_pmu.cntval_bits;
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 2d56055..3ea0126e 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2711,21 +2711,23 @@ static void intel_pmu_reset(void)
 {
 	struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+	int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
+	int num_counters = hybrid(cpuc->pmu, num_counters);
 	unsigned long flags;
 	int idx;
 
-	if (!x86_pmu.num_counters)
+	if (!num_counters)
 		return;
 
 	local_irq_save(flags);
 
 	pr_info("clearing PMU state on CPU#%d\n", smp_processor_id());
 
-	for (idx = 0; idx < x86_pmu.num_counters; idx++) {
+	for (idx = 0; idx < num_counters; idx++) {
 		wrmsrl_safe(x86_pmu_config_addr(idx), 0ull);
 		wrmsrl_safe(x86_pmu_event_addr(idx),  0ull);
 	}
-	for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) {
+	for (idx = 0; idx < num_counters_fixed; idx++) {
 		if (fixed_counter_disabled(idx, cpuc->pmu))
 			continue;
 		wrmsrl_safe(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index 9328aa1..312bf3b 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -1007,6 +1007,8 @@ void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
 static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
 {
 	struct debug_store *ds = cpuc->ds;
+	int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events);
+	int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
 	u64 threshold;
 	int reserved;
 
@@ -1014,9 +1016,9 @@ static inline void pebs_update_threshold(struct cpu_hw_events *cpuc)
 		return;
 
 	if (x86_pmu.flags & PMU_FL_PEBS_ALL)
-		reserved = x86_pmu.max_pebs_events + x86_pmu.num_counters_fixed;
+		reserved = max_pebs_events + num_counters_fixed;
 	else
-		reserved = x86_pmu.max_pebs_events;
+		reserved = max_pebs_events;
 
 	if (cpuc->n_pebs == cpuc->n_large_pebs) {
 		threshold = ds->pebs_absolute_maximum -
@@ -2072,6 +2074,8 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
 {
 	short counts[INTEL_PMC_IDX_FIXED + MAX_FIXED_PEBS_EVENTS] = {};
 	struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
+	int max_pebs_events = hybrid(cpuc->pmu, max_pebs_events);
+	int num_counters_fixed = hybrid(cpuc->pmu, num_counters_fixed);
 	struct debug_store *ds = cpuc->ds;
 	struct perf_event *event;
 	void *base, *at, *top;
@@ -2086,9 +2090,9 @@ static void intel_pmu_drain_pebs_icl(struct pt_regs *iregs, struct perf_sample_d
 
 	ds->pebs_index = ds->pebs_buffer_base;
 
-	mask = ((1ULL << x86_pmu.max_pebs_events) - 1) |
-	       (((1ULL << x86_pmu.num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED);
-	size = INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed;
+	mask = ((1ULL << max_pebs_events) - 1) |
+	       (((1ULL << num_counters_fixed) - 1) << INTEL_PMC_IDX_FIXED);
+	size = INTEL_PMC_IDX_FIXED + num_counters_fixed;
 
 	if (unlikely(base >= top)) {
 		intel_pmu_pebs_event_update_no_drain(cpuc, size);
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 059a1e1..df3689b 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -636,6 +636,9 @@ struct x86_hybrid_pmu {
 	struct pmu			pmu;
 	union perf_capabilities		intel_cap;
 	u64				intel_ctrl;
+	int				max_pebs_events;
+	int				num_counters;
+	int				num_counters_fixed;
 };
 
 static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu)
@@ -851,6 +854,7 @@ struct x86_pmu {
 	 * are available for all PMUs. The hybrid_pmu only includes the
 	 * unique capabilities.
 	 */
+	int				num_hybrid_pmus;
 	struct x86_hybrid_pmu		*hybrid_pmu;
 };
 
-- 
2.7.4


  parent reply	other threads:[~2021-04-12 14:38 UTC|newest]

Thread overview: 51+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-12 14:30 [PATCH V6 00/25] Add Alder Lake support for perf (kernel) kan.liang
2021-04-12 14:30 ` [PATCH V6 01/25] x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Ricardo Neri
2021-04-12 14:30 ` [PATCH V6 02/25] x86/cpu: Add helper function to get the type of the current hybrid CPU kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Ricardo Neri
2021-04-12 14:30 ` [PATCH V6 03/25] perf/x86: Track pmu in per-CPU cpu_hw_events kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 05/25] perf/x86: Hybrid PMU support for intel_ctrl kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` kan.liang [this message]
2021-04-20 10:46   ` [tip: perf/core] perf/x86: Hybrid PMU support for counters tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 07/25] perf/x86: Hybrid PMU support for unconstrained kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 08/25] perf/x86: Hybrid PMU support for hardware cache event kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 09/25] perf/x86: Hybrid PMU support for event constraints kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 10/25] perf/x86: Hybrid PMU support for extra_regs kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 11/25] perf/x86/intel: Factor out intel_pmu_check_num_counters kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 12/25] perf/x86/intel: Factor out intel_pmu_check_event_constraints kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 13/25] perf/x86/intel: Factor out intel_pmu_check_extra_regs kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 14/25] perf/x86: Remove temporary pmu assignment in event_init kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 16/25] perf/x86: Register hybrid PMUs kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 17/25] perf/x86: Add structures for the attributes of Hybrid PMUs kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 18/25] perf/x86/intel: Add attr_update for " kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:30 ` [PATCH V6 19/25] perf/x86: Support filter_match callback kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:31 ` [PATCH V6 20/25] perf/x86/intel: Add Alder Lake Hybrid support kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:31 ` [PATCH V6 21/25] perf: Extend PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:31 ` [PATCH V6 22/25] perf/x86/intel/uncore: Add Alder Lake support kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:31 ` [PATCH V6 23/25] perf/x86/msr: Add Alder Lake CPU support kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:31 ` [PATCH V6 24/25] perf/x86/cstate: " kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Kan Liang
2021-04-12 14:31 ` [PATCH V6 25/25] perf/x86/rapl: Add support for Intel Alder Lake kan.liang
2021-04-20 10:46   ` [tip: perf/core] " tip-bot2 for Zhang Rui

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