From: kan.liang@linux.intel.com To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org Cc: acme@kernel.org, tglx@linutronix.de, bp@alien8.de, namhyung@kernel.org, jolsa@redhat.com, ak@linux.intel.com, yao.jin@linux.intel.com, alexander.shishkin@linux.intel.com, adrian.hunter@intel.com, ricardo.neri-calderon@linux.intel.com, Kan Liang <kan.liang@linux.intel.com> Subject: [PATCH V6 07/25] perf/x86: Hybrid PMU support for unconstrained Date: Mon, 12 Apr 2021 07:30:47 -0700 [thread overview] Message-ID: <1618237865-33448-8-git-send-email-kan.liang@linux.intel.com> (raw) In-Reply-To: <1618237865-33448-1-git-send-email-kan.liang@linux.intel.com> From: Kan Liang <kan.liang@linux.intel.com> The unconstrained value depends on the number of GP and fixed counters. Each hybrid PMU should use its own unconstrained. Suggested-by: Peter Zijlstra (Intel) <peterz@infradead.org> Signed-off-by: Kan Liang <kan.liang@linux.intel.com> --- arch/x86/events/intel/core.c | 2 +- arch/x86/events/perf_event.h | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 3ea0126e..4cfc382f 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3147,7 +3147,7 @@ x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx, } } - return &unconstrained; + return &hybrid_var(cpuc->pmu, unconstrained); } static struct event_constraint * diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index df3689b..93d6479 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -639,6 +639,7 @@ struct x86_hybrid_pmu { int max_pebs_events; int num_counters; int num_counters_fixed; + struct event_constraint unconstrained; }; static __always_inline struct x86_hybrid_pmu *hybrid_pmu(struct pmu *pmu) @@ -659,6 +660,16 @@ extern struct static_key_false perf_is_hybrid; __Fp; \ })) +#define hybrid_var(_pmu, _var) \ +(*({ \ + typeof(&_var) __Fp = &_var; \ + \ + if (is_hybrid() && (_pmu)) \ + __Fp = &hybrid_pmu(_pmu)->_var; \ + \ + __Fp; \ +})) + /* * struct x86_pmu - generic x86 pmu */ -- 2.7.4
next prev parent reply other threads:[~2021-04-12 14:38 UTC|newest] Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-04-12 14:30 [PATCH V6 00/25] Add Alder Lake support for perf (kernel) kan.liang 2021-04-12 14:30 ` [PATCH V6 01/25] x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Ricardo Neri 2021-04-12 14:30 ` [PATCH V6 02/25] x86/cpu: Add helper function to get the type of the current hybrid CPU kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Ricardo Neri 2021-04-12 14:30 ` [PATCH V6 03/25] perf/x86: Track pmu in per-CPU cpu_hw_events kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 05/25] perf/x86: Hybrid PMU support for intel_ctrl kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 06/25] perf/x86: Hybrid PMU support for counters kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` kan.liang [this message] 2021-04-20 10:46 ` [tip: perf/core] perf/x86: Hybrid PMU support for unconstrained tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 08/25] perf/x86: Hybrid PMU support for hardware cache event kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 09/25] perf/x86: Hybrid PMU support for event constraints kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 10/25] perf/x86: Hybrid PMU support for extra_regs kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 11/25] perf/x86/intel: Factor out intel_pmu_check_num_counters kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 12/25] perf/x86/intel: Factor out intel_pmu_check_event_constraints kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 13/25] perf/x86/intel: Factor out intel_pmu_check_extra_regs kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 14/25] perf/x86: Remove temporary pmu assignment in event_init kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 16/25] perf/x86: Register hybrid PMUs kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 17/25] perf/x86: Add structures for the attributes of Hybrid PMUs kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 18/25] perf/x86/intel: Add attr_update for " kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:30 ` [PATCH V6 19/25] perf/x86: Support filter_match callback kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:31 ` [PATCH V6 20/25] perf/x86/intel: Add Alder Lake Hybrid support kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:31 ` [PATCH V6 21/25] perf: Extend PERF_TYPE_HARDWARE and PERF_TYPE_HW_CACHE kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:31 ` [PATCH V6 22/25] perf/x86/intel/uncore: Add Alder Lake support kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:31 ` [PATCH V6 23/25] perf/x86/msr: Add Alder Lake CPU support kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:31 ` [PATCH V6 24/25] perf/x86/cstate: " kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Kan Liang 2021-04-12 14:31 ` [PATCH V6 25/25] perf/x86/rapl: Add support for Intel Alder Lake kan.liang 2021-04-20 10:46 ` [tip: perf/core] " tip-bot2 for Zhang Rui
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1618237865-33448-8-git-send-email-kan.liang@linux.intel.com \ --to=kan.liang@linux.intel.com \ --cc=acme@kernel.org \ --cc=adrian.hunter@intel.com \ --cc=ak@linux.intel.com \ --cc=alexander.shishkin@linux.intel.com \ --cc=bp@alien8.de \ --cc=jolsa@redhat.com \ --cc=linux-kernel@vger.kernel.org \ --cc=mingo@kernel.org \ --cc=namhyung@kernel.org \ --cc=peterz@infradead.org \ --cc=ricardo.neri-calderon@linux.intel.com \ --cc=tglx@linutronix.de \ --cc=yao.jin@linux.intel.com \ --subject='Re: [PATCH V6 07/25] perf/x86: Hybrid PMU support for unconstrained' \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: link
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).