From: "Limonciello, Mario" <mario.limonciello@amd.com>
To: Huang Rui <ray.huang@amd.com>,
"Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
Viresh Kumar <viresh.kumar@linaro.org>,
Shuah Khan <skhan@linuxfoundation.org>,
Borislav Petkov <bp@suse.de>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@kernel.org>,
Giovanni Gherdovich <ggherdovich@suse.cz>,
linux-pm@vger.kernel.org
Cc: Deepak Sharma <deepak.sharma@amd.com>,
Alex Deucher <alexander.deucher@amd.com>,
Steven Noonan <steven@valvesoftware.com>,
Nathan Fontenot <nathan.fontenot@amd.com>,
Jinzhou Su <Jinzhou.Su@amd.com>,
Xiaojian Du <Xiaojian.Du@amd.com>,
linux-kernel@vger.kernel.org, x86@kernel.org
Subject: Re: [PATCH v3 08/21] cpufreq: amd: add acpi cppc function as the backend for legacy processors
Date: Fri, 29 Oct 2021 09:20:09 -0500 [thread overview]
Message-ID: <16386852-7ccb-47de-5b29-b64481b59237@amd.com> (raw)
In-Reply-To: <20211029130241.1984459-9-ray.huang@amd.com>
On 10/29/2021 08:02, Huang Rui wrote:
> In some old Zen based processors, they are using the shared memory that
> exposed from ACPI SBIOS.
I don't think this is only "old" processors. I think there are "new"
processors that just don't happen to implement the MSR too.
>
> Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
> Signed-off-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/cpufreq/amd-pstate.c | 58 ++++++++++++++++++++++++++++++++----
> 1 file changed, 53 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> index 55ff03f85608..d399938d6d85 100644
> --- a/drivers/cpufreq/amd-pstate.c
> +++ b/drivers/cpufreq/amd-pstate.c
> @@ -73,6 +73,19 @@ static inline int pstate_enable(bool enable)
> return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable ? 1 : 0);
> }
>
> +static int cppc_enable(bool enable)
> +{
> + int cpu, ret = 0;
> +
> + for_each_online_cpu(cpu) {
I wonder if this should also be changed to present CPU instead of
offline CPU. Otherwise could this turn into a situation that the user
starts with some CPU's offlined and enables them later but this doesn't
end up applying to the CPUs that were started offlined and changed?
> + ret = cppc_set_enable(cpu, enable ? 1 : 0);
> + if (ret)
> + return ret;
> + }
> +
> + return ret;
> +}
> +
> DEFINE_STATIC_CALL(amd_pstate_enable, pstate_enable);
>
> static inline int amd_pstate_enable(bool enable)
> @@ -103,6 +116,24 @@ static int pstate_init_perf(struct amd_cpudata *cpudata)
> return 0;
> }
>
> +static int cppc_init_perf(struct amd_cpudata *cpudata)
> +{
> + struct cppc_perf_caps cppc_perf;
> +
> + int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf);
> + if (ret)
> + return ret;
> +
> + WRITE_ONCE(cpudata->highest_perf, amd_get_highest_perf());
> +
> + WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf);
> + WRITE_ONCE(cpudata->lowest_nonlinear_perf,
> + cppc_perf.lowest_nonlinear_perf);
> + WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf);
> +
> + return 0;
> +}
> +
> DEFINE_STATIC_CALL(amd_pstate_init_perf, pstate_init_perf);
>
> static inline int amd_pstate_init_perf(struct amd_cpudata *cpudata)
> @@ -120,6 +151,19 @@ static void pstate_update_perf(struct amd_cpudata *cpudata, u32 min_perf,
> READ_ONCE(cpudata->cppc_req_cached));
> }
>
> +static void cppc_update_perf(struct amd_cpudata *cpudata,
> + u32 min_perf, u32 des_perf,
> + u32 max_perf, bool fast_switch)
> +{
> + struct cppc_perf_ctrls perf_ctrls;
> +
> + perf_ctrls.max_perf = max_perf;
> + perf_ctrls.min_perf = min_perf;
> + perf_ctrls.desired_perf = des_perf;
> +
> + cppc_set_perf(cpudata->cpu, &perf_ctrls);
> +}
> +
> DEFINE_STATIC_CALL(amd_pstate_update_perf, pstate_update_perf);
>
> static inline void amd_pstate_update_perf(struct amd_cpudata *cpudata,
> @@ -346,7 +390,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy)
> /* It will be updated by governor */
> policy->cur = policy->cpuinfo.min_freq;
>
> - policy->fast_switch_possible = true;
> + if (boot_cpu_has(X86_FEATURE_AMD_CPPC))
> + policy->fast_switch_possible = true;
>
> ret = freq_qos_add_request(&policy->constraints, &cpudata->req[0],
> FREQ_QOS_MIN, policy->cpuinfo.min_freq);
> @@ -397,7 +442,6 @@ static struct cpufreq_driver amd_pstate_driver = {
> .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS,
> .verify = amd_pstate_verify,
> .target = amd_pstate_target,
> - .adjust_perf = amd_pstate_adjust_perf,
> .init = amd_pstate_cpu_init,
> .exit = amd_pstate_cpu_exit,
> .name = "amd-pstate",
> @@ -421,10 +465,14 @@ static int __init amd_pstate_init(void)
> return -EEXIST;
>
> /* capability check */
> - if (!boot_cpu_has(X86_FEATURE_AMD_CPPC)) {
> - pr_debug("%s, AMD CPPC MSR based functionality is not supported\n",
> + if (boot_cpu_has(X86_FEATURE_AMD_CPPC)) {
> + pr_debug("%s, AMD CPPC MSR based functionality is supported\n",
> __func__);
> - return -ENODEV;
> + amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf;
> + } else {
> + static_call_update(amd_pstate_enable, cppc_enable);
> + static_call_update(amd_pstate_init_perf, cppc_init_perf);
> + static_call_update(amd_pstate_update_perf, cppc_update_perf);
> }
>
> /* enable amd pstate feature */
>
next prev parent reply other threads:[~2021-10-29 14:20 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-29 13:02 [PATCH v3 00/21] cpufreq: introduce a new AMD CPU frequency control mechanism Huang Rui
2021-10-29 13:02 ` [PATCH v3 01/21] x86/cpufreatures: add AMD Collaborative Processor Performance Control feature flag Huang Rui
2021-10-29 14:39 ` Borislav Petkov
2021-11-06 10:28 ` Borislav Petkov
2021-11-09 3:08 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 02/21] x86/msr: add AMD CPPC MSR definitions Huang Rui
2021-10-29 13:02 ` [PATCH v3 03/21] ACPI: CPPC: implement support for SystemIO registers Huang Rui
2021-10-29 13:02 ` [PATCH v3 04/21] ACPI: CPPC: Check present CPUs for determining _CPC is valid Huang Rui
2021-10-29 13:02 ` [PATCH v3 05/21] ACPI: CPPC: add cppc enable register function Huang Rui
2021-10-29 14:15 ` Limonciello, Mario
2021-11-01 9:20 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 06/21] cpufreq: amd: introduce a new amd pstate driver to support future processors Huang Rui
2021-11-02 18:52 ` Limonciello, Mario
2021-11-02 19:38 ` Nathan Fontenot
2021-11-03 7:01 ` Huang Rui
2021-11-04 15:10 ` Nathan Fontenot
2021-11-05 4:20 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 07/21] cpufreq: amd: add fast switch function for amd-pstate Huang Rui
2021-10-29 14:16 ` Limonciello, Mario
2021-11-02 19:56 ` Nathan Fontenot
2021-10-29 13:02 ` [PATCH v3 08/21] cpufreq: amd: add acpi cppc function as the backend for legacy processors Huang Rui
2021-10-29 14:20 ` Limonciello, Mario [this message]
2021-11-01 9:02 ` Huang Rui
2021-11-02 18:46 ` Nathan Fontenot
2021-11-03 12:00 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 09/21] cpufreq: amd: add trace for amd-pstate module Huang Rui
2021-10-29 13:02 ` [PATCH v3 10/21] cpufreq: amd: add boost mode support for amd-pstate Huang Rui
2021-10-29 13:02 ` [PATCH v3 11/21] cpufreq: amd: add amd-pstate frequencies attributes Huang Rui
2021-11-05 18:59 ` Nathan Fontenot
2021-11-10 12:28 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 12/21] cpufreq: amd: add amd-pstate performance attributes Huang Rui
2021-11-05 18:50 ` Nathan Fontenot
2021-10-29 13:02 ` [PATCH v3 13/21] cpupower: add AMD P-state capability flag Huang Rui
2021-10-29 13:02 ` [PATCH v3 14/21] cpupower: add the function to check amd-pstate enabled Huang Rui
2021-10-29 13:02 ` [PATCH v3 15/21] cpupower: initial AMD P-state capability Huang Rui
2021-10-29 13:02 ` [PATCH v3 16/21] cpupower: add the function to get the sysfs value from specific table Huang Rui
2021-10-29 13:02 ` [PATCH v3 17/21] cpupower: add amd-pstate sysfs definition and access helper Huang Rui
2021-10-29 14:10 ` Limonciello, Mario
2021-11-01 9:14 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 18/21] cpupower: enable boost state support for amd-pstate module Huang Rui
2021-11-02 20:11 ` Nathan Fontenot
2021-11-03 7:04 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 19/21] cpupower: move print_speed function into misc helper Huang Rui
2021-10-29 13:02 ` [PATCH v3 20/21] cpupower: print amd-pstate information on cpupower Huang Rui
2021-10-29 13:02 ` [PATCH v3 21/21] Documentation: amd-pstate: add amd-pstate driver introduction Huang Rui
2021-11-04 16:40 ` [PATCH v3 00/21] cpufreq: introduce a new AMD CPU frequency control mechanism Giovanni Gherdovich
2021-11-05 16:09 ` Huang Rui
2021-11-06 8:58 ` Matt McDonald
2021-11-08 9:20 ` Huang Rui
2021-11-12 11:21 ` Du, Xiaojian
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=16386852-7ccb-47de-5b29-b64481b59237@amd.com \
--to=mario.limonciello@amd.com \
--cc=Jinzhou.Su@amd.com \
--cc=Xiaojian.Du@amd.com \
--cc=alexander.deucher@amd.com \
--cc=bp@suse.de \
--cc=deepak.sharma@amd.com \
--cc=ggherdovich@suse.cz \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=mingo@kernel.org \
--cc=nathan.fontenot@amd.com \
--cc=peterz@infradead.org \
--cc=rafael.j.wysocki@intel.com \
--cc=ray.huang@amd.com \
--cc=skhan@linuxfoundation.org \
--cc=steven@valvesoftware.com \
--cc=viresh.kumar@linaro.org \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).