From: Huang Rui <ray.huang@amd.com>
To: "Limonciello, Mario" <Mario.Limonciello@amd.com>
Cc: "Rafael J . Wysocki" <rafael.j.wysocki@intel.com>,
Viresh Kumar <viresh.kumar@linaro.org>,
Shuah Khan <skhan@linuxfoundation.org>,
Borislav Petkov <bp@suse.de>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@kernel.org>,
Giovanni Gherdovich <ggherdovich@suse.cz>,
"linux-pm@vger.kernel.org" <linux-pm@vger.kernel.org>,
"Sharma, Deepak" <Deepak.Sharma@amd.com>,
"Deucher, Alexander" <Alexander.Deucher@amd.com>,
Steven Noonan <steven@valvesoftware.com>,
"Fontenot, Nathan" <Nathan.Fontenot@amd.com>,
"Su, Jinzhou (Joe)" <Jinzhou.Su@amd.com>,
"Du, Xiaojian" <Xiaojian.Du@amd.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"x86@kernel.org" <x86@kernel.org>
Subject: Re: [PATCH v3 08/21] cpufreq: amd: add acpi cppc function as the backend for legacy processors
Date: Mon, 1 Nov 2021 17:02:43 +0800 [thread overview]
Message-ID: <YX+tM7FOQBKqHetw@hr-amd> (raw)
In-Reply-To: <16386852-7ccb-47de-5b29-b64481b59237@amd.com>
On Fri, Oct 29, 2021 at 10:20:09PM +0800, Limonciello, Mario wrote:
> On 10/29/2021 08:02, Huang Rui wrote:
> > In some old Zen based processors, they are using the shared memory that
> > exposed from ACPI SBIOS.
>
> I don't think this is only "old" processors. I think there are "new"
> processors that just don't happen to implement the MSR too.
>
Yes, I will correct the description.
> >
> > Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
> > Signed-off-by: Huang Rui <ray.huang@amd.com>
> > ---
> > drivers/cpufreq/amd-pstate.c | 58 ++++++++++++++++++++++++++++++++----
> > 1 file changed, 53 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c
> > index 55ff03f85608..d399938d6d85 100644
> > --- a/drivers/cpufreq/amd-pstate.c
> > +++ b/drivers/cpufreq/amd-pstate.c
> > @@ -73,6 +73,19 @@ static inline int pstate_enable(bool enable)
> > return wrmsrl_safe(MSR_AMD_CPPC_ENABLE, enable ? 1 : 0);
> > }
> >
> > +static int cppc_enable(bool enable)
> > +{
> > + int cpu, ret = 0;
> > +
> > + for_each_online_cpu(cpu) {
>
> I wonder if this should also be changed to present CPU instead of
> offline CPU. Otherwise could this turn into a situation that the user
> starts with some CPU's offlined and enables them later but this doesn't
> end up applying to the CPUs that were started offlined and changed?
>
Yes, make sense. It is actually similiar with previous acpi_cpc_valid fix
patch. I will update it in V4.
Thanks,
Ray
next prev parent reply other threads:[~2021-11-01 9:03 UTC|newest]
Thread overview: 50+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-29 13:02 [PATCH v3 00/21] cpufreq: introduce a new AMD CPU frequency control mechanism Huang Rui
2021-10-29 13:02 ` [PATCH v3 01/21] x86/cpufreatures: add AMD Collaborative Processor Performance Control feature flag Huang Rui
2021-10-29 14:39 ` Borislav Petkov
2021-11-06 10:28 ` Borislav Petkov
2021-11-09 3:08 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 02/21] x86/msr: add AMD CPPC MSR definitions Huang Rui
2021-10-29 13:02 ` [PATCH v3 03/21] ACPI: CPPC: implement support for SystemIO registers Huang Rui
2021-10-29 13:02 ` [PATCH v3 04/21] ACPI: CPPC: Check present CPUs for determining _CPC is valid Huang Rui
2021-10-29 13:02 ` [PATCH v3 05/21] ACPI: CPPC: add cppc enable register function Huang Rui
2021-10-29 14:15 ` Limonciello, Mario
2021-11-01 9:20 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 06/21] cpufreq: amd: introduce a new amd pstate driver to support future processors Huang Rui
2021-11-02 18:52 ` Limonciello, Mario
2021-11-02 19:38 ` Nathan Fontenot
2021-11-03 7:01 ` Huang Rui
2021-11-04 15:10 ` Nathan Fontenot
2021-11-05 4:20 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 07/21] cpufreq: amd: add fast switch function for amd-pstate Huang Rui
2021-10-29 14:16 ` Limonciello, Mario
2021-11-02 19:56 ` Nathan Fontenot
2021-10-29 13:02 ` [PATCH v3 08/21] cpufreq: amd: add acpi cppc function as the backend for legacy processors Huang Rui
2021-10-29 14:20 ` Limonciello, Mario
2021-11-01 9:02 ` Huang Rui [this message]
2021-11-02 18:46 ` Nathan Fontenot
2021-11-03 12:00 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 09/21] cpufreq: amd: add trace for amd-pstate module Huang Rui
2021-10-29 13:02 ` [PATCH v3 10/21] cpufreq: amd: add boost mode support for amd-pstate Huang Rui
2021-10-29 13:02 ` [PATCH v3 11/21] cpufreq: amd: add amd-pstate frequencies attributes Huang Rui
2021-11-05 18:59 ` Nathan Fontenot
2021-11-10 12:28 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 12/21] cpufreq: amd: add amd-pstate performance attributes Huang Rui
2021-11-05 18:50 ` Nathan Fontenot
2021-10-29 13:02 ` [PATCH v3 13/21] cpupower: add AMD P-state capability flag Huang Rui
2021-10-29 13:02 ` [PATCH v3 14/21] cpupower: add the function to check amd-pstate enabled Huang Rui
2021-10-29 13:02 ` [PATCH v3 15/21] cpupower: initial AMD P-state capability Huang Rui
2021-10-29 13:02 ` [PATCH v3 16/21] cpupower: add the function to get the sysfs value from specific table Huang Rui
2021-10-29 13:02 ` [PATCH v3 17/21] cpupower: add amd-pstate sysfs definition and access helper Huang Rui
2021-10-29 14:10 ` Limonciello, Mario
2021-11-01 9:14 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 18/21] cpupower: enable boost state support for amd-pstate module Huang Rui
2021-11-02 20:11 ` Nathan Fontenot
2021-11-03 7:04 ` Huang Rui
2021-10-29 13:02 ` [PATCH v3 19/21] cpupower: move print_speed function into misc helper Huang Rui
2021-10-29 13:02 ` [PATCH v3 20/21] cpupower: print amd-pstate information on cpupower Huang Rui
2021-10-29 13:02 ` [PATCH v3 21/21] Documentation: amd-pstate: add amd-pstate driver introduction Huang Rui
2021-11-04 16:40 ` [PATCH v3 00/21] cpufreq: introduce a new AMD CPU frequency control mechanism Giovanni Gherdovich
2021-11-05 16:09 ` Huang Rui
2021-11-06 8:58 ` Matt McDonald
2021-11-08 9:20 ` Huang Rui
2021-11-12 11:21 ` Du, Xiaojian
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