[PATCH v7 0/5] support rockchip dwc3 driver

[PATCH v7 0/5] support rockchip dwc3 driver

[William Wu]

This series add support for rockchip dwc3 driver,
and add additional optional properties for specific
platforms (e.g., rockchip rk3399 platform).

William Wu (5):
  usb: dwc3: of-simple: add compatible for rockchip rk3399
  usb: dwc3: add dis_u2_freeclk_exists_quirk
  usb: dwc3: make usb2 phy utmi interface configurable in DT
  usb: dwc3: add dis_del_phy_power_chg_quirk
  usb: dwc3: rockchip: add devicetree bindings documentation

 Documentation/devicetree/bindings/usb/dwc3.txt     |  8 +++
 .../devicetree/bindings/usb/rockchip,dwc3.txt      | 59 ++++++++++++++++++++++
 drivers/usb/dwc3/core.c                            | 35 +++++++++++++
 drivers/usb/dwc3/core.h                            | 18 +++++++
 drivers/usb/dwc3/dwc3-of-simple.c                  |  1 +
 5 files changed, 121 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt

-- 
1.9.1

[PATCH v7 1/5] usb: dwc3: of-simple: add compatible for rockchip rk3399

[William Wu]

Rockchip platform merely enable usb3 clocks and
populate its children. So we can use this generic
glue layer to support Rockchip dwc3.

Signed-off-by: William Wu <william.wu@rock-chips.com>
---
Changes in v7:
- None

Changes in v6:
- None

Changes in v5:
- change compatible from "rockchip,dwc3" to "rockchip,rk3399-dwc3" (Heiko)

Changes in v4:
- None

Changes in v3:
- None

Changes in v2:
- sort the list of_dwc3_simple_match (Doug)

 drivers/usb/dwc3/dwc3-of-simple.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index 9743353..05c9349 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -161,6 +161,7 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = {
 
 static const struct of_device_id of_dwc3_simple_match[] = {
 	{ .compatible = "qcom,dwc3" },
+	{ .compatible = "rockchip,rk3399-dwc3" },
 	{ .compatible = "xlnx,zynqmp-dwc3" },
 	{ /* Sentinel */ }
 };
-- 
1.9.1

[PATCH v7 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk

[William Wu]

Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
which specifies whether the USB2.0 PHY provides a free-running
PHY clock, which is active when the clock control input is active.

Signed-off-by: William Wu <william.wu@rock-chips.com>
---
Changes in v7:
- None

Changes in v6:
- use '-' instead of '_' in dts (Rob Herring)

Changes in v5:
- None

Changes in v4:
- rebase on top of balbi testing/next, remove pdata (balbi)

Changes in v3:
- None

Changes in v2:
- None

 Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
 drivers/usb/dwc3/core.c                        | 5 +++++
 drivers/usb/dwc3/core.h                        | 5 +++++
 3 files changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 7d7ce08..020b0e9 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -39,6 +39,9 @@ Optional properties:
 			disabling the suspend signal to the PHY.
  - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection
 			in PHY P3 power state.
+ - snps,dis-u2-freeclk-exists-quirk: when set, clear the u2_freeclk_exists
+			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
+			a free-running PHY clock.
  - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
 			utmi_l1_suspend_n, false when asserts utmi_sleep_n
  - snps,hird-threshold: HIRD threshold
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 9466431..0b7bfd2 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -500,6 +500,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_enblslpm_quirk)
 		reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 
+	if (dwc->dis_u2_freeclk_exists_quirk)
+		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 
 	return 0;
@@ -924,6 +927,8 @@ static int dwc3_probe(struct platform_device *pdev)
 				"snps,dis_enblslpm_quirk");
 	dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
 				"snps,dis_rxdet_inp3_quirk");
+	dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
+				"snps,dis-u2-freeclk-exists-quirk");
 
 	dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 				"snps,tx_de_emphasis_quirk");
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 45d6de5..f321a5c 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -199,6 +199,7 @@
 
 /* Global USB2 PHY Configuration Register */
 #define DWC3_GUSB2PHYCFG_PHYSOFTRST	(1 << 31)
+#define DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS	(1 << 30)
 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
 #define DWC3_GUSB2PHYCFG_ULPI_UTMI	(1 << 4)
 #define DWC3_GUSB2PHYCFG_ENBLSLPM	(1 << 8)
@@ -799,6 +800,9 @@ struct dwc3_scratchpad_array {
  * @dis_u2_susphy_quirk: set if we disable usb2 suspend phy
  * @dis_enblslpm_quirk: set if we clear enblslpm in GUSB2PHYCFG,
  *                      disabling the suspend signal to the PHY.
+ * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
+ *			in GUSB2PHYCFG, specify that USB2 PHY doesn't
+ *			provide a free-running PHY clock.
  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
  * @tx_de_emphasis: Tx de-emphasis value
  * 	0	- -6dB de-emphasis
@@ -942,6 +946,7 @@ struct dwc3 {
 	unsigned		dis_u2_susphy_quirk:1;
 	unsigned		dis_enblslpm_quirk:1;
 	unsigned		dis_rxdet_inp3_quirk:1;
+	unsigned		dis_u2_freeclk_exists_quirk:1;
 
 	unsigned		tx_de_emphasis_quirk:1;
 	unsigned		tx_de_emphasis:2;
-- 
1.9.1

[PATCH v7 3/5] usb: dwc3: make usb2 phy utmi interface configurable in DT

[William Wu]

Add snps,phyif-utmi-width devicetree property to configure
the UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
interface is a hardware property, and it's platform dependent.
Normally,the PHYIF can be configured during coreconsultant.
But for some specific USB cores(e.g. rk3399 SoC DWC3), the
default PHYIF configuration value is fault, so we need to
reconfigure it by software.

And refer to the DWC3 databook, the GUSB2PHYCFG.USBTRDTIM
must be set to the corresponding value according to the
UTMI+ PHY interface.

Signed-off-by: William Wu <william.wu@rock-chips.com>
---
Changes in v7:
- remove quirk and use only one property to configure utmi (Heiko, Rob Herring)

Changes in v6:
- use '-' instead of '_' in dts (Rob Herring)

Changes in v5:
- None

Changes in v4:
- rebase on top of balbi testing/next, remove pdata (balbi)

Changes in v3:
- None

Changes in v2:
- add a quirk for phyif_utmi (balbi)

 Documentation/devicetree/bindings/usb/dwc3.txt |  3 +++
 drivers/usb/dwc3/core.c                        | 25 +++++++++++++++++++++++++
 drivers/usb/dwc3/core.h                        | 10 ++++++++++
 3 files changed, 38 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 020b0e9..00cc541 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -47,6 +47,9 @@ Optional properties:
  - snps,hird-threshold: HIRD threshold
  - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for
    UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3.
+ - snps,phyif-utmi-width: the value to configure the core to support a UTMI+ PHY
+			with an 8- or 16-bit interface. Value 8 select 8-bit
+			interface, value 16 select 16-bit interface.
  - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ
 	register for post-silicon frame length adjustment when the
 	fladj_30mhz_sdbnd signal is invalid or incorrect.
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 0b7bfd2..40c54db 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -408,6 +408,8 @@ static void dwc3_cache_hwparams(struct dwc3 *dwc)
 static int dwc3_phy_setup(struct dwc3 *dwc)
 {
 	u32 reg;
+	u32 usbtrdtim;
+	u8 phyif;
 	int ret;
 
 	reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
@@ -503,6 +505,16 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_u2_freeclk_exists_quirk)
 		reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 
+	if (dwc->phyif_utmi_width > 0) {
+		reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
+		       DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
+		usbtrdtim = (dwc->phyif_utmi_width == 16) ?
+			    USBTRDTIM_UTMI_16_BIT : USBTRDTIM_UTMI_8_BIT;
+		phyif = (dwc->phyif_utmi_width == 16) ? 1 : 0;
+		reg |= DWC3_GUSB2PHYCFG_PHYIF(phyif) |
+		       DWC3_GUSB2PHYCFG_USBTRDTIM(usbtrdtim);
+	}
+
 	dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 
 	return 0;
@@ -900,6 +912,19 @@ static int dwc3_probe(struct platform_device *pdev)
 				"snps,is-utmi-l1-suspend");
 	device_property_read_u8(dev, "snps,hird-threshold",
 				&hird_threshold);
+
+	ret = device_property_read_u8(dev, "snps,phyif-utmi-width",
+				      &dwc->phyif_utmi_width);
+	if (ret < 0) {
+		dwc->phyif_utmi_width = 0;
+	} else if (dwc->phyif_utmi_width != 16 &&
+		dwc->phyif_utmi_width != 8) {
+		dev_err(dev, "unsupported utmi interface width %d\n",
+			dwc->phyif_utmi_width);
+		ret = -EINVAL;
+		goto err0;
+	}
+
 	dwc->usb3_lpm_capable = device_property_read_bool(dev,
 				"snps,usb3_lpm_capable");
 
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index f321a5c..99a72c7 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -203,6 +203,12 @@
 #define DWC3_GUSB2PHYCFG_SUSPHY		(1 << 6)
 #define DWC3_GUSB2PHYCFG_ULPI_UTMI	(1 << 4)
 #define DWC3_GUSB2PHYCFG_ENBLSLPM	(1 << 8)
+#define DWC3_GUSB2PHYCFG_PHYIF(n)	(n << 3)
+#define DWC3_GUSB2PHYCFG_PHYIF_MASK	DWC3_GUSB2PHYCFG_PHYIF(1)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM(n)	(n << 10)
+#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK	DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
+#define USBTRDTIM_UTMI_8_BIT		9
+#define USBTRDTIM_UTMI_16_BIT		5
 
 /* Global USB2 PHY Vendor Control Register */
 #define DWC3_GUSB2PHYACC_NEWREGREQ	(1 << 25)
@@ -770,6 +776,9 @@ struct dwc3_scratchpad_array {
  * @test_mode_nr: test feature selector
  * @lpm_nyet_threshold: LPM NYET response threshold
  * @hird_threshold: HIRD threshold
+ * @phyif_utmi_width: UTMI+ PHY interface width value
+ *	8	- 8 bits
+ *	16	- 16 bits
  * @hsphy_interface: "utmi" or "ulpi"
  * @connected: true when we're connected to a host, false otherwise
  * @delayed_status: true when gadget driver asks for delayed status
@@ -917,6 +926,7 @@ struct dwc3 {
 	u8			test_mode_nr;
 	u8			lpm_nyet_threshold;
 	u8			hird_threshold;
+	u8			phyif_utmi_width;
 
 	const char		*hsphy_interface;
 
-- 
1.9.1

[PATCH v7 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk

[William Wu]

Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
which specifies whether disable delay PHY power change
from P0 to P1/P2/P3 when link state changing from U0
to U1/U2/U3 respectively.

Signed-off-by: William Wu <william.wu@rock-chips.com>
---
Changes in v7:
- None

Changes in v6:
- use '-' instead of '_' in dts (Rob Herring)

Changes in v5:
- None

Changes in v4:
- rebase on top of balbi testing/next, remove pdata (balbi)

Changes in v3:
- None

Changes in v2:
- None

 Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
 drivers/usb/dwc3/core.c                        | 5 +++++
 drivers/usb/dwc3/core.h                        | 3 +++
 3 files changed, 10 insertions(+)

diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 00cc541..7832e19 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -42,6 +42,8 @@ Optional properties:
  - snps,dis-u2-freeclk-exists-quirk: when set, clear the u2_freeclk_exists
 			in GUSB2PHYCFG, specify that USB2 PHY doesn't provide
 			a free-running PHY clock.
+ - snps,dis-del-phy-power-chg-quirk: when set core will change PHY power
+			from P0 to P1/P2/P3 without delay.
  - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
 			utmi_l1_suspend_n, false when asserts utmi_sleep_n
  - snps,hird-threshold: HIRD threshold
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 40c54db..bff5ae4 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -450,6 +450,9 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
 	if (dwc->dis_u3_susphy_quirk)
 		reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 
+	if (dwc->dis_del_phy_power_chg_quirk)
+		reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
+
 	dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 
 	reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
@@ -954,6 +957,8 @@ static int dwc3_probe(struct platform_device *pdev)
 				"snps,dis_rxdet_inp3_quirk");
 	dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
 				"snps,dis-u2-freeclk-exists-quirk");
+	dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
+				"snps,dis-del-phy-power-chg-quirk");
 
 	dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
 				"snps,tx_de_emphasis_quirk");
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 99a72c7..753d977a 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -812,6 +812,8 @@ struct dwc3_scratchpad_array {
  * @dis_u2_freeclk_exists_quirk : set if we clear u2_freeclk_exists
  *			in GUSB2PHYCFG, specify that USB2 PHY doesn't
  *			provide a free-running PHY clock.
+ * @dis_del_phy_power_chg_quirk: set if we disable delay phy power
+ *			change quirk.
  * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk
  * @tx_de_emphasis: Tx de-emphasis value
  * 	0	- -6dB de-emphasis
@@ -957,6 +959,7 @@ struct dwc3 {
 	unsigned		dis_enblslpm_quirk:1;
 	unsigned		dis_rxdet_inp3_quirk:1;
 	unsigned		dis_u2_freeclk_exists_quirk:1;
+	unsigned		dis_del_phy_power_chg_quirk:1;
 
 	unsigned		tx_de_emphasis_quirk:1;
 	unsigned		tx_de_emphasis:2;
-- 
1.9.1

[PATCH v7 5/5] usb: dwc3: rockchip: add devicetree bindings documentation

[William Wu]

This patch adds the devicetree documentation required for Rockchip
USB3.0 core wrapper consisting of USB3.0 IP from Synopsys.

It supports DRD mode, and could operate in device mode (SS, HS, FS)
and host mode (SS, HS, FS, LS).

Signed-off-by: William Wu <william.wu@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v7:
- add Acked-by (Rob Herring)

Changes in v6:
- rename bus_clk, and add usbdrd3_1 node as an example (Heiko)

Changes in v5:
- rename clock-names, and remove unnecessary clocks (Heiko)

Changes in v4:
- modify commit log, and add phy documentation location (Sergei)

Changes in v3:
- add dwc3 address (balbi)

Changes in v2:
- add rockchip,dwc3.txt to Documentation/devicetree/bindings/ (balbi, Brian)

 .../devicetree/bindings/usb/rockchip,dwc3.txt      | 59 ++++++++++++++++++++++
 1 file changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/usb/rockchip,dwc3.txt

diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
new file mode 100644
index 0000000..0536a93
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.txt
@@ -0,0 +1,59 @@
+Rockchip SuperSpeed DWC3 USB SoC controller
+
+Required properties:
+- compatible:	should contain "rockchip,rk3399-dwc3" for rk3399 SoC
+- clocks:	A list of phandle + clock-specifier pairs for the
+		clocks listed in clock-names
+- clock-names:	Should contain the following:
+  "ref_clk"	Controller reference clk, have to be 24 MHz
+  "suspend_clk"	Controller suspend clk, have to be 24 MHz or 32 KHz
+  "bus_clk"	Master/Core clock, have to be >= 62.5 MHz for SS
+		operation and >= 30MHz for HS operation
+  "grf_clk"	Controller grf clk
+
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+Phy documentation is provided in the following places:
+Documentation/devicetree/bindings/phy/rockchip,dwc3-usb-phy.txt
+
+Example device nodes:
+
+	usbdrd3_0: usb@fe800000 {
+		compatible = "rockchip,rk3399-dwc3";
+		clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
+			 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk", "grf_clk";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+		usbdrd_dwc3_0: dwc3@fe800000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xfe800000 0x0 0x100000>;
+			interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "otg";
+			status = "disabled";
+		};
+	};
+
+	usbdrd3_1: usb@fe900000 {
+		compatible = "rockchip,rk3399-dwc3";
+		clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
+			 <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
+		clock-names = "ref_clk", "suspend_clk",
+			      "bus_clk", "grf_clk";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+		status = "disabled";
+		usbdrd_dwc3_1: dwc3@fe900000 {
+			compatible = "snps,dwc3";
+			reg = <0x0 0xfe900000 0x0 0x100000>;
+			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
+			dr_mode = "otg";
+			status = "disabled";
+		};
+	};
-- 
1.9.1

Re: [PATCH v7 2/5] usb: dwc3: add dis_u2_freeclk_exists_quirk

[Rob Herring]

On Thu, Jul 14, 2016 at 04:59:19PM +0800, William Wu wrote:
> Add a quirk to clear the GUSB2PHYCFG.U2_FREECLK_EXISTS bit,
> which specifies whether the USB2.0 PHY provides a free-running
> PHY clock, which is active when the clock control input is active.
> 
> Signed-off-by: William Wu <william.wu@rock-chips.com>
> ---
> Changes in v7:
> - None
> 
> Changes in v6:
> - use '-' instead of '_' in dts (Rob Herring)
> 
> Changes in v5:
> - None
> 
> Changes in v4:
> - rebase on top of balbi testing/next, remove pdata (balbi)
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - None
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
>  drivers/usb/dwc3/core.c                        | 5 +++++
>  drivers/usb/dwc3/core.h                        | 5 +++++
>  3 files changed, 13 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v7 3/5] usb: dwc3: make usb2 phy utmi interface configurable in DT

[Rob Herring]

On Thu, Jul 14, 2016 at 04:59:20PM +0800, William Wu wrote:
> Add snps,phyif-utmi-width devicetree property to configure
> the UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
> interface is a hardware property, and it's platform dependent.
> Normally,the PHYIF can be configured during coreconsultant.
           ^
space

> But for some specific USB cores(e.g. rk3399 SoC DWC3), the
> default PHYIF configuration value is fault, so we need to
> reconfigure it by software.
> 
> And refer to the DWC3 databook, the GUSB2PHYCFG.USBTRDTIM
> must be set to the corresponding value according to the
> UTMI+ PHY interface.
> 
> Signed-off-by: William Wu <william.wu@rock-chips.com>
> ---
> Changes in v7:
> - remove quirk and use only one property to configure utmi (Heiko, Rob Herring)
> 
> Changes in v6:
> - use '-' instead of '_' in dts (Rob Herring)
> 
> Changes in v5:
> - None
> 
> Changes in v4:
> - rebase on top of balbi testing/next, remove pdata (balbi)
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - add a quirk for phyif_utmi (balbi)
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt |  3 +++
>  drivers/usb/dwc3/core.c                        | 25 +++++++++++++++++++++++++
>  drivers/usb/dwc3/core.h                        | 10 ++++++++++
>  3 files changed, 38 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index 020b0e9..00cc541 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -47,6 +47,9 @@ Optional properties:
>   - snps,hird-threshold: HIRD threshold
>   - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for
>     UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3.
> + - snps,phyif-utmi-width: the value to configure the core to support a UTMI+ PHY
> +			with an 8- or 16-bit interface. Value 8 select 8-bit
> +			interface, value 16 select 16-bit interface.

Is 'phy_type = "utmi_wide"' not the same as 16-bit width?

Again, I think this should be common.

Rob

Re: [PATCH v7 4/5] usb: dwc3: add dis_del_phy_power_chg_quirk

[Rob Herring]

On Thu, Jul 14, 2016 at 04:59:21PM +0800, William Wu wrote:
> Add a quirk to clear the GUSB3PIPECTL.DELAYP1TRANS bit,
> which specifies whether disable delay PHY power change
> from P0 to P1/P2/P3 when link state changing from U0
> to U1/U2/U3 respectively.
> 
> Signed-off-by: William Wu <william.wu@rock-chips.com>
> ---
> Changes in v7:
> - None
> 
> Changes in v6:
> - use '-' instead of '_' in dts (Rob Herring)
> 
> Changes in v5:
> - None
> 
> Changes in v4:
> - rebase on top of balbi testing/next, remove pdata (balbi)
> 
> Changes in v3:
> - None
> 
> Changes in v2:
> - None
> 
>  Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
>  drivers/usb/dwc3/core.c                        | 5 +++++
>  drivers/usb/dwc3/core.h                        | 3 +++
>  3 files changed, 10 insertions(+)

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH v7 3/5] usb: dwc3: make usb2 phy utmi interface configurable in DT

[Heiko Stübner]

Am Samstag, 16. Juli 2016, 17:57:15 schrieb Rob Herring:
> On Thu, Jul 14, 2016 at 04:59:20PM +0800, William Wu wrote:
> > Add snps,phyif-utmi-width devicetree property to configure
> > the UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
> > interface is a hardware property, and it's platform dependent.
> > Normally,the PHYIF can be configured during coreconsultant.
> 
>            ^
> space
> 
> > But for some specific USB cores(e.g. rk3399 SoC DWC3), the
> > default PHYIF configuration value is fault, so we need to
> > reconfigure it by software.
> > 
> > And refer to the DWC3 databook, the GUSB2PHYCFG.USBTRDTIM
> > must be set to the corresponding value according to the
> > UTMI+ PHY interface.
> > 
> > Signed-off-by: William Wu <william.wu@rock-chips.com>
> > ---
> > Changes in v7:
> > - remove quirk and use only one property to configure utmi (Heiko, Rob
> > Herring)
> > 
> > Changes in v6:
> > - use '-' instead of '_' in dts (Rob Herring)
> > 
> > Changes in v5:
> > - None
> > 
> > Changes in v4:
> > - rebase on top of balbi testing/next, remove pdata (balbi)
> > 
> > Changes in v3:
> > - None
> > 
> > Changes in v2:
> > - add a quirk for phyif_utmi (balbi)
> > 
> >  Documentation/devicetree/bindings/usb/dwc3.txt |  3 +++
> >  drivers/usb/dwc3/core.c                        | 25
> >  +++++++++++++++++++++++++ drivers/usb/dwc3/core.h                       
> >  | 10 ++++++++++
> >  3 files changed, 38 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
> > b/Documentation/devicetree/bindings/usb/dwc3.txt index 020b0e9..00cc541
> > 100644
> > --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> > +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> > 
> > @@ -47,6 +47,9 @@ Optional properties:
> >   - snps,hird-threshold: HIRD threshold
> >   - snps,hsphy_interface: High-Speed PHY interface selection between
> >   "utmi" for>   
> >     UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value
> >     3.
> > 
> > + - snps,phyif-utmi-width: the value to configure the core to support a
> > UTMI+ PHY +			with an 8- or 16-bit interface. Value 8 select 8-bit
> > +			interface, value 16 select 16-bit interface.
> 
> Is 'phy_type = "utmi_wide"' not the same as 16-bit width?
> 
> Again, I think this should be common.

after knowing that I need to look for that "utmi_wide", I think I'd agree.

I found mention of that in usb/ci-hdrc-usb2.txt and usb/fsl-usb.txt and from
the coresponding code, I can see that they really mean the 16bit interface,
the Rockchip TRM as well as the spec [0] seems to call it UTMI+ but really
looks the same as utmi_wide.

Interestingly, there is already generic code in drivers/usb/phy/of.c so that 
property should probably move to devicetree/bindings/usb/generic.txt
as well.


Heiko

[0] http://cache.nxp.com/files/corporate/doc/support_info/UTMI-PLUS-SPECIFICATION.pdf

Re: [PATCH v7 3/5] usb: dwc3: make usb2 phy utmi interface configurable in DT

[William.wu]

Dear Rob,


On 2016/7/17 6:57, Rob Herring wrote:
> On Thu, Jul 14, 2016 at 04:59:20PM +0800, William Wu wrote:
>> Add snps,phyif-utmi-width devicetree property to configure
>> the UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
>> interface is a hardware property, and it's platform dependent.
>> Normally,the PHYIF can be configured during coreconsultant.
>             ^
> space
I'll fix it next patch, thanks:-)
>
>> But for some specific USB cores(e.g. rk3399 SoC DWC3), the
>> default PHYIF configuration value is fault, so we need to
>> reconfigure it by software.
>>
>> And refer to the DWC3 databook, the GUSB2PHYCFG.USBTRDTIM
>> must be set to the corresponding value according to the
>> UTMI+ PHY interface.
>>
>> Signed-off-by: William Wu <william.wu@rock-chips.com>
>> ---
>> Changes in v7:
>> - remove quirk and use only one property to configure utmi (Heiko, Rob Herring)
>>
>> Changes in v6:
>> - use '-' instead of '_' in dts (Rob Herring)
>>
>> Changes in v5:
>> - None
>>
>> Changes in v4:
>> - rebase on top of balbi testing/next, remove pdata (balbi)
>>
>> Changes in v3:
>> - None
>>
>> Changes in v2:
>> - add a quirk for phyif_utmi (balbi)
>>
>>   Documentation/devicetree/bindings/usb/dwc3.txt |  3 +++
>>   drivers/usb/dwc3/core.c                        | 25 +++++++++++++++++++++++++
>>   drivers/usb/dwc3/core.h                        | 10 ++++++++++
>>   3 files changed, 38 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
>> index 020b0e9..00cc541 100644
>> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>> @@ -47,6 +47,9 @@ Optional properties:
>>    - snps,hird-threshold: HIRD threshold
>>    - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for
>>      UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3.
>> + - snps,phyif-utmi-width: the value to configure the core to support a UTMI+ PHY
>> +			with an 8- or 16-bit interface. Value 8 select 8-bit
>> +			interface, value 16 select 16-bit interface.
> Is 'phy_type = "utmi_wide"' not the same as 16-bit width?
>
> Again, I think this should be common.
Yes， I agree with you. ‘phy_type = "utmi_wide" really means 16-bit UTMI 
width.
Thanks very much for your rigorous check.

And according to Heiko's helpful suggestion，I double check the kernel 
code and
look over UTMI/UTMI+ spec，I confirm that there is already generic code in
drivers/usb/phy/of.c about utmi interface, 'phy_type = "utmi"' means 
8-bit interface,
and 'phy_type = "utmi_wide"' means 16-bit interface.

So I think I don't need to add a new dts property 
'snps,phyif-utmi-width' here，
but just use the‘phy_type’ property to confirm UTMI+ interface for dwc3.

>
> Rob
>
>
>

Re: [PATCH v7 3/5] usb: dwc3: make usb2 phy utmi interface configurable in DT

[William.wu]

Dear Heiko,


On 2016/7/17 18:28, Heiko Stübner wrote:
> Am Samstag, 16. Juli 2016, 17:57:15 schrieb Rob Herring:
>> On Thu, Jul 14, 2016 at 04:59:20PM +0800, William Wu wrote:
>>> Add snps,phyif-utmi-width devicetree property to configure
>>> the UTMI+ PHY with an 8- or 16-bit interface. UTMI+ PHY
>>> interface is a hardware property, and it's platform dependent.
>>> Normally,the PHYIF can be configured during coreconsultant.
>>             ^
>> space
>>
>>> But for some specific USB cores(e.g. rk3399 SoC DWC3), the
>>> default PHYIF configuration value is fault, so we need to
>>> reconfigure it by software.
>>>
>>> And refer to the DWC3 databook, the GUSB2PHYCFG.USBTRDTIM
>>> must be set to the corresponding value according to the
>>> UTMI+ PHY interface.
>>>
>>> Signed-off-by: William Wu <william.wu@rock-chips.com>
>>> ---
>>> Changes in v7:
>>> - remove quirk and use only one property to configure utmi (Heiko, Rob
>>> Herring)
>>>
>>> Changes in v6:
>>> - use '-' instead of '_' in dts (Rob Herring)
>>>
>>> Changes in v5:
>>> - None
>>>
>>> Changes in v4:
>>> - rebase on top of balbi testing/next, remove pdata (balbi)
>>>
>>> Changes in v3:
>>> - None
>>>
>>> Changes in v2:
>>> - add a quirk for phyif_utmi (balbi)
>>>
>>>   Documentation/devicetree/bindings/usb/dwc3.txt |  3 +++
>>>   drivers/usb/dwc3/core.c                        | 25
>>>   +++++++++++++++++++++++++ drivers/usb/dwc3/core.h
>>>   | 10 ++++++++++
>>>   3 files changed, 38 insertions(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
>>> b/Documentation/devicetree/bindings/usb/dwc3.txt index 020b0e9..00cc541
>>> 100644
>>> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
>>> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
>>>
>>> @@ -47,6 +47,9 @@ Optional properties:
>>>    - snps,hird-threshold: HIRD threshold
>>>    - snps,hsphy_interface: High-Speed PHY interface selection between
>>>    "utmi" for>
>>>      UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value
>>>      3.
>>>
>>> + - snps,phyif-utmi-width: the value to configure the core to support a
>>> UTMI+ PHY +			with an 8- or 16-bit interface. Value 8 select 8-bit
>>> +			interface, value 16 select 16-bit interface.
>> Is 'phy_type = "utmi_wide"' not the same as 16-bit width?
>>
>> Again, I think this should be common.
> after knowing that I need to look for that "utmi_wide", I think I'd agree.
>
> I found mention of that in usb/ci-hdrc-usb2.txt and usb/fsl-usb.txt and from
> the coresponding code, I can see that they really mean the 16bit interface,
> the Rockchip TRM as well as the spec [0] seems to call it UTMI+ but really
> looks the same as utmi_wide.
>
> Interestingly, there is already generic code in drivers/usb/phy/of.c so that
> property should probably move to devicetree/bindings/usb/generic.txt
> as well.
>
>
> Heiko
>
> [0] http://cache.nxp.com/files/corporate/doc/support_info/UTMI-PLUS-SPECIFICATION.pdf

Thank you very much for your kindly help and helpful suggestion.:-D
I quite agree with you about use ‘phy_type’ to config UTMI+ interface 
for DWC3 controller, and add the ‘phy_type’ property to 
devicetree/bindings/usb/generic.txt.

So I shouldn't add a new dts property ‘snps,phyif-utmi-width’ here， and 
just use ‘phy_type’is enough.

BTW, I think rk3399 UTMI+ isn't the same as ‘utmi_wide’. Because UTMI+ 
support both 8-bit data interface and 16-bit data interface, but refer 
to code in drivers/usb/phy/of.c and related driver，‘phy_type = 
"utmi_wide"’means 16-bits, 'phy_type = utmi' means 8-bits.

Dear Felipe， how about your opinion about add ‘phy_type’ to config UTMI+ 
interface?

Best Regards
        William wu
>
>
>
>