* [PATCH v9 0/2] Add the driver for Intel Keem Bay SoC timer block
@ 2022-03-07 11:31 shruthi.sanil
2022-03-07 11:31 ` [PATCH v9 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil
2022-03-07 11:31 ` [PATCH v9 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil
0 siblings, 2 replies; 6+ messages in thread
From: shruthi.sanil @ 2022-03-07 11:31 UTC (permalink / raw)
To: daniel.lezcano, tglx, robh+dt, linux-kernel, devicetree
Cc: andriy.shevchenko, mgross, srikanth.thokala,
lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar,
shruthi.sanil
From: Shruthi Sanil <shruthi.sanil@intel.com>
The timer block supports 1 64-bit free running counter
and 8 32-bit general purpose timers.
Patch 1 holds the device tree binding documentation.
Patch 2 holds the device driver.
This driver is tested on the Keem Bay evaluation module board.
Changes since v8:
- The clockevent stucture has been declared as a global static variable,
rather than allocating memory using kzalloc during probing.
- Updated the print statement indicating the configuration missing as the FW Bug.
- Updated the comments in the function keembay_timer_isr().
- Updated the dt-binding to remove 'oneOf' as there is only 1 entry.
- Updated the dt-binding description clearly indicating that
the descrption is about the undelying HW.
Changes since v7:
- Added back the compatible string "intel,keembay-gpt-creg"
as an enum to the mfd device node in the device tree bindings.
- As the timer is used as a broadcast timer during CPU idle,
only one timer is needed. Hence updated the driver accordingly
incorporating the review comments.
Changes since v6:
- Removed the unused compatible string from the mfd device node
to fix the error thrown by the make dt-binding command.
Changes since v5:
- Created a MFD device for the common configuration register
in the device tree bindings.
- Updated the timer driver with the MFD framework to access the
common configuration register.
Changes since v4:
- Updated the description in the device tree bindings.
- Updated the unit address of all the timers and counter
in the device tree binding.
Changes since v3:
- Update in KConfig file to support COMPILE_TEST for Keem Bay timer.
- Update in device tree bindings to remove status field.
- Update in device tree bindings to remove 64-bit address space for
the child nodes by using non-empty ranges.
Changes since v2:
- Add multi timer support.
- Update in the device tree binding to support multi timers.
- Code optimization.
Changes since v1:
- Add support for KEEMBAY_TIMER to get selected through Kconfig.platforms.
- Add CLOCK_EVT_FEAT_DYNIRQ as part of clockevent feature.
- Avoid overlapping reg regions across 2 device nodes.
- Simplify 2 device nodes as 1 because both are from same IP block.
- Adapt the driver code according to the new simplified devicetree.
Shruthi Sanil (2):
dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer
clocksource: Add Intel Keem Bay timer support
.../bindings/timer/intel,keembay-timer.yaml | 125 ++++++++++
MAINTAINERS | 6 +
drivers/clocksource/Kconfig | 11 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-keembay.c | 227 ++++++++++++++++++
5 files changed, 370 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
create mode 100644 drivers/clocksource/timer-keembay.c
base-commit: ffb217a13a2eaf6d5bd974fc83036a53ca69f1e2
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v9 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer
2022-03-07 11:31 [PATCH v9 0/2] Add the driver for Intel Keem Bay SoC timer block shruthi.sanil
@ 2022-03-07 11:31 ` shruthi.sanil
2022-03-07 11:31 ` [PATCH v9 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil
1 sibling, 0 replies; 6+ messages in thread
From: shruthi.sanil @ 2022-03-07 11:31 UTC (permalink / raw)
To: daniel.lezcano, tglx, robh+dt, linux-kernel, devicetree
Cc: andriy.shevchenko, mgross, srikanth.thokala,
lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar,
shruthi.sanil
From: Shruthi Sanil <shruthi.sanil@intel.com>
Add Device Tree bindings for the Timer IP, which can be used as
clocksource and clockevent device in the Intel Keem Bay SoC.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com>
---
.../bindings/timer/intel,keembay-timer.yaml | 125 ++++++++++++++++++
1 file changed, 125 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
new file mode 100644
index 000000000000..333f137e39e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Intel Keem Bay SoC Timers
+
+maintainers:
+ - Shruthi Sanil <shruthi.sanil@intel.com>
+
+description: |
+ The Intel Keem Bay timer IP supports 1 free running counter and 8 timers.
+ Each timer is capable of generating inividual interrupt.
+ Both the features are enabled through the timer general config register.
+
+ The parent node represents the common general configuration details and
+ the child nodes represents the counter and timers.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - intel,keembay-gpt-creg
+ - const: simple-mfd
+
+ reg:
+ description: General configuration register address and length.
+ maxItems: 1
+
+ ranges: true
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+
+patternProperties:
+ "^counter@[0-9a-f]+$":
+ description: Properties for Intel Keem Bay counter.
+ type: object
+ properties:
+ compatible:
+ items:
+ - enum:
+ - intel,keembay-counter
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - clocks
+
+ "^timer@[0-9a-f]+$":
+ description: Properties for Intel Keem Bay timer
+ type: object
+ properties:
+ compatible:
+ items:
+ - enum:
+ - intel,keembay-timer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #define KEEM_BAY_A53_TIM
+
+ soc {
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ gpt@20331000 {
+ compatible = "intel,keembay-gpt-creg", "simple-mfd";
+ reg = <0x0 0x20331000 0x0 0xc>;
+ ranges = <0x0 0x0 0x20330000 0xF0>;
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+
+ counter@e8 {
+ compatible = "intel,keembay-counter";
+ reg = <0xe8 0x8>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+
+ timer@30 {
+ compatible = "intel,keembay-timer";
+ reg = <0x30 0xc>;
+ interrupts = <GIC_SPI 0x5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&scmi_clk KEEM_BAY_A53_TIM>;
+ };
+ };
+ };
+
+...
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v9 2/2] clocksource: Add Intel Keem Bay timer support
2022-03-07 11:31 [PATCH v9 0/2] Add the driver for Intel Keem Bay SoC timer block shruthi.sanil
2022-03-07 11:31 ` [PATCH v9 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil
@ 2022-03-07 11:31 ` shruthi.sanil
2022-03-07 13:45 ` Andy Shevchenko
2022-03-07 17:21 ` Daniel Lezcano
1 sibling, 2 replies; 6+ messages in thread
From: shruthi.sanil @ 2022-03-07 11:31 UTC (permalink / raw)
To: daniel.lezcano, tglx, robh+dt, linux-kernel, devicetree
Cc: andriy.shevchenko, mgross, srikanth.thokala,
lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar,
shruthi.sanil
From: Shruthi Sanil <shruthi.sanil@intel.com>
The Intel Keem Bay timer driver supports clocksource and clockevent
features for the timer IP used in Intel Keem Bay SoC.
The timer block supports 1 free running counter and 8 timers.
The free running counter can be used as a clocksource and
the timers can be used as clockevent. Each timer is capable of
generating individual interrupt.
Both the features are enabled through the timer general config register.
Reviewed-by: Andy Shevchenko <andriy.shevchenko@intel.com>
Signed-off-by: Shruthi Sanil <shruthi.sanil@intel.com>
---
MAINTAINERS | 6 +
drivers/clocksource/Kconfig | 11 ++
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer-keembay.c | 227 ++++++++++++++++++++++++++++
4 files changed, 245 insertions(+)
create mode 100644 drivers/clocksource/timer-keembay.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 05fd080b82f3..90af9439d529 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9791,6 +9791,12 @@ F: drivers/crypto/keembay/keembay-ocs-hcu-core.c
F: drivers/crypto/keembay/ocs-hcu.c
F: drivers/crypto/keembay/ocs-hcu.h
+INTEL KEEM BAY TIMER DRIVER
+M: Shruthi Sanil <shruthi.sanil@intel.com>
+S: Maintained
+F: Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml
+F: drivers/clocksource/timer-keembay.c
+
INTEL THUNDER BAY EMMC PHY DRIVER
M: Nandhini Srikandan <nandhini.srikandan@intel.com>
M: Rashmi A <rashmi.a@intel.com>
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index cfb8ea0df3b1..65b6cf916e5a 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -721,4 +721,15 @@ config MICROCHIP_PIT64B
modes and high resolution. It is used as a clocksource
and a clockevent.
+config KEEMBAY_TIMER
+ bool "Intel Keem Bay timer"
+ depends on ARCH_KEEMBAY || COMPILE_TEST
+ select TIMER_OF
+ help
+ This option enables the support for the Intel Keem Bay
+ general purpose timer and free running counter driver.
+ Each timer can generate an individual interrupt and
+ supports oneshot and periodic modes.
+ The 64-bit counter can be used as a clock source.
+
endmenu
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index fa5f624eadb6..dff6458ef9e5 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -89,3 +89,4 @@ obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o
obj-$(CONFIG_HYPERV_TIMER) += hyperv_timer.o
obj-$(CONFIG_MICROCHIP_PIT64B) += timer-microchip-pit64b.o
obj-$(CONFIG_MSC313E_TIMER) += timer-msc313e.o
+obj-$(CONFIG_KEEMBAY_TIMER) += timer-keembay.o
diff --git a/drivers/clocksource/timer-keembay.c b/drivers/clocksource/timer-keembay.c
new file mode 100644
index 000000000000..385863c064cd
--- /dev/null
+++ b/drivers/clocksource/timer-keembay.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Intel Keem Bay Timer driver
+ *
+ * Copyright (C) 2020 Intel Corporation
+ */
+
+#include <linux/bitops.h>
+#include <linux/interrupt.h>
+#include <linux/io-64-nonatomic-lo-hi.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/sizes.h>
+#include <linux/slab.h>
+#include <linux/regmap.h>
+
+#include "timer-of.h"
+
+/* Timer register offset */
+#define TIM_CNT_VAL_OFFSET 0x0
+#define TIM_RELOAD_VAL_OFFSET 0x4
+#define TIM_CONFIG_OFFSET 0x8
+
+/* Bit fields of timer general config register */
+#define TIM_CONFIG_PRESCALER_ENABLE BIT(2)
+#define TIM_CONFIG_COUNTER_ENABLE BIT(0)
+
+/* Bit fields of timer config register */
+#define TIM_CONFIG_INTERRUPT_PENDING BIT(4)
+#define TIM_CONFIG_INTERRUPT_ENABLE BIT(2)
+#define TIM_CONFIG_RESTART BIT(1)
+#define TIM_CONFIG_ENABLE BIT(0)
+
+#define TIM_GEN_MASK GENMASK(31, 12)
+#define TIM_RATING 200
+#define TIM_CLKSRC_MASK_BITS 64
+
+#define TIMER_NAME_SIZE 25
+
+static inline void keembay_timer_enable(void __iomem *base, u32 flags)
+{
+ writel(TIM_CONFIG_ENABLE | flags, base + TIM_CONFIG_OFFSET);
+}
+
+static inline void keembay_timer_disable(void __iomem *base)
+{
+ writel(0x0, base + TIM_CONFIG_OFFSET);
+}
+
+static inline void keembay_timer_update_counter(void __iomem *base, u32 val)
+{
+ writel(val, base + TIM_CNT_VAL_OFFSET);
+ writel(val, base + TIM_RELOAD_VAL_OFFSET);
+}
+
+static inline void keembay_timer_clear_pending_int(void __iomem *base)
+{
+ u32 val;
+
+ val = readl(base + TIM_CONFIG_OFFSET);
+ val &= ~TIM_CONFIG_INTERRUPT_PENDING;
+ writel(val, base + TIM_CONFIG_OFFSET);
+}
+
+static int keembay_timer_set_next_event(unsigned long evt, struct clock_event_device *ce)
+{
+ u32 flags = TIM_CONFIG_INTERRUPT_ENABLE;
+ struct timer_of *to = to_timer_of(ce);
+ void __iomem *tim_base = timer_of_base(to);
+
+ keembay_timer_disable(tim_base);
+ keembay_timer_update_counter(tim_base, evt);
+ keembay_timer_enable(tim_base, flags);
+
+ return 0;
+}
+
+static int keembay_timer_periodic(struct clock_event_device *ce)
+{
+ u32 flags = TIM_CONFIG_INTERRUPT_ENABLE | TIM_CONFIG_RESTART;
+ struct timer_of *to = to_timer_of(ce);
+ void __iomem *tim_base = timer_of_base(to);
+
+ keembay_timer_disable(tim_base);
+ keembay_timer_update_counter(tim_base, timer_of_period(to));
+ keembay_timer_enable(tim_base, flags);
+
+ return 0;
+}
+
+static int keembay_timer_shutdown(struct clock_event_device *ce)
+{
+ struct timer_of *to = to_timer_of(ce);
+
+ keembay_timer_disable(timer_of_base(to));
+
+ return 0;
+}
+
+static irqreturn_t keembay_timer_isr(int irq, void *dev_id)
+{
+ struct clock_event_device *evt = dev_id;
+ struct timer_of *to = to_timer_of(evt);
+ void __iomem *tim_base = timer_of_base(to);
+ u32 val;
+
+ val = readl(tim_base + TIM_CONFIG_OFFSET);
+
+ if (val & TIM_CONFIG_RESTART) {
+ /* Periodic Timer */
+ keembay_timer_clear_pending_int(tim_base);
+ } else {
+ /* One-Shot Timer */
+ keembay_timer_disable(tim_base);
+ }
+
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static struct timer_of keembay_ce_to = {
+ .flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
+ .clkevt = {
+ .name = "keembay_sys_clkevt",
+ .cpumask = cpu_possible_mask,
+ .features = CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_DYNIRQ,
+ .rating = TIM_RATING,
+ .set_next_event = keembay_timer_set_next_event,
+ .set_state_periodic = keembay_timer_periodic,
+ .set_state_shutdown = keembay_timer_shutdown,
+ },
+ .of_irq = {
+ .handler = keembay_timer_isr,
+ .flags = IRQF_TIMER,
+ },
+};
+
+static int __init keembay_clockevent_init(struct device_node *np)
+{
+ struct regmap *regmap;
+ int ret;
+ u32 val;
+
+ regmap = device_node_to_regmap(np->parent);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ ret = regmap_read(regmap, TIM_CONFIG_OFFSET, &val);
+ if (ret)
+ return ret;
+
+ /* Prescaler bit must be enabled for the timer to function */
+ if (!(val & TIM_CONFIG_PRESCALER_ENABLE)) {
+ pr_err("%pOF: FW_BUG: Prescaler is not enabled\n", np);
+ ret = -ENODEV;
+ }
+
+
+ ret = timer_of_init(np, &keembay_ce_to);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(regmap, TIM_RELOAD_VAL_OFFSET, &val);
+ if (ret)
+ return ret;
+
+ keembay_ce_to.of_clk.rate = keembay_ce_to.of_clk.rate / (val + 1);
+
+ clockevents_config_and_register(&keembay_ce_to.clkevt,
+ timer_of_rate(&keembay_ce_to),
+ 1,
+ U32_MAX);
+
+ return 0;
+}
+
+static struct timer_of keembay_cs_to = {
+ .flags = TIMER_OF_BASE | TIMER_OF_CLOCK,
+};
+
+static u64 notrace keembay_clocksource_read(struct clocksource *cs)
+{
+ return lo_hi_readq(timer_of_base(&keembay_cs_to));
+}
+
+static struct clocksource keembay_counter = {
+ .name = "keembay_sys_counter",
+ .rating = TIM_RATING,
+ .read = keembay_clocksource_read,
+ .mask = CLOCKSOURCE_MASK(TIM_CLKSRC_MASK_BITS),
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS |
+ CLOCK_SOURCE_SUSPEND_NONSTOP,
+};
+
+static int __init keembay_clocksource_init(struct device_node *np)
+{
+ struct regmap *regmap;
+ u32 val;
+ int ret;
+
+ regmap = device_node_to_regmap(np->parent);
+ if (IS_ERR(regmap))
+ return PTR_ERR(regmap);
+
+ ret = regmap_read(regmap, TIM_CONFIG_OFFSET, &val);
+ if (ret)
+ return ret;
+
+ /* Free Running Counter bit must be enabled for counter to function */
+ if (!(val & TIM_CONFIG_COUNTER_ENABLE)) {
+ pr_err("%pOF: FW_BUG: free running counter is not enabled\n", np);
+ return -ENODEV;
+ }
+
+ ret = timer_of_init(np, &keembay_cs_to);
+ if (ret)
+ return ret;
+
+ return clocksource_register_hz(&keembay_counter, timer_of_rate(&keembay_cs_to));
+}
+
+TIMER_OF_DECLARE(keembay_clockevent, "intel,keembay-timer", keembay_clockevent_init);
+TIMER_OF_DECLARE(keembay_clocksource, "intel,keembay-counter", keembay_clocksource_init);
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v9 2/2] clocksource: Add Intel Keem Bay timer support
2022-03-07 11:31 ` [PATCH v9 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil
@ 2022-03-07 13:45 ` Andy Shevchenko
2022-03-07 16:33 ` Sanil, Shruthi
2022-03-07 17:21 ` Daniel Lezcano
1 sibling, 1 reply; 6+ messages in thread
From: Andy Shevchenko @ 2022-03-07 13:45 UTC (permalink / raw)
To: shruthi.sanil
Cc: daniel.lezcano, tglx, robh+dt, linux-kernel, devicetree, mgross,
srikanth.thokala, lakshmi.bai.raja.subramanian,
mallikarjunappa.sangannavar
On Mon, Mar 07, 2022 at 05:01:47PM +0530, shruthi.sanil@intel.com wrote:
> From: Shruthi Sanil <shruthi.sanil@intel.com>
>
> The Intel Keem Bay timer driver supports clocksource and clockevent
> features for the timer IP used in Intel Keem Bay SoC.
> The timer block supports 1 free running counter and 8 timers.
> The free running counter can be used as a clocksource and
> the timers can be used as clockevent. Each timer is capable of
> generating individual interrupt.
> Both the features are enabled through the timer general config register.
...
> + pr_err("%pOF: FW_BUG: Prescaler is not enabled\n", np);
FW_BUG is a macro. The above is an incorrect use of it.
...
> + pr_err("%pOF: FW_BUG: free running counter is not enabled\n", np);
Ditto.
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH v9 2/2] clocksource: Add Intel Keem Bay timer support
2022-03-07 13:45 ` Andy Shevchenko
@ 2022-03-07 16:33 ` Sanil, Shruthi
0 siblings, 0 replies; 6+ messages in thread
From: Sanil, Shruthi @ 2022-03-07 16:33 UTC (permalink / raw)
To: Andy Shevchenko
Cc: daniel.lezcano, tglx, robh+dt, linux-kernel, devicetree, mgross,
Thokala, Srikanth, Raja Subramanian, Lakshmi Bai, Sangannavar,
Mallikarjunappa
> -----Original Message-----
> From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Sent: Monday, March 7, 2022 7:15 PM
> To: Sanil, Shruthi <shruthi.sanil@intel.com>
> Cc: daniel.lezcano@linaro.org; tglx@linutronix.de; robh+dt@kernel.org;
> linux-kernel@vger.kernel.org; devicetree@vger.kernel.org;
> mgross@linux.intel.com; Thokala, Srikanth <srikanth.thokala@intel.com>;
> Raja Subramanian, Lakshmi Bai <lakshmi.bai.raja.subramanian@intel.com>;
> Sangannavar, Mallikarjunappa <mallikarjunappa.sangannavar@intel.com>
> Subject: Re: [PATCH v9 2/2] clocksource: Add Intel Keem Bay timer support
>
> On Mon, Mar 07, 2022 at 05:01:47PM +0530, shruthi.sanil@intel.com wrote:
> > From: Shruthi Sanil <shruthi.sanil@intel.com>
> >
> > The Intel Keem Bay timer driver supports clocksource and clockevent
> > features for the timer IP used in Intel Keem Bay SoC.
> > The timer block supports 1 free running counter and 8 timers.
> > The free running counter can be used as a clocksource and the timers
> > can be used as clockevent. Each timer is capable of generating
> > individual interrupt.
> > Both the features are enabled through the timer general config register.
>
> ...
>
> > + pr_err("%pOF: FW_BUG: Prescaler is not enabled\n", np);
>
> FW_BUG is a macro. The above is an incorrect use of it.
Oh! I'll correct it and send the updated patch.
>
> ...
>
> > + pr_err("%pOF: FW_BUG: free running counter is not
> enabled\n", np);
>
> Ditto.
>
> --
> With Best Regards,
> Andy Shevchenko
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v9 2/2] clocksource: Add Intel Keem Bay timer support
2022-03-07 11:31 ` [PATCH v9 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil
2022-03-07 13:45 ` Andy Shevchenko
@ 2022-03-07 17:21 ` Daniel Lezcano
1 sibling, 0 replies; 6+ messages in thread
From: Daniel Lezcano @ 2022-03-07 17:21 UTC (permalink / raw)
To: shruthi.sanil, tglx, robh+dt, linux-kernel, devicetree
Cc: andriy.shevchenko, mgross, srikanth.thokala,
lakshmi.bai.raja.subramanian, mallikarjunappa.sangannavar
On 07/03/2022 12:31, shruthi.sanil@intel.com wrote:
> From: Shruthi Sanil <shruthi.sanil@intel.com>
[ ... ]
> + /* Prescaler bit must be enabled for the timer to function */
> + if (!(val & TIM_CONFIG_PRESCALER_ENABLE)) {
> + pr_err("%pOF: FW_BUG: Prescaler is not enabled\n", np);
> + ret = -ENODEV;
return -ENODEV;
> + }
[ ... ]
FW_BUG macro comment was already spotted
--
<http://www.linaro.org/> Linaro.org │ Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-03-07 17:21 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-07 11:31 [PATCH v9 0/2] Add the driver for Intel Keem Bay SoC timer block shruthi.sanil
2022-03-07 11:31 ` [PATCH v9 1/2] dt-bindings: timer: Add bindings for Intel Keem Bay SoC Timer shruthi.sanil
2022-03-07 11:31 ` [PATCH v9 2/2] clocksource: Add Intel Keem Bay timer support shruthi.sanil
2022-03-07 13:45 ` Andy Shevchenko
2022-03-07 16:33 ` Sanil, Shruthi
2022-03-07 17:21 ` Daniel Lezcano
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).