[PATCH 1/2] ARM: dts: exynos: Add CLK_ACLK432_SCALER clock to gsc_pd for Exynos5800

[PATCH 1/2] ARM: dts: exynos: Add CLK_ACLK432_SCALER clock to gsc_pd for Exynos5800

[Javier Martinez Canillas]

On Exynos5800 SoC the SCALER block uses 2 input clocks: CLK_ACLK_300_GSCL
and CLK_ACLK432_SCALER, so both needs to be ungated in order to access it.

The SoC manual say the CLK_ACLK432_SCALER is needed to access the internal
buses, so add this clock as another asynchronous bridges (ASB) clock.

The Exynos5420 only has the CLK_ACLK_300_GSCL clock defined. So just using
this definition from exynos5420.dtsi in Exynos5800 leads to the following:

[  227.008559] Unhandled fault: imprecise external abort (0x1c06) at 0x00048e14
[  227.015116] pgd = ed5dc000
[  227.017213] [00048e14] *pgd=b17c6835
[  227.020889] Internal error: : 1c06 [#1] PREEMPT SMP ARM
...
[  227.241585] [<bf2429bc>] (gsc_wait_reset [exynos_gsc]) from [<bf24009c>] (gsc_runtime_resume+0x9c/0xec [exynos_gsc])
[  227.252331] [<bf24009c>] (gsc_runtime_resume [exynos_gsc]) from [<c042e488>] (genpd_runtime_resume+0x120/0x1d4)
[  227.262294] [<c042e488>] (genpd_runtime_resume) from [<c04241c0>] (__rpm_callback+0xc8/0x218)

domain                          status          slaves
    /device                                             runtime status
----------------------------------------------------------------------
power-domain@100440C0           on
    /devices/platform/soc/14450000.mixer                active
    /devices/platform/soc/14530000.hdmi                 active
power-domain@10044120           on
power-domain@10044060           off-0
power-domain@10044020           on
power-domain@10044000           on
    /devices/platform/soc/13e00000.video-scaler         suspended
    /devices/platform/soc/13e10000.video-scaler         resuming

Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
---

 arch/arm/boot/dts/exynos5800.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi
index 8213016803e5..4847abbf7a92 100644
--- a/arch/arm/boot/dts/exynos5800.dtsi
+++ b/arch/arm/boot/dts/exynos5800.dtsi
@@ -134,3 +134,11 @@
 &mfc {
 	compatible = "samsung,mfc-v8";
 };
+
+&gsc_pd {
+	clocks = <&clock CLK_FIN_PLL>,
+		<&clock CLK_MOUT_USER_ACLK300_GSCL>,
+		<&clock CLK_GSCL0>, <&clock CLK_GSCL1>,
+		<&clock CLK_ACLK432_SCALER>;
+	clock-names = "oscclk", "clk0", "asb0", "asb1", "asb2";
+};
-- 
2.7.4

[PATCH 2/2] ARM: dts: exynos: Use correct mfc_pd async-bridge clock for Exynos5420

[Javier Martinez Canillas]

Commit 94aed538e032 ("ARM: dts: exynos: Add async-bridge clock to MFC
power domain for Exynos5420") fixed an imprecise external abort error
when the MFC registers were tried to be accessed and the needed clock
for the asynchronous bridges were gated.

But according to the Exynos5420 manual the "Gating AXI clock for MFC"
is not CLK_ACLK333 but CLK_MFC.

The end effect is the same because CLK_ACLK333 is a parent of CLK_MFC
but the correct clock should be used instead.

Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>

---

 arch/arm/boot/dts/exynos5420.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 906a1a42a7ea..ffb148ea91d6 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -294,7 +294,7 @@
 			reg = <0x10044060 0x20>;
 			clocks = <&clock CLK_FIN_PLL>,
 				 <&clock CLK_MOUT_USER_ACLK333>,
-				 <&clock CLK_ACLK333>;
+				 <&clock CLK_MFC>;
 			clock-names = "oscclk", "clk0","asb0";
 			#power-domain-cells = <0>;
 		};
-- 
2.7.4

Re: [PATCH 1/2] ARM: dts: exynos: Add CLK_ACLK432_SCALER clock to gsc_pd for Exynos5800

[Javier Martinez Canillas]

Hello,

On 01/19/2017 07:29 PM, Javier Martinez Canillas wrote:
> On Exynos5800 SoC the SCALER block uses 2 input clocks: CLK_ACLK_300_GSCL
> and CLK_ACLK432_SCALER, so both needs to be ungated in order to access it.
> 
> The SoC manual say the CLK_ACLK432_SCALER is needed to access the internal
> buses, so add this clock as another asynchronous bridges (ASB) clock.
> 
> The Exynos5420 only has the CLK_ACLK_300_GSCL clock defined. So just using
> this definition from exynos5420.dtsi in Exynos5800 leads to the following:
> 

Please ignore this patch as suggested by Marek. Instead I'll post a patch
to mark the clock as CLK_IS_CRITICAL, as a temporary workaround until a
proper runtime PM based solution gets merged.

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

Re: [PATCH 2/2] ARM: dts: exynos: Use correct mfc_pd async-bridge clock for Exynos5420

[Krzysztof Kozlowski]

On Thu, Jan 19, 2017 at 07:29:55PM -0300, Javier Martinez Canillas wrote:
> Commit 94aed538e032 ("ARM: dts: exynos: Add async-bridge clock to MFC
> power domain for Exynos5420") fixed an imprecise external abort error
> when the MFC registers were tried to be accessed and the needed clock
> for the asynchronous bridges were gated.
> 
> But according to the Exynos5420 manual the "Gating AXI clock for MFC"
> is not CLK_ACLK333 but CLK_MFC.
> 
> The end effect is the same because CLK_ACLK333 is a parent of CLK_MFC
> but the correct clock should be used instead.
> 
> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
> 
> ---
> 
>  arch/arm/boot/dts/exynos5420.dtsi | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)

Is this still needed?

Best regards,
Krzysztof

> 
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index 906a1a42a7ea..ffb148ea91d6 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -294,7 +294,7 @@
>  			reg = <0x10044060 0x20>;
>  			clocks = <&clock CLK_FIN_PLL>,
>  				 <&clock CLK_MOUT_USER_ACLK333>,
> -				 <&clock CLK_ACLK333>;
> +				 <&clock CLK_MFC>;
>  			clock-names = "oscclk", "clk0","asb0";
>  			#power-domain-cells = <0>;
>  		};
> -- 
> 2.7.4
> 

Re: [PATCH 2/2] ARM: dts: exynos: Use correct mfc_pd async-bridge clock for Exynos5420

[Javier Martinez Canillas]

Hello Krzysztof,

On 01/20/2017 01:28 PM, Krzysztof Kozlowski wrote:
> On Thu, Jan 19, 2017 at 07:29:55PM -0300, Javier Martinez Canillas wrote:
>> Commit 94aed538e032 ("ARM: dts: exynos: Add async-bridge clock to MFC
>> power domain for Exynos5420") fixed an imprecise external abort error
>> when the MFC registers were tried to be accessed and the needed clock
>> for the asynchronous bridges were gated.
>>
>> But according to the Exynos5420 manual the "Gating AXI clock for MFC"
>> is not CLK_ACLK333 but CLK_MFC.
>>
>> The end effect is the same because CLK_ACLK333 is a parent of CLK_MFC
>> but the correct clock should be used instead.
>>
>> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
>>
>> ---
>>
>>  arch/arm/boot/dts/exynos5420.dtsi | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> Is this still needed?
> 

Not really, only if we care about correctness in the existing power domains
that have their clocks defined. But as said, even currently with CLK_ACLK333
works due to the clock hierarchy.

I think is less of an issue now that we prefer to mark clocks that needs to
be ungated as critical instead of growing the DT ABI.

> Best regards,
> Krzysztof
> 
 
Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

Re: [PATCH 2/2] ARM: dts: exynos: Use correct mfc_pd async-bridge clock for Exynos5420

[Krzysztof Kozlowski]

On Fri, Jan 20, 2017 at 02:15:40PM -0300, Javier Martinez Canillas wrote:
> Hello Krzysztof,
> 
> On 01/20/2017 01:28 PM, Krzysztof Kozlowski wrote:
> > On Thu, Jan 19, 2017 at 07:29:55PM -0300, Javier Martinez Canillas wrote:
> >> Commit 94aed538e032 ("ARM: dts: exynos: Add async-bridge clock to MFC
> >> power domain for Exynos5420") fixed an imprecise external abort error
> >> when the MFC registers were tried to be accessed and the needed clock
> >> for the asynchronous bridges were gated.
> >>
> >> But according to the Exynos5420 manual the "Gating AXI clock for MFC"
> >> is not CLK_ACLK333 but CLK_MFC.
> >>
> >> The end effect is the same because CLK_ACLK333 is a parent of CLK_MFC
> >> but the correct clock should be used instead.
> >>
> >> Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
> >>
> >> ---
> >>
> >>  arch/arm/boot/dts/exynos5420.dtsi | 2 +-
> >>  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > Is this still needed?
> > 
> 
> Not really, only if we care about correctness in the existing power domains
> that have their clocks defined. But as said, even currently with CLK_ACLK333
> works due to the clock hierarchy.
> 
> I think is less of an issue now that we prefer to mark clocks that needs to
> be ungated as critical instead of growing the DT ABI.

Okay then, I'll skip the patch. Resend if it turns out to be needed.


Best regards,
Krzysztof