Re: [PATCH 00/36] AArch64 Linux kernel port

From: Arnd Bergmann <arnd@arndb.de>
To: Catalin Marinas <catalin.marinas@arm.com>
Cc: Pavel Machek <pavel@ucw.cz>, Ingo Molnar <mingo@kernel.org>,
	Olof Johansson <olof@lixom.net>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Linus Torvalds <torvalds@linux-foundation.org>,
	Russell King <linux@arm.linux.org.uk>,
	Andrew Morton <akpm@linux-foundation.org>,
	Alan Cox <alan@lxorguk.ukuu.org.uk>
Subject: Re: [PATCH 00/36] AArch64 Linux kernel port
Date: Sun, 15 Jul 2012 19:43:07 +0000	[thread overview]
Message-ID: <201207151943.08183.arnd@arndb.de> (raw)
In-Reply-To: <20120715121644.GB10597@arm.com>

On Sunday 15 July 2012, Catalin Marinas wrote:
> The AArch32 execution mode is optional, so it depends on the actual CPU
> implementation (while AArch64 is mandatory). If the implementation
> supports it, the most likely scenario for AArch32 at kernel level is in
> virtual machines or the secure OS. I'll explain below why.
> 
> The exception (or privilege) levels on an ARMv8 architecture look like
> this:
> 
> Secure World    Normal World
> +-----+
> | EL3 |                         - Secure monitor
> +-----+
>                 +-----+
>                 | EL2 |         - Hypervisor (normal world only)
>                 +-----+
> +-----+         +-----+
> | EL1 |         | EL1 |         - OS kernel (secure or normal)
> +-----+         +-----+
> +-----+         +-----+
> | EL0 |         | EL0 |         - User apps (secure or normal)
> +-----+         +-----+
> 
> In theory, each of these levels (implementation specific) can run both
> AArch32 and AArch64 modes. There is however a restriction on how the
> mode switching is done - this can only happen on a change of exception
> level. When going up the EL the register width (RW) can never go down. A
> lower EL can never have a higher RW than a higher EL.
> 
> Additionally, the RW (the AArch32/AArch64 mode) for an EL is controlled
> by the next higher level (with EL3 hard-wired). An EL cannot cause
> itself to switch between AArch32 and AArch64.

So is the highest level always hardwired to 64-bit on ARMv8?

On a related note: how does the endianess change between
exception levels on ARMv8? Can you switch endianess every time you
move from one level to another? Can any of the levels pick the
endianess for itself?

> So while it is possible, the primary target for 32-bit at the OS kernel
> level is virtualisation. We also don't plan to support a 32-bit SoC on
> ARMv8 systems, given that the compat layer is fully functional.

Yes, I agree that's the best way to handle this. Compared to other
architectures, I think x86 is the only that allows booting either a
32 or 64 bit kernel on the same system. We used to support 32 bit
kernels on 64 bit PowerMac, but nobody used it and we discontinued
it long ago. Tile 64 bit is actually incompatible with 32 bit kernels
at the architecture level and would require a third mode. On sparc,
parisc and mips, AFAIK we could support 32 bit kernels on 64 bit
machines, but never did.

	Arnd