From: Christopher Covington <cov@codeaurora.org>
To: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>
Cc: linux-kernel@vger.kernel.org, Arnd Bergmann <arnd@arndb.de>
Subject: Re: [09/36] AArch64: Exception handling
Date: Thu, 09 Aug 2012 13:05:36 -0400 [thread overview]
Message-ID: <5023EDE0.3070506@codeaurora.org> (raw)
In-Reply-To: <1341608777-12982-10-git-send-email-catalin.marinas@arm.com>
Hi Catalin and Will,
On 01/-10/-28163 02:59 PM, Catalin Marinas wrote:
> The patch contains the exception entry code (kernel/entry.S), pt_regs
> structure and related accessors, undefined instruction trapping and
> stack tracing.
>
> AArch64 Linux kernel (including kernel threads) runs in EL1 mode using
> the SP1 stack. The vectors don't have a fixed address, only alignment
> (2^11) requirements.
[...]
> diff --git a/arch/aarch64/kernel/entry.S b/arch/aarch64/kernel/entry.S
> new file mode 100644
> index 0000000..8ad3995
> --- /dev/null
> +++ b/arch/aarch64/kernel/entry.S
> @@ -0,0 +1,696 @@
> +/*
> + * Low-level exception handling code
[...]
> +/*
> + * Exception vectors.
> + */
> + .macro ventry label
> + .align 7
> + b \label
> + .endm
> +
> + .align 11
> +ENTRY(vectors)
> + ventry el1_sync_invalid // Synchronous EL1t
> + ventry el1_irq_invalid // IRQ EL1t
> + ventry el1_fiq_invalid // FIQ EL1t
> + ventry el1_error_invalid // Error EL1t
> +
> + ventry el1_sync // Synchronous EL1h
> + ventry el1_irq // IRQ EL1h
> + ventry el1_fiq_invalid // FIQ EL1h
> + ventry el1_error_invalid // Error EL1h
> +
> + ventry el0_sync // Synchronous 64-bit EL0
> + ventry el0_irq // IRQ 64-bit EL0
> + ventry el0_fiq_invalid // FIQ 64-bit EL0
> + ventry el0_error_invalid // Error 64-bit EL0
> +
> +#ifdef CONFIG_AARCH32_EMULATION
> + ventry el0_sync_compat // Synchronous 32-bit EL0
> + ventry el0_irq_compat // IRQ 32-bit EL0
> + ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
> + ventry el0_error_invalid_compat // Error 32-bit EL0
> +#else
> + ventry el0_sync_invalid // Synchronous 32-bit EL0
> + ventry el0_irq_invalid // IRQ 32-bit EL0
> + ventry el0_fiq_invalid // FIQ 32-bit EL0
> + ventry el0_error_invalid // Error 32-bit EL0
> +#endif
> +END(vectors)
> +
> +/*
> + * Invalid mode handlers
> + */
> + .macro inv_entry, el, reason, regsize = 64
> + kernel_entry el, \regsize
> + mov x0, sp
> + mov x1, #\reason
> + mrs x2, esr_el1
> + b bad_mode
> + .endm
The code seems to indicate that the invalid mode handlers have different alignment requirements than the valid mode handlers, which puzzles me.
> +
> +el0_sync_invalid:
> + inv_entry 0, BAD_SYNC
> +ENDPROC(el0_sync_invalid)
Plain labels, the ENTRY macro, the END macro and the ENDPROC macro are used variously throughout this file, and I wonder if a greater amount of consistency might be attainable. The description of the ENDPROC macro in include/linux/linkage.h makes me think its use might not be completely warranted in blocks of assembly that don't end with a return instruction.
> +el0_irq_invalid:
> + inv_entry 0, BAD_IRQ
> +ENDPROC(el0_irq_invalid)
> +
> +el0_fiq_invalid:
> + inv_entry 0, BAD_FIQ
> +ENDPROC(el0_fiq_invalid)
> +
> +el0_error_invalid:
> + inv_entry 0, BAD_ERROR
> +ENDPROC(el0_error_invalid)
> +
> +#ifdef CONFIG_AARCH32_EMULATION
> +el0_fiq_invalid_compat:
> + inv_entry 0, BAD_FIQ, 32
> +ENDPROC(el0_fiq_invalid_compat)
> +
> +el0_error_invalid_compat:
> + inv_entry 0, BAD_ERROR, 32
> +ENDPROC(el0_error_invalid_compat)
> +#endif
> +
> +el1_sync_invalid:
> + inv_entry 1, BAD_SYNC
> +ENDPROC(el1_sync_invalid)
> +
> +el1_irq_invalid:
> + inv_entry 1, BAD_IRQ
> +ENDPROC(el1_irq_invalid)
> +
> +el1_fiq_invalid:
> + inv_entry 1, BAD_FIQ
> +ENDPROC(el1_fiq_invalid)
> +
> +el1_error_invalid:
> + inv_entry 1, BAD_ERROR
> +ENDPROC(el1_error_invalid)
> +
> +/*
> + * EL1 mode handlers.
> + */
> + .align 6
> +el1_sync:
> + kernel_entry 1
> + mrs x1, esr_el1 // read the syndrome register
> + lsr x24, x1, #26 // exception class
> + cmp x24, #0x25 // data abort in EL1
> + b.eq el1_da
> + cmp x24, #0x18 // configurable trap
> + b.eq el1_undef
> + cmp x24, #0x26 // stack alignment exception
> + b.eq el1_sp_pc
> + cmp x24, #0x22 // pc alignment exception
> + b.eq el1_sp_pc
> + cmp x24, #0x00 // unknown exception in EL1
> + b.eq el1_undef
> + cmp x24, #0x30 // debug exception in EL1
> + b.ge el1_dbg
> + b el1_inv
> +el1_da:
> + /*
> + * Data abort handling
> + */
> + mrs x0, far_el1
> + enable_dbg_if_not_stepping x2
> + // re-enable interrupts if they were enabled in the aborted context
> + tbnz x23, #7, 1f // PSR_I_BIT
> + enable_irq
> +1:
> + mov x2, sp // struct pt_regs
> + bl do_mem_abort
> +
> + // disable interrupts before pulling preserved data off the stack
> + disable_irq
> + kernel_exit 1
> +el1_sp_pc:
> + /*
> + *Stack or PC alignment exception handling
> + */
> + mrs x0, far_el1
> + mov x1, x25
> + mov x2, sp
> + b do_sp_pc_abort
> +el1_undef:
> + /*
> + *Undefined instruction
> + */
> + mov x0, sp
> + b do_undefinstr
> +el1_dbg:
> + /*
> + * Debug exception handling
> + */
> + tbz x24, #0, el1_inv // EL1 only
> + mrs x0, far_el1
> + mov x2, sp // struct pt_regs
> + bl do_debug_exception
> +
> + kernel_exit 1
> +el1_inv:
> + // TODO: add support for undefined instructions in kernel mode
> + mov x0, sp
> + mov x1, #BAD_SYNC
> + mrs x2, esr_el1
> + b bad_mode
> +ENDPROC(el1_sync)
> +
> + .align 6
> +el1_irq:
> + kernel_entry 1
> + enable_dbg_if_not_stepping x0
> +#ifdef CONFIG_TRACE_IRQFLAGS
> + bl trace_hardirqs_off
> +#endif
> +#ifdef CONFIG_PREEMPT
> + get_thread_info tsk
> + ldr x24, [tsk, #TI_PREEMPT] // get preempt count
> + add x0, x24, #1 // increment it
> + str x0, [tsk, #TI_PREEMPT]
> +#endif
> + irq_handler
> +#ifdef CONFIG_PREEMPT
> + str x24, [tsk, #TI_PREEMPT] // restore preempt count
> + cbnz x24, 1f // preempt count != 0
> + ldr x0, [tsk, #TI_FLAGS] // get flags
> + tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
> + bl el1_preempt
> +1:
> +#endif
> +#ifdef CONFIG_TRACE_IRQFLAGS
> + bl trace_hardirqs_on
> +#endif
> + kernel_exit 1
> +ENDPROC(el1_irq)
> +
> +#ifdef CONFIG_PREEMPT
> +el1_preempt:
> + mov x24, lr
> +1: enable_dbg
> + bl preempt_schedule_irq // irq en/disable is done inside
> + ldr x0, [tsk, #TI_FLAGS] // get new tasks TI_FLAGS
> + tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
> + ret x24
> +#endif
> +
> +/*
> + * EL0 mode handlers.
> + */
> + .align 6
> +el0_sync:
> + kernel_entry 0
> + mrs x25, esr_el1 // read the syndrome register
> + lsr x24, x25, #26 // exception class
> + cmp x24, #0x15 // SVC in 64-bit state
> + b.eq el0_svc
> + adr lr, ret_from_exception
> + cmp x24, #0x24 // data abort in EL0
> + b.eq el0_da
> + cmp x24, #0x20 // instruction abort in EL0
> + b.eq el0_ia
> + cmp x24, #0x07 // FP/ASIMD access
> + b.eq el0_fpsimd_acc
> + cmp x24, #0x2c // FP/ASIMD exception
> + b.eq el0_fpsimd_exc
> + cmp x24, #0x18 // configurable trap
> + b.eq el0_undef
> + cmp x24, #0x26 // stack alignment exception
> + b.eq el0_sp_pc
> + cmp x24, #0x22 // pc alignment exception
> + b.eq el0_sp_pc
> + cmp x24, #0x00 // unknown exception in EL0
> + b.eq el0_undef
> + cmp x24, #0x30 // debug exception in EL0
> + b.ge el0_dbg
> + b el0_inv
> +
> +#ifdef CONFIG_AARCH32_EMULATION
> + .align 6
> +el0_sync_compat:
> + kernel_entry 0, 32
> + mrs x25, esr_el1 // read the syndrome register
> + lsr x24, x25, #26 // exception class
> + cmp x24, #0x11 // SVC in 32-bit state
> + b.eq el0_svc_compat
> + adr lr, ret_from_exception
> + cmp x24, #0x24 // data abort in EL0
> + b.eq el0_da
> + cmp x24, #0x20 // instruction abort in EL0
> + b.eq el0_ia
> + cmp x24, #0x07 // FP/ASIMD access
> + b.eq el0_fpsimd_acc
> + cmp x24, #0x28 // FP/ASIMD exception
> + b.eq el0_fpsimd_exc
> + cmp x24, #0x00 // unknown exception in EL0
> + b.eq el0_undef
> + cmp x24, #0x30 // debug exception in EL0
> + b.ge el0_dbg
> + b el0_inv
> +el0_svc_compat:
> + /*
> + * AArch32 syscall handling
> + */
> + adr stbl, compat_sys_call_table // load compat syscall table pointer
> + uxtw scno, w7 // syscall number in w7 (r7)
> + mov sc_nr, #__NR_compat_syscalls
> + b el0_svc_naked
> +
> + .align 6
> +el0_irq_compat:
> + kernel_entry 0, 32
> + b el0_irq_naked
> +#endif
> +
> +el0_da:
> + /*
> + * Data abort handling
> + */
> + mrs x0, far_el1
> + disable_step x1
> + isb
> + enable_dbg
> + // enable interrupts before calling the main handler
> + enable_irq
> + mov x1, x25
> + mov x2, sp
> + b do_mem_abort
> +el0_ia:
> + /*
> + * Instruction abort handling
> + */
> + mrs x0, far_el1
> + disable_step x1
> + isb
> + enable_dbg
> + // enable interrupts before calling the main handler
> + enable_irq
> + orr x1, x25, #1 << 24 // use reserved ISS bit for instruction aborts
> + mov x2, sp
> + b do_mem_abort
> +el0_fpsimd_acc:
> + /*
> + * Floating Point or Advanced SIMD access
> + */
> + mov x0, x25
> + mov x1, sp
> + b do_fpsimd_acc
> +el0_fpsimd_exc:
> + /*
> + * Floating Point or Advanced SIMD exception
> + */
> + mov x0, x25
> + mov x1, sp
> + b do_fpsimd_exc
> +el0_sp_pc:
> + /*
> + * Stack or PC alignment exception handling
> + */
> + mrs x0, far_el1
> + disable_step x1
> + isb
> + enable_dbg
> + // enable interrupts before calling the main handler
> + enable_irq
> + mov x1, x25
> + mov x2, sp
> + b do_sp_pc_abort
> +el0_undef:
> + /*
> + *Undefined instruction
> + */
> + mov x0, sp
> + b do_undefinstr
> +el0_dbg:
> + /*
> + * Debug exception handling
> + */
> + tbnz x24, #0, el0_inv // EL0 only
> + mrs x0, far_el1
> + disable_step x1
> + mov x1, x25
> + mov x2, sp
> + b do_debug_exception
> +el0_inv:
> + mov x0, sp
> + mov x1, #BAD_SYNC
> + mrs x2, esr_el1
> + b bad_mode
> +ENDPROC(el0_sync)
> +
> + .align 6
> +el0_irq:
> + kernel_entry 0
> +el0_irq_naked:
> + disable_step x1
> + isb
> + enable_dbg
> +#ifdef CONFIG_TRACE_IRQFLAGS
> + bl trace_hardirqs_off
> +#endif
> + get_thread_info tsk
> +#ifdef CONFIG_PREEMPT
> + ldr x24, [tsk, #TI_PREEMPT] // get preempt count
> + add x23, x24, #1 // increment it
> + str x23, [tsk, #TI_PREEMPT]
> +#endif
> + irq_handler
> +#ifdef CONFIG_PREEMPT
> + ldr x0, [tsk, #TI_PREEMPT]
> + str x24, [tsk, #TI_PREEMPT]
> + cmp x0, x23
> + b.eq 1f
> + mov x1, #0
> + str x1, [x1] // BUG
It looks like the error handling here isn't quite complete.
> +1:
> +#endif
> +#ifdef CONFIG_TRACE_IRQFLAGS
> + bl trace_hardirqs_on
> +#endif
> + b ret_to_user
> +ENDPROC(el0_irq)
[...]
Regards,
Christopher
--
Employee of Qualcomm Innovation Center, Inc.
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum
next prev parent reply other threads:[~2012-08-09 17:05 UTC|newest]
Thread overview: 182+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-07-06 21:05 [PATCH 00/36] AArch64 Linux kernel port Catalin Marinas
2012-07-06 21:05 ` [PATCH 01/36] atomic64_test: Simplify the #ifdef for atomic64_dec_if_positive() test Catalin Marinas
2012-07-18 4:33 ` Benjamin Herrenschmidt
2012-07-18 9:06 ` Catalin Marinas
2012-07-06 21:05 ` [PATCH 02/36] ipc: Add COMPAT_SHMLBA support Catalin Marinas
2012-07-18 5:53 ` Jon Masters
2012-07-18 9:03 ` Will Deacon
2012-07-06 21:05 ` [PATCH 03/36] ipc: allow compat IPC version field parsing if !ARCH_WANT_OLD_COMPAT_IPC Catalin Marinas
2012-07-06 21:05 ` [PATCH 04/36] ipc: compat: use signed size_t types for msgsnd and msgrcv Catalin Marinas
2012-07-06 21:05 ` [PATCH 05/36] fs: Build sys_stat64() and friends if __ARCH_WANT_COMPAT_STAT64 Catalin Marinas
2012-07-06 21:05 ` [PATCH 06/36] fdt: Add generic dt_memblock_reserve() function Catalin Marinas
2012-07-07 21:18 ` Rob Herring
2012-07-08 9:43 ` Catalin Marinas
2012-07-06 21:05 ` [PATCH 07/36] AArch64: Assembly macros and definitions Catalin Marinas
2012-07-07 5:57 ` Greg KH
2012-07-08 9:23 ` Catalin Marinas
2012-07-20 14:22 ` [07/36] " Christopher Covington
2012-07-24 16:40 ` Catalin Marinas
2012-07-06 21:05 ` [PATCH 08/36] AArch64: Kernel booting and initialisation Catalin Marinas
2012-07-06 21:32 ` Stephen Warren
2012-07-08 9:18 ` Catalin Marinas
2012-07-23 17:48 ` Stephen Warren
2012-07-23 17:58 ` Catalin Marinas
2012-07-18 6:57 ` Jon Masters
2012-07-18 9:07 ` Will Deacon
2012-07-20 7:11 ` Jon Masters
2012-07-19 17:31 ` Christopher Covington
2012-07-20 7:10 ` Jon Masters
2012-07-20 8:28 ` Arnd Bergmann
2012-07-20 10:52 ` Catalin Marinas
2012-07-20 12:32 ` Geert Uytterhoeven
2012-07-20 13:16 ` Catalin Marinas
2012-07-20 13:47 ` Christopher Covington
2012-07-20 13:52 ` Catalin Marinas
2012-07-20 13:48 ` Catalin Marinas
2012-07-20 14:53 ` Christopher Covington
2012-07-23 20:52 ` [08/36] " Christopher Covington
2012-07-24 16:24 ` Catalin Marinas
2012-07-24 18:53 ` Arnd Bergmann
2012-07-24 23:20 ` Frank Rowand
2012-07-25 8:34 ` Catalin Marinas
2012-07-24 19:42 ` Christopher Covington
2012-07-25 8:47 ` Catalin Marinas
2012-07-25 13:39 ` Christopher Covington
2012-07-06 21:05 ` [PATCH 09/36] AArch64: Exception handling Catalin Marinas
2012-08-09 17:05 ` Christopher Covington [this message]
2012-08-09 17:23 ` [09/36] " Catalin Marinas
2012-08-09 19:19 ` Christopher Covington
2012-07-06 21:05 ` [PATCH 10/36] AArch64: MMU definitions Catalin Marinas
2012-10-02 0:43 ` Jon Masters
2012-10-02 15:39 ` Catalin Marinas
2012-07-06 21:05 ` [PATCH 11/36] AArch64: MMU initialisation Catalin Marinas
2012-07-06 21:05 ` [PATCH 12/36] AArch64: MMU fault handling and page table management Catalin Marinas
2012-07-06 21:05 ` [PATCH 13/36] AArch64: Process management Catalin Marinas
2012-07-06 21:05 ` [PATCH 14/36] AArch64: CPU support Catalin Marinas
2012-07-06 21:05 ` [PATCH 15/36] AArch64: Cache maintenance routines Catalin Marinas
2012-07-06 21:05 ` [PATCH 16/36] AArch64: TLB maintenance functionality Catalin Marinas
2012-07-06 21:05 ` [PATCH 17/36] AArch64: IRQ handling Catalin Marinas
2012-07-06 21:05 ` [PATCH 18/36] AArch64: Atomic operations Catalin Marinas
2012-07-06 21:06 ` [PATCH 19/36] AArch64: Device specific operations Catalin Marinas
2012-07-06 21:06 ` [PATCH 20/36] AArch64: DMA mapping API Catalin Marinas
2012-07-06 21:06 ` [PATCH 21/36] AArch64: SMP support Catalin Marinas
2012-07-06 21:06 ` [PATCH 22/36] AArch64: ELF definitions Catalin Marinas
2012-07-06 21:06 ` [PATCH 23/36] AArch64: System calls handling Catalin Marinas
2012-07-06 21:06 ` [PATCH 24/36] AArch64: VDSO support Catalin Marinas
2012-07-06 21:06 ` [PATCH 25/36] AArch64: Signal handling support Catalin Marinas
2012-07-06 21:06 ` [PATCH 26/36] AArch64: User access library functions Catalin Marinas
2012-07-06 21:06 ` [PATCH 27/36] AArch64: 32-bit (compat) applications support Catalin Marinas
2012-07-06 21:06 ` [PATCH 28/36] AArch64: Floating point and SIMD Catalin Marinas
2012-07-06 21:06 ` [PATCH 29/36] AArch64: Debugging support Catalin Marinas
2012-07-06 21:06 ` [PATCH 30/36] AArch64: Performance counters support Catalin Marinas
2012-07-06 21:06 ` [PATCH 31/36] AArch64: Miscellaneous library functions Catalin Marinas
2012-07-06 21:06 ` [PATCH 32/36] AArch64: Loadable modules Catalin Marinas
2012-07-06 21:06 ` [PATCH 33/36] AArch64: Generic timers support Catalin Marinas
2012-07-12 0:18 ` Linus Walleij
2012-07-12 10:09 ` Marc Zyngier
2012-07-12 10:56 ` Linus Walleij
2012-07-12 16:57 ` John Stultz
2012-07-12 17:31 ` Marc Zyngier
2012-07-12 17:39 ` John Stultz
2012-07-13 12:40 ` Arnd Bergmann
2012-07-13 16:02 ` Catalin Marinas
2012-07-13 16:32 ` Arnd Bergmann
2012-07-13 18:30 ` John Stultz
2012-07-06 21:06 ` [PATCH 34/36] AArch64: Miscellaneous header files Catalin Marinas
2012-07-06 21:06 ` [PATCH 35/36] AArch64: Build infrastructure Catalin Marinas
2012-07-06 21:06 ` [PATCH 36/36] AArch64: MAINTAINERS update Catalin Marinas
2012-08-10 16:24 ` [36/36] " Christopher Covington
2012-07-06 22:58 ` [PATCH 00/36] AArch64 Linux kernel port Alan Cox
2012-07-07 21:30 ` Arnd Bergmann
2012-07-07 23:14 ` Catalin Marinas
2012-07-07 23:29 ` Alan Cox
2012-07-09 11:35 ` Catalin Marinas
2012-07-09 13:51 ` Alan Cox
2012-07-09 15:32 ` Arnd Bergmann
2012-07-09 15:49 ` Alan Cox
2012-07-09 16:02 ` Catalin Marinas
2012-07-09 16:33 ` Arnd Bergmann
2012-07-07 3:29 ` Matthew Garrett
2012-07-09 12:32 ` Mark Brown
2012-07-09 13:06 ` Matthew Garrett
2012-07-09 13:56 ` Mark Brown
2012-07-09 14:02 ` Matthew Garrett
2012-07-09 15:46 ` Mark Brown
2012-07-07 3:53 ` Olof Johansson
2012-07-07 19:27 ` Arnd Bergmann
2012-07-07 23:45 ` Jan Engelhardt
2012-07-08 5:05 ` Henrique de Moraes Holschuh
2012-07-08 20:28 ` Jan Engelhardt
2012-07-08 7:54 ` Jon Masters
2012-07-08 11:17 ` Dr. David Alan Gilbert
2012-07-08 18:13 ` Jon Masters
2012-07-08 18:31 ` Jon Masters
2012-07-08 22:24 ` Dennis Gilmore
2012-07-09 2:01 ` Jon Masters
2012-07-09 8:57 ` Catalin Marinas
2012-07-09 13:33 ` Geert Uytterhoeven
2012-07-08 20:31 ` Jan Engelhardt
2012-07-08 23:32 ` Jon Masters
2012-07-10 7:10 ` Ingo Molnar
2012-07-10 10:10 ` Catalin Marinas
2012-07-10 15:33 ` Alan Cox
2012-07-10 16:52 ` Arnd Bergmann
2012-07-10 20:35 ` Ingo Molnar
2012-07-10 21:19 ` Arnd Bergmann
2012-07-10 21:48 ` Catalin Marinas
2012-07-11 8:20 ` Ingo Molnar
2012-07-11 11:30 ` Alan Cox
2012-07-10 21:44 ` Catalin Marinas
2012-07-11 8:55 ` Catalin Marinas
2012-07-11 5:26 ` Rusty Russell
2012-07-11 10:53 ` Catalin Marinas
2012-07-12 2:08 ` Rusty Russell
2012-07-10 16:57 ` Catalin Marinas
2012-07-10 16:52 ` Dennis Gilmore
2012-07-10 17:14 ` Joe Perches
2012-07-10 18:01 ` Jan Ceuleers
2012-07-10 18:05 ` richard -rw- weinberger
2012-07-10 20:16 ` Alexander Holler
2012-07-14 22:16 ` Jon Masters
2012-07-10 22:08 ` Chris Adams
2012-07-14 9:30 ` Pavel Machek
2012-07-15 12:16 ` Catalin Marinas
2012-07-15 19:43 ` Arnd Bergmann
2012-07-15 21:33 ` Catalin Marinas
2012-07-16 12:16 ` Pavel Machek
2012-07-17 7:05 ` Jon Masters
2012-07-17 8:02 ` Arnd Bergmann
2012-07-17 9:50 ` Alan Cox
2012-07-18 2:36 ` Jon Masters
2012-07-17 10:45 ` Catalin Marinas
2012-07-16 9:26 ` Geert Uytterhoeven
2012-07-17 6:53 ` Christoph Hellwig
2012-07-17 8:07 ` Arnd Bergmann
2012-07-16 8:24 ` Avi Kivity
2012-07-17 7:09 ` Jon Masters
2012-07-17 8:37 ` Catalin Marinas
2012-07-15 23:21 ` Måns Rullgård
2012-07-15 23:53 ` Linus Torvalds
2012-07-17 22:18 ` Catalin Marinas
2012-07-17 22:35 ` Joe Perches
2012-07-18 2:33 ` Jon Masters
2012-07-18 15:27 ` Dennis Gilmore
2012-07-18 17:14 ` Catalin Marinas
2012-07-18 17:25 ` Måns Rullgård
2012-07-18 19:35 ` Jon Masters
2012-07-18 19:55 ` Linus Torvalds
2012-07-19 14:16 ` Guillem Jover
2012-07-07 23:42 ` Jan Engelhardt
2012-07-08 10:18 ` Catalin Marinas
2012-07-09 12:31 ` Jan Engelhardt
2012-07-07 9:30 ` Mikael Pettersson
2012-07-07 19:21 ` Kirill A. Shutemov
2012-07-10 10:12 ` Catalin Marinas
2012-07-14 9:35 ` Pavel Machek
2012-07-15 11:36 ` Catalin Marinas
2012-07-16 16:19 ` Pavel Machek
2012-07-16 19:45 ` Arnd Bergmann
2012-07-16 19:47 ` Måns Rullgård
2012-07-18 5:35 ` Jon Masters
2012-07-18 9:13 ` Catalin Marinas
2012-07-26 11:59 ` Catalin Marinas
[not found] <jknWN-4WG-3@gated-at.bofh.it>
[not found] ` <jkulA-O3-3@gated-at.bofh.it>
[not found] ` <jkIRz-2Hu-11@gated-at.bofh.it>
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