Re: [PATCH v11 0/4] Introducing a queue read/write lock implementation

[Will Deacon <will.deacon@arm.com>]

Hi Peter,

On Thu, Jan 30, 2014 at 03:44:00PM +0000, Peter Zijlstra wrote:
> Something like this would work for ARM and PPC, although I didn't do the
> PPC variant of atomic_sub_release().
> 
> 
> --- a/arch/arm64/include/asm/atomic.h
> +++ b/arch/arm64/include/asm/atomic.h
> @@ -90,6 +90,21 @@ static inline void atomic_sub(int i, ato
>  	: "cc");
>  }
>  
> +static inline void atomic_sub_release(int i, atomic_t *v)
> +{
> +	unsigned long tmp;
> +	int result;
> +
> +	asm volatile("// atomic_sub\n"
> +"1:	ldxr	%w0, %2\n"
> +"	sub	%w0, %w0, %w3\n"
> +"	stlxr	%w1, %w0, %2\n"
> +"	cbnz	%w1, 1b"
> +	: "=&r" (result), "=&r" (tmp), "+Q" (v->counter)
> +	: "Ir" (i)
> +	: "cc");

Probably want to replace this "cc" with a "memory".

> --- /dev/null
> +++ b/arch/arm64/include/asm/qrwlock.h
> @@ -0,0 +1,21 @@
> +#ifndef _ASM_ARM64_QRWLOCK_H
> +#define _ASM_ARM64_QRWLOCK_H
> +
> +#include <asm-generic/qrwlock_types.h>
> +
> +#define queue_read_unlock queue_read_unlock
> +static inline void queue_read_unlock(struct qrwlock *lock)
> +{
> +	atomic_sub_release(_QR_BIAS, &lock->cnts);
> +}
> +
> +#define queue_write_unlock queue_write_unlock
> +static inline void queue_write_unlock(struct qrwlock *lock)
> +{
> +	atomic_sub_release(_QW_LOCKED, &lock->cnts);
> +}
> +
> +#include <asm-generic/qrwlock.h>
> +
> +#endif /* _ASM_ARM64_QRWLOCK_H */

It would be nice if these were default implementations of the unlock, then
architectures just implement atomic_sub_release how they like.

One thing worth mentioning: I have a fairly invasive set of changes pending
for arch/arm64/include/asm/atomic.h, so if you do decide to go with this,
I'm more than happy to take the sub_release part via the arm64 tree. I guess
it depends on when this is likely to get merged.

Cheers,

Will