Re: [PATCH v2 16/18] x86: io: implement dummy relaxed accessor macros for writes

[Will Deacon <will.deacon@arm.com>]

Hi Peter,

On Thu, May 22, 2014 at 06:15:27PM +0100, H. Peter Anvin wrote:
> On 05/22/2014 09:47 AM, Will Deacon wrote:
> > write{b,w,l,q}_relaxed are implemented by some architectures in order to
> > permit memory-mapped I/O accesses with weaker barrier semantics than the
> > non-relaxed variants.
> > 
> > This patch adds dummy macros for the read and write accessors to x86,
> > which simply expand to the non-relaxed variants. Note that this
> > strengthens the relaxed read accessors, since they are now ordered with
> > respect to each other by way of a compiler barrier.
> 
> OK, do we want/need that compiler barrier?  And you say "strengthens" -
> strengthens with respect to what if we didn't have them before?

Actually, x86 does already implement the relaxed read accessors:

	#define readb_relaxed(a) __readb(a)
	#define readw_relaxed(a) __readw(a)
	#define readl_relaxed(a) __readl(a)

where __read* don't have "memory" clobbers, unlike the read* implementations.

I would like the relaxed accessors to be ordered with respect to each other
but, looking again, that is already achieved through the use of volatile asm
so I've come full circle and decided that we don't need the clobbers after
all.

What do you think?

Will