From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>,
Viresh Kumar <viresh.linux@gmail.com>,
Shiraz Hashim <shiraz.linux.kernel@gmail.com>,
spear-devel@list.st.com
Subject: [patch 06/13] irqchip: spear_shirq: Reorder the spear320 ras blocks
Date: Thu, 19 Jun 2014 21:34:40 -0000 [thread overview]
Message-ID: <20140619212713.310591579@linutronix.de> (raw)
In-Reply-To: 20140619212606.431750473@linutronix.de
[-- Attachment #1: spear-reorder-320.patch --]
[-- Type: text/plain, Size: 1688 bytes --]
Order the ras blocks in the order of interrupts not alphabetically.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
drivers/irqchip/spear-shirq.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
Index: linux/drivers/irqchip/spear-shirq.c
===================================================================
--- linux.orig/drivers/irqchip/spear-shirq.c
+++ linux/drivers/irqchip/spear-shirq.c
@@ -138,20 +138,22 @@ static struct spear_shirq *spear310_shir
#define SPEAR320_INT_CLR_MASK_REG 0x04
#define SPEAR320_INT_ENB_MASK_REG 0x08
-static struct spear_shirq spear320_shirq_ras1 = {
- .offset = 7,
- .nr_irqs = 3,
+static struct spear_shirq spear320_shirq_ras3 = {
+ .offset = 0,
+ .nr_irqs = 7,
+ .disabled = 1,
.regs = {
- .enb_reg = -1,
+ .enb_reg = SPEAR320_INT_ENB_MASK_REG,
+ .reset_to_enb = 1,
.status_reg = SPEAR320_INT_STS_MASK_REG,
.clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,
},
};
-static struct spear_shirq spear320_shirq_ras2 = {
- .offset = 10,
- .nr_irqs = 1,
+static struct spear_shirq spear320_shirq_ras1 = {
+ .offset = 7,
+ .nr_irqs = 3,
.regs = {
.enb_reg = -1,
.status_reg = SPEAR320_INT_STS_MASK_REG,
@@ -160,13 +162,11 @@ static struct spear_shirq spear320_shirq
},
};
-static struct spear_shirq spear320_shirq_ras3 = {
- .offset = 0,
- .nr_irqs = 7,
- .disabled = 1,
+static struct spear_shirq spear320_shirq_ras2 = {
+ .offset = 10,
+ .nr_irqs = 1,
.regs = {
- .enb_reg = SPEAR320_INT_ENB_MASK_REG,
- .reset_to_enb = 1,
+ .enb_reg = -1,
.status_reg = SPEAR320_INT_STS_MASK_REG,
.clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,
next prev parent reply other threads:[~2014-06-19 21:34 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-19 21:34 [patch 00/13] irqchip: spear_shirq: Cleanup the bitrot Thomas Gleixner
2014-06-19 21:34 ` [patch 01/13] irqchip: spear_shirq: Fix interrupt offset Thomas Gleixner
2014-06-21 23:30 ` Jason Cooper
2014-06-19 21:34 ` [patch 02/13] irqchip: spear_shirq: Kill pointless static Thomas Gleixner
2014-06-19 21:34 ` [patch 03/13] irqchip: spear_shirq: Move private structs to source Thomas Gleixner
2014-06-19 21:34 ` [patch 05/13] irqchip: spear_shirq: Namespace cleanup Thomas Gleixner
2014-06-19 21:34 ` [patch 04/13] irqchip: spear_shirq: No point in storing the parent irq Thomas Gleixner
2014-06-19 21:34 ` [patch 07/13] irqchip: spear_shirq: Use the proper interfaces Thomas Gleixner
2014-06-19 21:34 ` Thomas Gleixner [this message]
2014-06-19 21:34 ` [patch 08/13] irqchip: spear_shirq: Precalculate status mask Thomas Gleixner
2014-06-20 7:19 ` Viresh Kumar
2014-06-20 8:06 ` Thomas Gleixner
2014-06-20 8:19 ` Viresh Kumar
2014-06-19 21:34 ` [patch 09/13] irqchip: spear_shirq: Kill the clear_reg nonsense Thomas Gleixner
2014-06-20 7:05 ` Viresh Kumar
2014-06-20 8:00 ` Thomas Gleixner
2014-06-19 21:34 ` [patch 10/13] irqchip: spear_shirq: Simplify chained handler Thomas Gleixner
2014-06-19 21:34 ` [patch 11/13] irqchip: spear_shirq: Remove the parent irq "ack"/unmask Thomas Gleixner
2014-06-19 21:34 ` [patch 12/13] irqchip: spear_shirq: Use proper irq chips for the different SoCs Thomas Gleixner
2014-06-19 21:34 ` [patch 13/13] irqchip: spear_shirq: Simplify register access code Thomas Gleixner
2014-06-20 7:09 ` Viresh Kumar
2014-06-20 8:05 ` Thomas Gleixner
2014-06-20 8:24 ` Viresh Kumar
2014-06-20 9:20 ` [patch 00/13] irqchip: spear_shirq: Cleanup the bitrot Viresh Kumar
2014-06-23 8:25 ` Viresh Kumar
2014-06-24 12:45 ` Jason Cooper
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