From: Viresh Kumar <viresh.kumar@linaro.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>,
Jason Cooper <jason@lakedaemon.net>,
Shiraz Hashim <shiraz.linux.kernel@gmail.com>,
spear-devel <spear-devel@list.st.com>
Subject: Re: [patch 09/13] irqchip: spear_shirq: Kill the clear_reg nonsense
Date: Fri, 20 Jun 2014 12:35:00 +0530 [thread overview]
Message-ID: <CAOh2x==nhq6OHkd9U17L3r-_7qnnjYLyiqiKYpGdMuSVEj07=g@mail.gmail.com> (raw)
In-Reply-To: <20140619212713.570396433@linutronix.de>
On Fri, Jun 20, 2014 at 3:04 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
> None of the chips has a ACK register.
I need to recheck on this after looking at datasheets. Arranging for
them, will revert by tomorrow.
> The code brainlessly fiddles
> with the enable register, so it might even reenable a disabled
> interrupt at least on spear300.
Ack/Clear register is only configured for SPEAr320, how will it
make a difference to SPEAr300 ?
And for SPEAr320 as well, the offset mentioned in code for clear
register is different then ENABLE register.
> Index: linux/drivers/irqchip/spear-shirq.c
> ===================================================================
> --- linux.orig/drivers/irqchip/spear-shirq.c
> +++ linux/drivers/irqchip/spear-shirq.c
> @@ -33,15 +33,11 @@
> * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
> * status_reg: status register offset
> * status_reg_mask: status register valid mask
> - * clear_reg: clear register offset
> - * reset_to_clear: val 1 indicates, we need to clear bit for clearing interrupt
> */
> struct shirq_regs {
> u32 enb_reg;
> u32 reset_to_enb;
> u32 status_reg;
> - u32 clear_reg;
> - u32 reset_to_clear;
AFAIR, there was a revision for SPEAr320 which was actually using
reset_to_clear and so was present in code. But later revisions got rid
of it and code never got updated.
> @@ -150,13 +141,6 @@ static struct spear_shirq spear320_shirq
> .nr_irqs = 7,
> .mask = ((0x1 << 7) - 1) << 0,
> .disabled = 1,
> - .regs = {
> - .enb_reg = SPEAR320_INT_ENB_MASK_REG,
> - .reset_to_enb = 1,
> - .status_reg = SPEAR320_INT_STS_MASK_REG,
> - .clear_reg = SPEAR320_INT_CLR_MASK_REG,
> - .reset_to_clear = 1,
> - },
Was removing .regs completely intentional?
I don't see these registers getting added again in later patches.
next prev parent reply other threads:[~2014-06-20 7:05 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-19 21:34 [patch 00/13] irqchip: spear_shirq: Cleanup the bitrot Thomas Gleixner
2014-06-19 21:34 ` [patch 01/13] irqchip: spear_shirq: Fix interrupt offset Thomas Gleixner
2014-06-21 23:30 ` Jason Cooper
2014-06-19 21:34 ` [patch 02/13] irqchip: spear_shirq: Kill pointless static Thomas Gleixner
2014-06-19 21:34 ` [patch 03/13] irqchip: spear_shirq: Move private structs to source Thomas Gleixner
2014-06-19 21:34 ` [patch 05/13] irqchip: spear_shirq: Namespace cleanup Thomas Gleixner
2014-06-19 21:34 ` [patch 04/13] irqchip: spear_shirq: No point in storing the parent irq Thomas Gleixner
2014-06-19 21:34 ` [patch 07/13] irqchip: spear_shirq: Use the proper interfaces Thomas Gleixner
2014-06-19 21:34 ` [patch 06/13] irqchip: spear_shirq: Reorder the spear320 ras blocks Thomas Gleixner
2014-06-19 21:34 ` [patch 08/13] irqchip: spear_shirq: Precalculate status mask Thomas Gleixner
2014-06-20 7:19 ` Viresh Kumar
2014-06-20 8:06 ` Thomas Gleixner
2014-06-20 8:19 ` Viresh Kumar
2014-06-19 21:34 ` [patch 09/13] irqchip: spear_shirq: Kill the clear_reg nonsense Thomas Gleixner
2014-06-20 7:05 ` Viresh Kumar [this message]
2014-06-20 8:00 ` Thomas Gleixner
2014-06-19 21:34 ` [patch 10/13] irqchip: spear_shirq: Simplify chained handler Thomas Gleixner
2014-06-19 21:34 ` [patch 11/13] irqchip: spear_shirq: Remove the parent irq "ack"/unmask Thomas Gleixner
2014-06-19 21:34 ` [patch 12/13] irqchip: spear_shirq: Use proper irq chips for the different SoCs Thomas Gleixner
2014-06-19 21:34 ` [patch 13/13] irqchip: spear_shirq: Simplify register access code Thomas Gleixner
2014-06-20 7:09 ` Viresh Kumar
2014-06-20 8:05 ` Thomas Gleixner
2014-06-20 8:24 ` Viresh Kumar
2014-06-20 9:20 ` [patch 00/13] irqchip: spear_shirq: Cleanup the bitrot Viresh Kumar
2014-06-23 8:25 ` Viresh Kumar
2014-06-24 12:45 ` Jason Cooper
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='CAOh2x==nhq6OHkd9U17L3r-_7qnnjYLyiqiKYpGdMuSVEj07=g@mail.gmail.com' \
--to=viresh.kumar@linaro.org \
--cc=jason@lakedaemon.net \
--cc=linux-kernel@vger.kernel.org \
--cc=shiraz.linux.kernel@gmail.com \
--cc=spear-devel@list.st.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).