From: Thomas Gleixner <tglx@linutronix.de>
To: LKML <linux-kernel@vger.kernel.org>
Cc: Jason Cooper <jason@lakedaemon.net>,
Viresh Kumar <viresh.linux@gmail.com>,
Shiraz Hashim <shiraz.linux.kernel@gmail.com>,
spear-devel@list.st.com
Subject: [patch 13/13] irqchip: spear_shirq: Simplify register access code
Date: Thu, 19 Jun 2014 21:34:44 -0000 [thread overview]
Message-ID: <20140619212713.923306179@linutronix.de> (raw)
In-Reply-To: 20140619212606.431750473@linutronix.de
[-- Attachment #1: spear-irqchip-optimize-register-access.patch --]
[-- Type: text/plain, Size: 5113 bytes --]
The extra register data structure is pointless. Move the offsets of
the status and the mask register into the shirq block structure.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
drivers/irqchip/spear-shirq.c | 61 +++++++++++-------------------------------
1 file changed, 16 insertions(+), 45 deletions(-)
Index: linux/drivers/irqchip/spear-shirq.c
===================================================================
--- linux.orig/drivers/irqchip/spear-shirq.c
+++ linux/drivers/irqchip/spear-shirq.c
@@ -27,24 +27,11 @@
#include "irqchip.h"
/*
- * struct shirq_regs: shared irq register configuration
- *
- * enb_reg: enable register offset
- * reset_to_enb: val 1 indicates, we need to clear bit for enabling interrupt
- * status_reg: status register offset
- * status_reg_mask: status register valid mask
- */
-struct shirq_regs {
- u32 enb_reg;
- u32 reset_to_enb;
- u32 status_reg;
-};
-
-/*
* struct spear_shirq: shared irq structure
*
* base: Base register address
- * regs: Register configuration for shared irq block
+ * status_reg: Status register offset for chained interrupt handler
+ * mask_reg: Mask register offset for irq chip
* mask: Mask to apply to the status register
* virq_base: Base virtual interrupt number
* nr_irqs: Number of interrupts handled by this block
@@ -54,7 +41,8 @@ struct shirq_regs {
*/
struct spear_shirq {
void __iomem *base;
- struct shirq_regs regs;
+ u32 status_reg;
+ u32 mask_reg;
u32 mask;
u32 virq_base;
u32 nr_irqs;
@@ -72,7 +60,7 @@ static void shirq_irq_mask(struct irq_da
{
struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
- u32 __iomem *reg = shirq->base + shirq->regs.enb_reg;
+ u32 __iomem *reg = shirq->base + shirq->mask_reg;
raw_spin_lock(&shirq_lock);
val = readl(reg) & ~(0x1 << shift);
@@ -84,7 +72,7 @@ static void shirq_irq_unmask(struct irq_
{
struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
- u32 __iomem *reg = shirq->base + shirq->regs.enb_reg;
+ u32 __iomem *reg = shirq->base + shirq->mask_reg;
raw_spin_lock(&shirq_lock);
val = readl(reg) | (0x1 << shift);
@@ -103,10 +91,8 @@ static struct spear_shirq spear300_shirq
.nr_irqs = 9,
.mask = ((0x1 << 9) - 1) << 0,
.irq_chip = &shirq_chip,
- .regs = {
- .enb_reg = SPEAR300_INT_ENB_MASK_REG,
- .status_reg = SPEAR300_INT_STS_MASK_REG,
- },
+ .status_reg = SPEAR300_INT_STS_MASK_REG,
+ .mask_reg = SPEAR300_INT_ENB_MASK_REG,
};
static struct spear_shirq *spear300_shirq_blocks[] = {
@@ -121,9 +107,7 @@ static struct spear_shirq spear310_shirq
.nr_irqs = 8,
.mask = ((0x1 << 8) - 1) << 0,
.irq_chip = &dummy_irq_chip,
- .regs = {
- .status_reg = SPEAR310_INT_STS_MASK_REG,
- },
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
};
static struct spear_shirq spear310_shirq_ras2 = {
@@ -131,10 +115,7 @@ static struct spear_shirq spear310_shirq
.nr_irqs = 5,
.mask = ((0x1 << 5) - 1) << 8,
.irq_chip = &dummy_irq_chip,
- .regs = {
- .enb_reg = -1,
- .status_reg = SPEAR310_INT_STS_MASK_REG,
- },
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
};
static struct spear_shirq spear310_shirq_ras3 = {
@@ -142,9 +123,7 @@ static struct spear_shirq spear310_shirq
.nr_irqs = 1,
.mask = ((0x1 << 1) - 1) << 13,
.irq_chip = &dummy_irq_chip,
- .regs = {
- .status_reg = SPEAR310_INT_STS_MASK_REG,
- },
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
};
static struct spear_shirq spear310_shirq_intrcomm_ras = {
@@ -152,9 +131,7 @@ static struct spear_shirq spear310_shirq
.nr_irqs = 3,
.mask = ((0x1 << 3) - 1) << 14,
.irq_chip = &dummy_irq_chip,
- .regs = {
- .status_reg = SPEAR310_INT_STS_MASK_REG,
- },
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
};
static struct spear_shirq *spear310_shirq_blocks[] = {
@@ -180,9 +157,7 @@ static struct spear_shirq spear320_shirq
.nr_irqs = 3,
.mask = ((0x1 << 3) - 1) << 7,
.irq_chip = &dummy_irq_chip,
- .regs = {
- .status_reg = SPEAR320_INT_STS_MASK_REG,
- },
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
};
static struct spear_shirq spear320_shirq_ras2 = {
@@ -190,9 +165,7 @@ static struct spear_shirq spear320_shirq
.nr_irqs = 1,
.mask = ((0x1 << 1) - 1) << 10,
.irq_chip = &dummy_irq_chip,
- .regs = {
- .status_reg = SPEAR320_INT_STS_MASK_REG,
- },
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
};
static struct spear_shirq spear320_shirq_intrcomm_ras = {
@@ -200,9 +173,7 @@ static struct spear_shirq spear320_shirq
.nr_irqs = 11,
.mask = ((0x1 << 11) - 1) << 11,
.irq_chip = &dummy_irq_chip,
- .regs = {
- .status_reg = SPEAR320_INT_STS_MASK_REG,
- },
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
};
static struct spear_shirq *spear320_shirq_blocks[] = {
@@ -217,7 +188,7 @@ static void shirq_handler(unsigned irq,
struct spear_shirq *shirq = irq_get_handler_data(irq);
u32 pend;
- pend = readl(shirq->base + shirq->regs.status_reg) & shirq->mask;
+ pend = readl(shirq->base + shirq->status_reg) & shirq->mask;
pend >>= shirq->offset;
while (pend) {
next prev parent reply other threads:[~2014-06-19 21:34 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-19 21:34 [patch 00/13] irqchip: spear_shirq: Cleanup the bitrot Thomas Gleixner
2014-06-19 21:34 ` [patch 01/13] irqchip: spear_shirq: Fix interrupt offset Thomas Gleixner
2014-06-21 23:30 ` Jason Cooper
2014-06-19 21:34 ` [patch 02/13] irqchip: spear_shirq: Kill pointless static Thomas Gleixner
2014-06-19 21:34 ` [patch 03/13] irqchip: spear_shirq: Move private structs to source Thomas Gleixner
2014-06-19 21:34 ` [patch 05/13] irqchip: spear_shirq: Namespace cleanup Thomas Gleixner
2014-06-19 21:34 ` [patch 04/13] irqchip: spear_shirq: No point in storing the parent irq Thomas Gleixner
2014-06-19 21:34 ` [patch 07/13] irqchip: spear_shirq: Use the proper interfaces Thomas Gleixner
2014-06-19 21:34 ` [patch 06/13] irqchip: spear_shirq: Reorder the spear320 ras blocks Thomas Gleixner
2014-06-19 21:34 ` [patch 08/13] irqchip: spear_shirq: Precalculate status mask Thomas Gleixner
2014-06-20 7:19 ` Viresh Kumar
2014-06-20 8:06 ` Thomas Gleixner
2014-06-20 8:19 ` Viresh Kumar
2014-06-19 21:34 ` [patch 09/13] irqchip: spear_shirq: Kill the clear_reg nonsense Thomas Gleixner
2014-06-20 7:05 ` Viresh Kumar
2014-06-20 8:00 ` Thomas Gleixner
2014-06-19 21:34 ` [patch 10/13] irqchip: spear_shirq: Simplify chained handler Thomas Gleixner
2014-06-19 21:34 ` [patch 11/13] irqchip: spear_shirq: Remove the parent irq "ack"/unmask Thomas Gleixner
2014-06-19 21:34 ` [patch 12/13] irqchip: spear_shirq: Use proper irq chips for the different SoCs Thomas Gleixner
2014-06-19 21:34 ` Thomas Gleixner [this message]
2014-06-20 7:09 ` [patch 13/13] irqchip: spear_shirq: Simplify register access code Viresh Kumar
2014-06-20 8:05 ` Thomas Gleixner
2014-06-20 8:24 ` Viresh Kumar
2014-06-20 9:20 ` [patch 00/13] irqchip: spear_shirq: Cleanup the bitrot Viresh Kumar
2014-06-23 8:25 ` Viresh Kumar
2014-06-24 12:45 ` Jason Cooper
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20140619212713.923306179@linutronix.de \
--to=tglx@linutronix.de \
--cc=jason@lakedaemon.net \
--cc=linux-kernel@vger.kernel.org \
--cc=shiraz.linux.kernel@gmail.com \
--cc=spear-devel@list.st.com \
--cc=viresh.linux@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).