From: Viresh Kumar <viresh.kumar@linaro.org>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: LKML <linux-kernel@vger.kernel.org>,
Jason Cooper <jason@lakedaemon.net>,
Shiraz Hashim <shiraz.linux.kernel@gmail.com>,
spear-devel <spear-devel@list.st.com>
Subject: Re: [patch 13/13] irqchip: spear_shirq: Simplify register access code
Date: Fri, 20 Jun 2014 13:54:38 +0530 [thread overview]
Message-ID: <CAKohpomcQh_EtM1vzn1Od1uZNK2K2BAGCzbriXc4VQn3PdCYhw@mail.gmail.com> (raw)
In-Reply-To: <alpine.DEB.2.10.1406201000441.5170@nanos>
On 20 June 2014 13:35, Thomas Gleixner <tglx@linutronix.de> wrote:
> On Fri, 20 Jun 2014, Viresh Kumar wrote:
>> On Fri, Jun 20, 2014 at 3:04 AM, Thomas Gleixner <tglx@linutronix.de> wrote:
>>
>> > Index: linux/drivers/irqchip/spear-shirq.c
>> > -struct shirq_regs {
>> > - u32 enb_reg;
>> > - u32 reset_to_enb;
>>
>> I don't see something similar to 'reset_to_enb' is added again.
>> AFAICT, this field is being used by two blocks:
>>
>> spear300_shirq_ras1: writes 0 to this. i.e. we need to write 0 to
>> mask the interrupt
>>
>> and
>>
>> spear320_shirq_ras3: writes 1 to this. i.e. we need to write 1 to
>> mask the interrupt.
>
> AGAIN: spear320_shirq_ras3 is never instantiated as a chained irq. So
> the chip for these interrupts is never set.
Didn't knew it, yes spear320_shirq_ras3 is never registered.
> And if it ever is, you need a separate irq chip for it and not some
> conditional hackery.
Yeah.
>> And so the new code you have added breaks it for SPEAr300 ?
>
> +static void shirq_irq_mask(struct irq_data *d)
> +{
> + struct spear_shirq *shirq = irq_data_get_irq_chip_data(d);
> + u32 val, shift = d->irq - shirq->virq_base + shirq->offset;
> + u32 __iomem *reg = shirq->base + shirq->regs.enb_reg;
> +
> + raw_spin_lock(&shirq_lock);
> + val = readl(reg) & ~(0x1 << shift);
> + writel(val, reg);
> + raw_spin_unlock(&shirq_lock);
> +}
>
> That's the mask function for 300 and it clears the bit, right?
Yeah, that looks fine. Misread it.
next prev parent reply other threads:[~2014-06-20 8:24 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-06-19 21:34 [patch 00/13] irqchip: spear_shirq: Cleanup the bitrot Thomas Gleixner
2014-06-19 21:34 ` [patch 01/13] irqchip: spear_shirq: Fix interrupt offset Thomas Gleixner
2014-06-21 23:30 ` Jason Cooper
2014-06-19 21:34 ` [patch 02/13] irqchip: spear_shirq: Kill pointless static Thomas Gleixner
2014-06-19 21:34 ` [patch 03/13] irqchip: spear_shirq: Move private structs to source Thomas Gleixner
2014-06-19 21:34 ` [patch 05/13] irqchip: spear_shirq: Namespace cleanup Thomas Gleixner
2014-06-19 21:34 ` [patch 04/13] irqchip: spear_shirq: No point in storing the parent irq Thomas Gleixner
2014-06-19 21:34 ` [patch 07/13] irqchip: spear_shirq: Use the proper interfaces Thomas Gleixner
2014-06-19 21:34 ` [patch 06/13] irqchip: spear_shirq: Reorder the spear320 ras blocks Thomas Gleixner
2014-06-19 21:34 ` [patch 08/13] irqchip: spear_shirq: Precalculate status mask Thomas Gleixner
2014-06-20 7:19 ` Viresh Kumar
2014-06-20 8:06 ` Thomas Gleixner
2014-06-20 8:19 ` Viresh Kumar
2014-06-19 21:34 ` [patch 09/13] irqchip: spear_shirq: Kill the clear_reg nonsense Thomas Gleixner
2014-06-20 7:05 ` Viresh Kumar
2014-06-20 8:00 ` Thomas Gleixner
2014-06-19 21:34 ` [patch 10/13] irqchip: spear_shirq: Simplify chained handler Thomas Gleixner
2014-06-19 21:34 ` [patch 11/13] irqchip: spear_shirq: Remove the parent irq "ack"/unmask Thomas Gleixner
2014-06-19 21:34 ` [patch 12/13] irqchip: spear_shirq: Use proper irq chips for the different SoCs Thomas Gleixner
2014-06-19 21:34 ` [patch 13/13] irqchip: spear_shirq: Simplify register access code Thomas Gleixner
2014-06-20 7:09 ` Viresh Kumar
2014-06-20 8:05 ` Thomas Gleixner
2014-06-20 8:24 ` Viresh Kumar [this message]
2014-06-20 9:20 ` [patch 00/13] irqchip: spear_shirq: Cleanup the bitrot Viresh Kumar
2014-06-23 8:25 ` Viresh Kumar
2014-06-24 12:45 ` Jason Cooper
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