[PATCH 1/5] x86, intel: Introduce macros for Intel family numbers

* [PATCH 1/5] x86, intel: Introduce macros for Intel family numbers
@ 2016-06-01 17:34 Dave Hansen
  2016-06-01 17:34 ` [PATCH 2/5] x86, perf: use Intel family macros for core perf events Dave Hansen
                   ` (3 more replies)
  0 siblings, 4 replies; 6+ messages in thread
From: Dave Hansen @ 2016-06-01 17:34 UTC (permalink / raw)
  To: linux-kernel; +Cc: x86, Dave Hansen, dave.hansen


From: Dave Hansen <dave.hansen@linux.intel.com>

We have at least four long lists of open-coded family-6 model
numbers.  Half of them have these model numbers in hex and the
other half in decimal.  This makes grepping for them tons of
fun, if you were to try.

So, let's consolidate them.  Put all the definitions in one
header.  While people have been _pretty_ good at making sure to
hit all four places in the code when Intel puts out a new CPU, we
have not been perfect, and this should make it easier.

The names here are closely derived from the comments describing
the models from arch/x86/events/intel/core.c.  We could easily
make them shorter by doing things like s/SANDYBRIDGE/SNB/, but
they seemed fine even with the longer versions to me.

Do not take any of these names too literally, like "DESKTOP"
or "MOBILE".  These are all colloquial names and not precise
descriptions of everywhere a given model will show up.

Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
---

 b/arch/x86/include/asm/intel-family.h |   57 ++++++++++++++++++++++++++++++++++
 1 file changed, 57 insertions(+)

diff -puN /dev/null arch/x86/include/asm/intel-family.h

--- /dev/null	2016-04-04 09:40:43.435149254 -0700
+++ b/arch/x86/include/asm/intel-family.h	2016-06-01 10:20:10.786311716 -0700
@@ -0,0 +1,57 @@
+#ifndef _ASM_X86_INTEL_FAMILY_H
+#define _ASM_X86_INTEL_FAMILY_H
+
+/*
+ * "Big Core" Processors (Branded as Core, Xeon, etc...)
+ *
+ * The "_X" parts are generally the EP and EX Xeons, or the
+ * "Extreme" ones, like Broadwell-E.
+ */
+
+#define INTEL_FAM6_MODEL_CORE_YONAH		0x0E
+#define INTEL_FAM6_MODEL_CORE2_MEROM		0x0F
+#define INTEL_FAM6_MODEL_CORE2_MEROM_L		0x16
+#define INTEL_FAM6_MODEL_CORE2_PENRYN		0x17
+#define INTEL_FAM6_MODEL_CORE2_DUNNINGTON	0x1D
+#define INTEL_FAM6_MODEL_NEHALEM		0x1E
+#define INTEL_FAM6_MODEL_NEHALEM_EP		0x1A
+#define INTEL_FAM6_MODEL_NEHALEM_EX		0x2E
+#define INTEL_FAM6_MODEL_WESTMERE		0x25
+#define INTEL_FAM6_MODEL_WESTMERE_EP		0x2C
+#define INTEL_FAM6_MODEL_WESTMERE_EX		0x2F
+#define INTEL_FAM6_MODEL_SANDYBRIDGE		0x2A
+#define INTEL_FAM6_MODEL_SANDYBRIDGE_X		0x2D
+#define INTEL_FAM6_MODEL_IVYBRIDGE		0x3A
+#define INTEL_FAM6_MODEL_IVYBRIDGE_X		0x3E
+#define INTEL_FAM6_MODEL_HASWELL_CORE		0x3C
+#define INTEL_FAM6_MODEL_HASWELL_X		0x3F
+#define INTEL_FAM6_MODEL_HASWELL_ULT		0x45
+#define INTEL_FAM6_MODEL_HASWELL_GT3E		0x46
+#define INTEL_FAM6_MODEL_BROADWELL_CORE_M	0x3D
+#define INTEL_FAM6_MODEL_BROADWELL_XEON_D	0x56
+#define INTEL_FAM6_MODEL_BROADWELL_GT3E		0x47
+#define INTEL_FAM6_MODEL_BROADWELL_X		0x4F
+#define INTEL_FAM6_MODEL_SKYLAKE_MOBILE		0x4E
+#define INTEL_FAM6_MODEL_SKYLAKE_DESKTOP	0x5E
+#define INTEL_FAM6_MODEL_SKYLAKE_X		0x55
+#define INTEL_FAM6_MODEL_KABYLAKE_MOBILE	0x8E
+#define INTEL_FAM6_MODEL_KABYLAKE_DESKTOP	0x9E
+
+/* "Small Core" Processors (Atom) */
+
+#define INTEL_FAM6_MODEL_ATOM_PINEVIEW		0x1C
+#define INTEL_FAM6_MODEL_ATOM_LINCROFT		0x26
+#define INTEL_FAM6_MODEL_ATOM_PENWELL		0x27
+#define INTEL_FAM6_MODEL_ATOM_CLOVERVIEW	0x35
+#define INTEL_FAM6_MODEL_ATOM_CEDARVIEW		0x36
+#define INTEL_FAM6_MODEL_ATOM_SILVERMONT1	0x37
+#define INTEL_FAM6_MODEL_ATOM_SILVERMONT2	0x4D /* Avaton/Rangely */
+#define INTEL_FAM6_MODEL_ATOM_AIRMONT		0x4C
+#define INTEL_FAM6_MODEL_ATOM_GOLDMONT		0x5C
+#define INTEL_FAM6_MODEL_ATOM_DENVERTON		0x5F /* Goldmont Microserver */
+
+/* Xeon Phi */
+
+#define INTEL_FAM6_MODEL_XEON_PHI_KNL		0x57 /* Knights Landing */
+
+#endif /* _ASM_X86_INTEL_FAMILY_H */
_

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