linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH v14 0/17] Add Analogix Core Display Port Driver
@ 2016-02-15 11:08 Yakir Yang
  2016-02-15 11:09 ` [PATCH v14 01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang
                   ` (19 more replies)
  0 siblings, 20 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:08 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel


Hi all,

  The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
controller, so I decide to name dp core driver with "analogix" which I
find in rk3288 eDP TRM

But there are still three light registers setting different between
exynos and rk3288.
1. RK3288 have five special pll registers which not indicate in exynos
   dp controller.
2. The address of DP_PHY_PD(dp phy power manager register) are different
   between rk3288 and exynos.
3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
   register).

Due to Mark Yao have introduced the ATOMIC support to Rockchip drm, so it's
okay to use the ATOMIC helpers functions in connector_funcs. No need to splict
the connector init to platform driver anymore, and this is the biggest change
since version 11.

This v14 didn't have lots of new changes which seems not the correct time to
upgrade the version number, but I have changed ordering of patches (adding 2
more, and removing 2 out). Especially to prevent confusing people, so I updated
the whole series.

Thanks,
- Yakir


Changes in v14:
- Rebase the new changes in imx-dp driver
- Split up this patch into 3 parts, make this easy to review (Heiko)
- Remove the Rockchip DP PHY to an separate thread (Heiko)
    https://patchwork.kernel.org/patch/8312701/

Changes in v13:
- Use .enable instead of preprare/commit in encoder_helper_funcs (Heiko)
- Fix the missing parameters with drm_encoder_init() helper function. (Heiko)

Changes in v12:
- Move the connector init to analogix_dp driver, and using ATOMIC helper (Heiko)
- Add the ack from Jingoo
- Remove the enum link_rate_type struct, using the marcos in drm_dp_helper.h (Jingoo)

Changes in v11:
- Uses tabs to fix the indentation issues in analogix_dp_core.h (Heiko)
- Rename the "analogix,need-force-hpd" to common 'force-hpd' (Rob)
- Add the ack from Rob Herring
- Revert parts of Gustavo Padovan's changes in commit:
	drm/exynos: do not start enabling DP at bind() phase
  Add dp phy poweron function in bind time.
- Move the panel prepare from get_modes time to bind time, and move
  the panel unprepare from bridge->disable to unbind time. (Heiko)

Changes in v10:
- Add the ack from Rob Herring
- Correct the ROCKCHIP_ANALOGIX_DP indentation in Kconfig to tabs here (Heiko)
- Add the ack from Rob Herring
- Remove the surplus "plat_data" check. (Heiko)
-       switch (dp->plat_data && dp->plat_data->dev_type) {
+       switch (dp->plat_data->dev_type) {

Changes in v9:
- Document more details for 'ports' property.

Changes in v8:
- Correct the right document path of display-timing.txt (Heiko)
- Correct the misspell of 'from' to 'frm'. (Heiko)
- Modify the commit subject name. (Heiko)

Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
  compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
  to avoid -EOVERFLOW error (Krzysztof)

Changes in v6:
- Fix the Kconfig recursive dependency (Javier)
- Fix Peach Pit hpd property name error:
-       hpd-gpio = <&gpx2 6 0>;
+       hpd-gpios = <&gpx2 6 0>;

Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
  the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
  attch function. Cause once platform failed at attach, core driver should
  still failed, so no need to init connector before platform attached (Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
  patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)
- Resequence this patch after analogix_dp driver have been split
  from exynos_dp code, and rephrase reasonable commit message, and
  remove some controversial style (Krzysztof)
    -		analogix_dp_write_byte_to_dpcd(
    - 				dp, DP_TEST_RESPONSE,
    +		analogix_dp_write_byte_to_dpcd(dp,
    +				DP_TEST_RESPONSE,
				DP_TEST_EDID_CHECKSUM_WRITE);
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).
- Correct the misspell in commit message. (Krzysztof)
- Remove the empty line at the end of document, and correct the endpoint
  numbers in the example DT node, and remove the regulator iomux setting
  in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
  support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)

Changes in v4:
- Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
- Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
- Create a separate folder for analogix code in bridge/ (Archit)
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
- Provide backword compatibility with samsung. (Krzysztof)
- Split all DTS changes, and provide backward compatibility. Mark old
  properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"
- Separate all DTS changes to a separate patch. (Krzysztof)
- Remove some deprecated DT properties in rockchip dp document.
- Seprate the link-rate and lane-count limit out with the device_type
  flag. (Thierry)
- Take Jingoo suggest, add commit messages.
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Move exynos's video_timing code to analogix_dp-exynos platform driver,
  add get_modes method to struct analogix_dp_plat_data. (Thierry)
- Rename some "samsung*" dts propery to "analogix*". (Heiko)
- The link_rate and lane_count shouldn't config to the DT property value
  directly, but we can take those as hardware limite. For example, RK3288
  only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
  like "link-rate = 0x0a" "lane-count = 4". (Thierry)
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
  devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
  and leave "sclk_edp" to analogix dp core driver which name to "dp",
  and leave "pclk_edp" to rockchip dp platform driver which name to
  "pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
  node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.
- move dp hpd detect to connector detect function.
- Add edid modes parse support

Changes in v2:
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
  uncommon style like bellow: (Joe Preches)
    -  retval = exynos_dp_read_bytes_from_i2c(...
  				  ...);
    +  retval =
    +  exynos_dp_read_bytes_from_i2c(......);
- Get panel node with remote-endpoint method, and create devicetree binding
  for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.
- Fix compile failed dut to phy_pd_addr variable misspell error

Heiko Stuebner (2):
  drm/exynos: dp: rename implementation specific driver part
  drm: bridge: analogix/dp: rename register constants

Yakir Yang (15):
  drm: bridge: analogix/dp: split exynos dp driver to bridge directory
  drm: bridge: analogix/dp: fix some obvious code style
  drm: bridge: analogix/dp: remove duplicate configuration of link rate
    and link count
  drm: bridge: analogix/dp: dynamic parse sync_pol & interlace &
    dynamic_range
  dt-bindings: add document for analogix display port driver
  ARM: dts: exynos/dp: remove some properties that deprecated by
    analogix_dp driver
  drm: rockchip: dp: add rockchip platform dp driver
  dt-bindings: add document for rockchip variant of analogix_dp
  drm: bridge: analogix/dp: add some rk3288 special registers setting
  drm: bridge: analogix/dp: add max link rate and lane count limit for
    RK3288
  drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  drm: bridge: analogix/dp: move hpd detect to connector detect function
  drm: bridge: analogix/dp: add edid modes parse in get_modes method
  drm: bridge: analogix/dp: add panel prepare/unprepare in
    suspend/resume time
  drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable
    time

 .../bindings/display/bridge/analogix_dp.txt        |   52 +
 .../bindings/display/exynos/exynos_dp.txt          |   93 +-
 .../display/rockchip/analogix_dp-rockchip.txt      |   92 ++
 arch/arm/boot/dts/exynos5250-arndale.dts           |    2 -
 arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 -
 arch/arm/boot/dts/exynos5250-snow-common.dtsi      |    4 +-
 arch/arm/boot/dts/exynos5250-spring.dts            |    4 +-
 arch/arm/boot/dts/exynos5420-peach-pit.dts         |    4 +-
 arch/arm/boot/dts/exynos5420-smdk5420.dts          |    2 -
 arch/arm/boot/dts/exynos5800-peach-pi.dts          |    2 -
 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    3 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1430 ++++++++++++++++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  281 ++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1320 +++++++++++++++++
 .../analogix/analogix_dp_reg.h}                    |  270 ++--
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp.c                 |  324 +++++
 drivers/gpu/drm/exynos/exynos_dp_core.c            | 1510 --------------------
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 ----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 ----------------
 drivers/gpu/drm/rockchip/Kconfig                   |    9 +
 drivers/gpu/drm/rockchip/Makefile                  |    1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    |  384 +++++
 include/drm/bridge/analogix_dp.h                   |   41 +
 28 files changed, 4115 insertions(+), 3269 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
 create mode 100644 Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (62%)
 create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
 create mode 100644 include/drm/bridge/analogix_dp.h

-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
@ 2016-02-15 11:09 ` Yakir Yang
  2016-03-17 21:47   ` [PATCH v14.1 " Heiko Stübner
  2016-03-30 20:32   ` [v14, " Guenter Roeck
  2016-02-15 11:09 ` [PATCH v14 02/17] drm/exynos: dp: rename implementation specific driver part Yakir Yang
                   ` (18 subsequent siblings)
  19 siblings, 2 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:09 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.

Beside the new analogix_dp driver would export six hooks.
"analogix_dp_bind()" and "analogix_dp_unbind()"
"analogix_dp_suspned()" and "analogix_dp_resume()"
"analogix_dp_detect()" and "analogix_dp_get_modes()"

The bind/unbind symbols is used for analogix platform driver to connect
with analogix_dp core driver. And the detect/get_modes is used for analogix
platform driver to init the connector.

They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v14:
- Rebase the new changes in imx-dp driver
- Split up this patch into 3 parts, make this easy to review (Heiko)

Changes in v13: None
Changes in v12:
- Move the connector init to analogix_dp driver, and using ATOMIC helper (Heiko)

Changes in v11:
- Uses tabs to fix the indentation issues in analogix_dp_core.h (Heiko)

Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6:
- Fix the Kconfig recursive dependency (Javier)

Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
  the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
  attch function. Cause once platform failed at attach, core driver should
  still failed, so no need to init connector before platform attached (Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
  patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)

Changes in v4:
- Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
- Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
- Create a separate folder for analogix code in bridge/ (Archit)

Changes in v3:
- Move exynos's video_timing code to analogix_dp-exynos platform driver,
  add get_modes method to struct analogix_dp_plat_data. (Thierry)
- Rename some "samsung*" dts propery to "analogix*". (Heiko)

Changes in v2:
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell

 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    3 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1351 +++++++++++++++++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  277 ++++
 .../analogix/analogix_dp_reg.c}                    |  160 +--
 .../analogix/analogix_dp_reg.h}                    |    8 +-
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp_core.c            | 1352 ++------------------
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 ----
 include/drm/bridge/analogix_dp.h                   |   40 +
 13 files changed, 1845 insertions(+), 1637 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.c => bridge/analogix/analogix_dp_reg.c} (84%)
 rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (98%)
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 create mode 100644 include/drm/bridge/analogix_dp.h

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 27e2022..efd94e0 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -40,4 +40,6 @@ config DRM_PARADE_PS8622
 	---help---
 	  Parade eDP-LVDS bridge chip driver.
 
+source "drivers/gpu/drm/bridge/analogix/Kconfig"
+
 endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index f13c33d..ff821f4 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
new file mode 100644
index 0000000..80f286f
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -0,0 +1,3 @@
+config DRM_ANALOGIX_DP
+	tristate
+	depends on DRM
diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
new file mode 100644
index 0000000..9107b86
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
new file mode 100644
index 0000000..392c296
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -0,0 +1,1351 @@
+/*
+* Analogix DP (Display Port) core interface driver.
+*
+* Copyright (C) 2012 Samsung Electronics Co., Ltd.
+* Author: Jingoo Han <jg1.han@samsung.com>
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2 of the License, or (at your
+* option) any later version.
+*/
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/gpio.h>
+#include <linux/component.h>
+#include <linux/phy/phy.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "analogix_dp_core.h"
+
+#define to_dp(nm)	container_of(nm, struct analogix_dp_device, nm)
+
+struct bridge_init {
+	struct i2c_client *client;
+	struct device_node *node;
+};
+
+static void analogix_dp_init_dp(struct analogix_dp_device *dp)
+{
+	analogix_dp_reset(dp);
+
+	analogix_dp_swreset(dp);
+
+	analogix_dp_init_analog_param(dp);
+	analogix_dp_init_interrupt(dp);
+
+	/* SW defined function Normal operation */
+	analogix_dp_enable_sw_function(dp);
+
+	analogix_dp_config_interrupt(dp);
+	analogix_dp_init_analog_func(dp);
+
+	analogix_dp_init_hpd(dp);
+	analogix_dp_init_aux(dp);
+}
+
+static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
+{
+	int timeout_loop = 0;
+
+	while (analogix_dp_get_plug_in_status(dp) != 0) {
+		timeout_loop++;
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "failed to get hpd plug status\n");
+			return -ETIMEDOUT;
+		}
+		usleep_range(10, 11);
+	}
+
+	return 0;
+}
+
+static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
+{
+	int i;
+	unsigned char sum = 0;
+
+	for (i = 0; i < EDID_BLOCK_LENGTH; i++)
+		sum = sum + edid_data[i];
+
+	return sum;
+}
+
+static int analogix_dp_read_edid(struct analogix_dp_device *dp)
+{
+	unsigned char edid[EDID_BLOCK_LENGTH * 2];
+	unsigned int extend_block = 0;
+	unsigned char sum;
+	unsigned char test_vector;
+	int retval;
+
+	/*
+	 * EDID device address is 0x50.
+	 * However, if necessary, you must have set upper address
+	 * into E-EDID in I2C device, 0x30.
+	 */
+
+	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
+	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+				EDID_EXTENSION_FLAG,
+				&extend_block);
+	if (retval)
+		return retval;
+
+	if (extend_block > 0) {
+		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
+
+		/* Read EDID data */
+		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+						EDID_HEADER_PATTERN,
+						EDID_BLOCK_LENGTH,
+						&edid[EDID_HEADER_PATTERN]);
+		if (retval != 0) {
+			dev_err(dp->dev, "EDID Read failed!\n");
+			return -EIO;
+		}
+		sum = analogix_dp_calc_edid_check_sum(edid);
+		if (sum != 0) {
+			dev_err(dp->dev, "EDID bad checksum!\n");
+			return -EIO;
+		}
+
+		/* Read additional EDID data */
+		retval = analogix_dp_read_bytes_from_i2c(dp,
+				I2C_EDID_DEVICE_ADDR,
+				EDID_BLOCK_LENGTH,
+				EDID_BLOCK_LENGTH,
+				&edid[EDID_BLOCK_LENGTH]);
+		if (retval != 0) {
+			dev_err(dp->dev, "EDID Read failed!\n");
+			return -EIO;
+		}
+		sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
+		if (sum != 0) {
+			dev_err(dp->dev, "EDID bad checksum!\n");
+			return -EIO;
+		}
+
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+					&test_vector);
+		if (test_vector & DP_TEST_LINK_EDID_READ) {
+			analogix_dp_write_byte_to_dpcd(dp,
+				DP_TEST_EDID_CHECKSUM,
+				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
+			analogix_dp_write_byte_to_dpcd(dp,
+				DP_TEST_RESPONSE,
+				DP_TEST_EDID_CHECKSUM_WRITE);
+		}
+	} else {
+		dev_info(dp->dev, "EDID data does not include any extensions.\n");
+
+		/* Read EDID data */
+		retval = analogix_dp_read_bytes_from_i2c(dp,
+				I2C_EDID_DEVICE_ADDR,
+				EDID_HEADER_PATTERN,
+				EDID_BLOCK_LENGTH,
+				&edid[EDID_HEADER_PATTERN]);
+		if (retval != 0) {
+			dev_err(dp->dev, "EDID Read failed!\n");
+			return -EIO;
+		}
+		sum = analogix_dp_calc_edid_check_sum(edid);
+		if (sum != 0) {
+			dev_err(dp->dev, "EDID bad checksum!\n");
+			return -EIO;
+		}
+
+		analogix_dp_read_byte_from_dpcd(dp,
+			DP_TEST_REQUEST,
+			&test_vector);
+		if (test_vector & DP_TEST_LINK_EDID_READ) {
+			analogix_dp_write_byte_to_dpcd(dp,
+				DP_TEST_EDID_CHECKSUM,
+				edid[EDID_CHECKSUM]);
+			analogix_dp_write_byte_to_dpcd(dp,
+				DP_TEST_RESPONSE,
+				DP_TEST_EDID_CHECKSUM_WRITE);
+		}
+	}
+
+	dev_dbg(dp->dev, "EDID Read success!\n");
+	return 0;
+}
+
+static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
+{
+	u8 buf[12];
+	int i;
+	int retval;
+
+	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
+				12, buf);
+	if (retval)
+		return retval;
+
+	/* Read EDID */
+	for (i = 0; i < 3; i++) {
+		retval = analogix_dp_read_edid(dp);
+		if (!retval)
+			break;
+	}
+
+	return retval;
+}
+
+static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
+						bool enable)
+{
+	u8 data;
+
+	analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
+
+	if (enable)
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+			DP_LANE_COUNT_ENHANCED_FRAME_EN |
+			DPCD_LANE_COUNT_SET(data));
+	else
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+			DPCD_LANE_COUNT_SET(data));
+}
+
+static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
+{
+	u8 data;
+	int retval;
+
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	retval = DPCD_ENHANCED_FRAME_CAP(data);
+
+	return retval;
+}
+
+static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
+{
+	u8 data;
+
+	data = analogix_dp_is_enhanced_mode_available(dp);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, data);
+	analogix_dp_enable_enhanced_mode(dp, data);
+}
+
+static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
+{
+	analogix_dp_set_training_pattern(dp, DP_NONE);
+
+	analogix_dp_write_byte_to_dpcd(dp,
+		DP_TRAINING_PATTERN_SET,
+		DP_TRAINING_PATTERN_DISABLE);
+}
+
+static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
+					int pre_emphasis, int lane)
+{
+	switch (lane) {
+	case 0:
+		analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
+		break;
+	case 1:
+		analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
+		break;
+
+	case 2:
+		analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
+		break;
+
+	case 3:
+		analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
+		break;
+	}
+}
+
+static int analogix_dp_link_start(struct analogix_dp_device *dp)
+{
+	u8 buf[4];
+	int lane, lane_count, pll_tries, retval;
+
+	lane_count = dp->link_train.lane_count;
+
+	dp->link_train.lt_state = CLOCK_RECOVERY;
+	dp->link_train.eq_loop = 0;
+
+	for (lane = 0; lane < lane_count; lane++)
+		dp->link_train.cr_loop[lane] = 0;
+
+	/* Set link rate and count as you want to establish*/
+	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
+	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
+
+	/* Setup RX configuration */
+	buf[0] = dp->link_train.link_rate;
+	buf[1] = dp->link_train.lane_count;
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
+				2, buf);
+	if (retval)
+		return retval;
+
+	/* Set TX pre-emphasis to minimum */
+	for (lane = 0; lane < lane_count; lane++)
+		analogix_dp_set_lane_lane_pre_emphasis(dp,
+			PRE_EMPHASIS_LEVEL_0, lane);
+
+	/* Wait for PLL lock */
+	pll_tries = 0;
+	while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
+			dev_err(dp->dev, "Wait for PLL lock timed out\n");
+			return -ETIMEDOUT;
+		}
+
+		pll_tries++;
+		usleep_range(90, 120);
+	}
+
+	/* Set training pattern 1 */
+	analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
+
+	/* Set RX training pattern */
+	retval = analogix_dp_write_byte_to_dpcd(dp,
+			DP_TRAINING_PATTERN_SET,
+			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
+	if (retval)
+		return retval;
+
+	for (lane = 0; lane < lane_count; lane++)
+		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
+			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
+
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+			lane_count, buf);
+
+	return retval;
+}
+
+static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
+{
+	int shift = (lane & 1) * 4;
+	u8 link_value = link_status[lane>>1];
+
+	return (link_value >> shift) & 0xf;
+}
+
+static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
+{
+	int lane;
+	u8 lane_status;
+
+	for (lane = 0; lane < lane_count; lane++) {
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
+		if ((lane_status & DP_LANE_CR_DONE) == 0)
+			return -EINVAL;
+	}
+	return 0;
+}
+
+static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
+				int lane_count)
+{
+	int lane;
+	u8 lane_status;
+
+	if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
+		return -EINVAL;
+
+	for (lane = 0; lane < lane_count; lane++) {
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
+		lane_status &= DP_CHANNEL_EQ_BITS;
+		if (lane_status != DP_CHANNEL_EQ_BITS)
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
+static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
+							int lane)
+{
+	int shift = (lane & 1) * 4;
+	u8 link_value = adjust_request[lane>>1];
+
+	return (link_value >> shift) & 0x3;
+}
+
+static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
+					u8 adjust_request[2],
+					int lane)
+{
+	int shift = (lane & 1) * 4;
+	u8 link_value = adjust_request[lane>>1];
+
+	return ((link_value >> shift) & 0xc) >> 2;
+}
+
+static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
+					u8 training_lane_set, int lane)
+{
+	switch (lane) {
+	case 0:
+		analogix_dp_set_lane0_link_training(dp, training_lane_set);
+		break;
+	case 1:
+		analogix_dp_set_lane1_link_training(dp, training_lane_set);
+		break;
+
+	case 2:
+		analogix_dp_set_lane2_link_training(dp, training_lane_set);
+		break;
+
+	case 3:
+		analogix_dp_set_lane3_link_training(dp, training_lane_set);
+		break;
+	}
+}
+
+static unsigned int analogix_dp_get_lane_link_training(
+				struct analogix_dp_device *dp,
+				int lane)
+{
+	u32 reg;
+
+	switch (lane) {
+	case 0:
+		reg = analogix_dp_get_lane0_link_training(dp);
+		break;
+	case 1:
+		reg = analogix_dp_get_lane1_link_training(dp);
+		break;
+	case 2:
+		reg = analogix_dp_get_lane2_link_training(dp);
+		break;
+	case 3:
+		reg = analogix_dp_get_lane3_link_training(dp);
+		break;
+	default:
+		WARN_ON(1);
+		return 0;
+	}
+
+	return reg;
+}
+
+static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
+{
+	analogix_dp_training_pattern_dis(dp);
+	analogix_dp_set_enhanced_mode(dp);
+
+	dp->link_train.lt_state = FAILED;
+}
+
+static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
+					u8 adjust_request[2])
+{
+	int lane, lane_count;
+	u8 voltage_swing, pre_emphasis, training_lane;
+
+	lane_count = dp->link_train.lane_count;
+	for (lane = 0; lane < lane_count; lane++) {
+		voltage_swing = analogix_dp_get_adjust_request_voltage(
+						adjust_request, lane);
+		pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
+						adjust_request, lane);
+		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
+				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
+
+		if (voltage_swing == VOLTAGE_LEVEL_3)
+			training_lane |= DP_TRAIN_MAX_SWING_REACHED;
+		if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
+			training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+		dp->link_train.training_lane[lane] = training_lane;
+	}
+}
+
+static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
+{
+	int lane, lane_count, retval;
+	u8 voltage_swing, pre_emphasis, training_lane;
+	u8 link_status[2], adjust_request[2];
+
+	usleep_range(100, 101);
+
+	lane_count = dp->link_train.lane_count;
+
+	retval =  analogix_dp_read_bytes_from_dpcd(dp,
+			DP_LANE0_1_STATUS, 2, link_status);
+	if (retval)
+		return retval;
+
+	retval =  analogix_dp_read_bytes_from_dpcd(dp,
+			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
+	if (retval)
+		return retval;
+
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
+		/* set training pattern 2 for EQ */
+		analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
+
+		retval = analogix_dp_write_byte_to_dpcd(dp,
+				DP_TRAINING_PATTERN_SET,
+				DP_LINK_SCRAMBLING_DISABLE |
+				DP_TRAINING_PATTERN_2);
+		if (retval)
+			return retval;
+
+		dev_info(dp->dev, "Link Training Clock Recovery success\n");
+		dp->link_train.lt_state = EQUALIZER_TRAINING;
+	} else {
+		for (lane = 0; lane < lane_count; lane++) {
+			training_lane = analogix_dp_get_lane_link_training(
+							dp, lane);
+			voltage_swing = analogix_dp_get_adjust_request_voltage(
+							adjust_request, lane);
+			pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
+							adjust_request, lane);
+
+			if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
+					voltage_swing &&
+			    DPCD_PRE_EMPHASIS_GET(training_lane) ==
+					pre_emphasis)
+				dp->link_train.cr_loop[lane]++;
+
+			if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
+			    voltage_swing == VOLTAGE_LEVEL_3 ||
+			    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
+				dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
+					dp->link_train.cr_loop[lane],
+					voltage_swing, pre_emphasis);
+				analogix_dp_reduce_link_rate(dp);
+				return -EIO;
+			}
+		}
+	}
+
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
+
+	for (lane = 0; lane < lane_count; lane++)
+		analogix_dp_set_lane_link_training(dp,
+			dp->link_train.training_lane[lane], lane);
+
+	retval = analogix_dp_write_bytes_to_dpcd(dp,
+			DP_TRAINING_LANE0_SET, lane_count,
+			dp->link_train.training_lane);
+	if (retval)
+		return retval;
+
+	return retval;
+}
+
+static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
+{
+	int lane, lane_count, retval;
+	u32 reg;
+	u8 link_align, link_status[2], adjust_request[2];
+
+	usleep_range(400, 401);
+
+	lane_count = dp->link_train.lane_count;
+
+	retval = analogix_dp_read_bytes_from_dpcd(dp,
+			DP_LANE0_1_STATUS, 2, link_status);
+	if (retval)
+		return retval;
+
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
+		analogix_dp_reduce_link_rate(dp);
+		return -EIO;
+	}
+
+	retval = analogix_dp_read_bytes_from_dpcd(dp,
+			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
+	if (retval)
+		return retval;
+
+	retval = analogix_dp_read_byte_from_dpcd(dp,
+			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
+	if (retval)
+		return retval;
+
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
+
+	if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
+		/* traing pattern Set to Normal */
+		analogix_dp_training_pattern_dis(dp);
+
+		dev_info(dp->dev, "Link Training success!\n");
+
+		analogix_dp_get_link_bandwidth(dp, &reg);
+		dp->link_train.link_rate = reg;
+		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
+			dp->link_train.link_rate);
+
+		analogix_dp_get_lane_count(dp, &reg);
+		dp->link_train.lane_count = reg;
+		dev_dbg(dp->dev, "final lane count = %.2x\n",
+			dp->link_train.lane_count);
+
+		/* set enhanced mode if available */
+		analogix_dp_set_enhanced_mode(dp);
+		dp->link_train.lt_state = FINISHED;
+
+		return 0;
+	}
+
+	/* not all locked */
+	dp->link_train.eq_loop++;
+
+	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
+		dev_err(dp->dev, "EQ Max loop\n");
+		analogix_dp_reduce_link_rate(dp);
+		return -EIO;
+	}
+
+	for (lane = 0; lane < lane_count; lane++)
+		analogix_dp_set_lane_link_training(dp,
+			dp->link_train.training_lane[lane], lane);
+
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+			lane_count, dp->link_train.training_lane);
+
+	return retval;
+}
+
+static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
+					u8 *bandwidth)
+{
+	u8 data;
+
+	/*
+	 * For DP rev.1.1, Maximum link rate of Main Link lanes
+	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+	 */
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
+	*bandwidth = data;
+}
+
+static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
+					u8 *lane_count)
+{
+	u8 data;
+
+	/*
+	 * For DP rev.1.1, Maximum number of Main Link lanes
+	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
+	 */
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	*lane_count = DPCD_MAX_LANE_COUNT(data);
+}
+
+static void analogix_dp_init_training(struct analogix_dp_device *dp,
+			enum link_lane_count_type max_lane,
+			enum link_rate_type max_rate)
+{
+	/*
+	 * MACRO_RST must be applied after the PLL_LOCK to avoid
+	 * the DP inter pair skew issue for at least 10 us
+	 */
+	analogix_dp_reset_macro(dp);
+
+	/* Initialize by reading RX's DPCD */
+	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
+	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
+
+	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
+	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
+			dp->link_train.link_rate);
+		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
+	}
+
+	if (dp->link_train.lane_count == 0) {
+		dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
+			dp->link_train.lane_count);
+		dp->link_train.lane_count = (u8)LANE_COUNT1;
+	}
+
+	/* Setup TX lane count & rate */
+	if (dp->link_train.lane_count > max_lane)
+		dp->link_train.lane_count = max_lane;
+	if (dp->link_train.link_rate > max_rate)
+		dp->link_train.link_rate = max_rate;
+
+	/* All DP analog module power up */
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
+}
+
+static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
+{
+	int retval = 0, training_finished = 0;
+
+	dp->link_train.lt_state = START;
+
+	/* Process here */
+	while (!retval && !training_finished) {
+		switch (dp->link_train.lt_state) {
+		case START:
+			retval = analogix_dp_link_start(dp);
+			if (retval)
+				dev_err(dp->dev, "LT link start failed!\n");
+			break;
+		case CLOCK_RECOVERY:
+			retval = analogix_dp_process_clock_recovery(dp);
+			if (retval)
+				dev_err(dp->dev, "LT CR failed!\n");
+			break;
+		case EQUALIZER_TRAINING:
+			retval = analogix_dp_process_equalizer_training(dp);
+			if (retval)
+				dev_err(dp->dev, "LT EQ failed!\n");
+			break;
+		case FINISHED:
+			training_finished = 1;
+			break;
+		case FAILED:
+			return -EREMOTEIO;
+		}
+	}
+	if (retval)
+		dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
+
+	return retval;
+}
+
+static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
+				u32 count,
+				u32 bwtype)
+{
+	int i;
+	int retval;
+
+	for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
+		analogix_dp_init_training(dp, count, bwtype);
+		retval = analogix_dp_sw_link_training(dp);
+		if (retval == 0)
+			break;
+
+		usleep_range(100, 110);
+	}
+
+	return retval;
+}
+
+static int analogix_dp_config_video(struct analogix_dp_device *dp)
+{
+	int retval = 0;
+	int timeout_loop = 0;
+	int done_count = 0;
+
+	analogix_dp_config_video_slave_mode(dp);
+
+	analogix_dp_set_video_color_format(dp);
+
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		dev_err(dp->dev, "PLL is not locked yet.\n");
+		return -EINVAL;
+	}
+
+	for (;;) {
+		timeout_loop++;
+		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
+			break;
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "Timeout of video streamclk ok\n");
+			return -ETIMEDOUT;
+		}
+
+		usleep_range(1, 2);
+	}
+
+	/* Set to use the register calculated M/N video */
+	analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
+
+	/* For video bist, Video timing must be generated by register */
+	analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
+
+	/* Disable video mute */
+	analogix_dp_enable_video_mute(dp, 0);
+
+	/* Configure video slave mode */
+	analogix_dp_enable_video_master(dp, 0);
+
+	timeout_loop = 0;
+
+	for (;;) {
+		timeout_loop++;
+		if (analogix_dp_is_video_stream_on(dp) == 0) {
+			done_count++;
+			if (done_count > 10)
+				break;
+		} else if (done_count) {
+			done_count = 0;
+		}
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "Timeout of video streamclk ok\n");
+			return -ETIMEDOUT;
+		}
+
+		usleep_range(1000, 1001);
+	}
+
+	if (retval != 0)
+		dev_err(dp->dev, "Video stream is not detected!\n");
+
+	return retval;
+}
+
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
+{
+	u8 data;
+
+	if (enable) {
+		analogix_dp_enable_scrambling(dp);
+
+		analogix_dp_read_byte_from_dpcd(dp,
+			DP_TRAINING_PATTERN_SET,
+			&data);
+		analogix_dp_write_byte_to_dpcd(dp,
+			DP_TRAINING_PATTERN_SET,
+			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
+	} else {
+		analogix_dp_disable_scrambling(dp);
+
+		analogix_dp_read_byte_from_dpcd(dp,
+			DP_TRAINING_PATTERN_SET,
+			&data);
+		analogix_dp_write_byte_to_dpcd(dp,
+			DP_TRAINING_PATTERN_SET,
+			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
+	}
+}
+
+static irqreturn_t analogix_dp_irq_handler(int irq, void *arg)
+{
+	struct analogix_dp_device *dp = arg;
+
+	enum dp_irq_type irq_type;
+
+	irq_type = analogix_dp_get_irq_type(dp);
+	switch (irq_type) {
+	case DP_IRQ_TYPE_HP_CABLE_IN:
+		dev_dbg(dp->dev, "Received irq - cable in\n");
+		schedule_work(&dp->hotplug_work);
+		analogix_dp_clear_hotplug_interrupts(dp);
+		break;
+	case DP_IRQ_TYPE_HP_CABLE_OUT:
+		dev_dbg(dp->dev, "Received irq - cable out\n");
+		analogix_dp_clear_hotplug_interrupts(dp);
+		break;
+	case DP_IRQ_TYPE_HP_CHANGE:
+		/*
+		 * We get these change notifications once in a while, but there
+		 * is nothing we can do with them. Just ignore it for now and
+		 * only handle cable changes.
+		 */
+		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
+		analogix_dp_clear_hotplug_interrupts(dp);
+		break;
+	default:
+		dev_err(dp->dev, "Received irq - unknown type!\n");
+		break;
+	}
+	return IRQ_HANDLED;
+}
+
+static void analogix_dp_hotplug(struct work_struct *work)
+{
+	struct analogix_dp_device *dp;
+
+	dp = container_of(work, struct analogix_dp_device, hotplug_work);
+
+	if (dp->drm_dev)
+		drm_helper_hpd_irq_event(dp->drm_dev);
+}
+
+static void analogix_dp_commit(struct analogix_dp_device *dp)
+{
+	int ret;
+
+	/* Keep the panel disabled while we configure video */
+	if (dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel))
+			DRM_ERROR("failed to disable the panel\n");
+	}
+
+	ret = analogix_dp_detect_hpd(dp);
+	if (ret) {
+		/* Cable has been disconnected, we're done */
+		return;
+	}
+
+	ret = analogix_dp_handle_edid(dp);
+	if (ret) {
+		dev_err(dp->dev, "unable to handle edid\n");
+		return;
+	}
+
+	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
+					dp->video_info->link_rate);
+	if (ret) {
+		dev_err(dp->dev, "unable to do link train\n");
+		return;
+	}
+
+	analogix_dp_enable_scramble(dp, 1);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
+	analogix_dp_enable_enhanced_mode(dp, 1);
+
+	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
+
+	analogix_dp_init_video(dp);
+	ret = analogix_dp_config_video(dp);
+	if (ret)
+		dev_err(dp->dev, "unable to config video\n");
+
+	/* Safe to enable the panel now */
+	if (dp->plat_data->panel) {
+		if (drm_panel_enable(dp->plat_data->panel))
+			DRM_ERROR("failed to enable the panel\n");
+	}
+
+	/* Enable video */
+	analogix_dp_start_video(dp);
+}
+
+int analogix_dp_get_modes(struct drm_connector *connector)
+{
+	struct analogix_dp_device *dp = to_dp(connector);
+	int num_modes = 0;
+
+	if (dp->plat_data->panel)
+		num_modes += drm_panel_get_modes(dp->plat_data->panel);
+
+	if (dp->plat_data->get_modes)
+		num_modes += dp->plat_data->get_modes(dp->plat_data);
+
+	return num_modes;
+}
+
+static struct drm_encoder *
+analogix_dp_best_encoder(struct drm_connector *connector)
+{
+	struct analogix_dp_device *dp = to_dp(connector);
+
+	return dp->encoder;
+}
+
+static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
+	.get_modes = analogix_dp_get_modes,
+	.best_encoder = analogix_dp_best_encoder,
+};
+
+enum drm_connector_status
+analogix_dp_detect(struct drm_connector *connector, bool force)
+{
+	return connector_status_connected;
+}
+
+static void analogix_dp_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static const struct drm_connector_funcs analogix_dp_connector_funcs = {
+	.dpms = drm_atomic_helper_connector_dpms,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.detect = analogix_dp_detect,
+	.destroy = analogix_dp_connector_destroy,
+	.reset = drm_atomic_helper_connector_reset,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = dp->encoder;
+	struct drm_connector *connector = &dp->connector;
+	int ret;
+
+	if (!bridge->encoder) {
+		DRM_ERROR("Parent encoder object not found");
+		return -ENODEV;
+	}
+
+	connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+	ret = drm_connector_init(dp->drm_dev, connector,
+				 &analogix_dp_connector_funcs,
+				 DRM_MODE_CONNECTOR_eDP);
+	if (ret) {
+		DRM_ERROR("Failed to initialize connector with drm\n");
+		return ret;
+	}
+
+	drm_connector_helper_add(connector,
+				 &analogix_dp_connector_helper_funcs);
+	drm_mode_connector_attach_encoder(connector, encoder);
+
+	/*
+	 * NOTE: the connector registration is implemented in analogix
+	 * platform driver, that to say connector would be exist after
+	 * plat_data->attch return, that's why we record the connector
+	 * point after plat attached.
+	 */
+	 if (dp->plat_data->attach) {
+		 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
+		 if (ret) {
+			 DRM_ERROR("Failed at platform attch func\n");
+			 return ret;
+		 }
+	}
+
+	if (dp->plat_data->panel) {
+		ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
+		if (ret) {
+			DRM_ERROR("Failed to attach panel\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+
+	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
+		return;
+
+	pm_runtime_get_sync(dp->dev);
+
+	if (dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
+			DRM_ERROR("failed to setup the panel\n");
+			return;
+		}
+	}
+
+	if (dp->plat_data->power_on)
+		dp->plat_data->power_on(dp->plat_data);
+
+	phy_power_on(dp->phy);
+	analogix_dp_init_dp(dp);
+	enable_irq(dp->irq);
+	analogix_dp_commit(dp);
+
+	dp->dpms_mode = DRM_MODE_DPMS_ON;
+}
+
+static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+
+	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
+		return;
+
+	if (dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel)) {
+			DRM_ERROR("failed to disable the panel\n");
+			return;
+		}
+	}
+
+	disable_irq(dp->irq);
+	flush_work(&dp->hotplug_work);
+	phy_power_off(dp->phy);
+
+	if (dp->plat_data->power_off)
+		dp->plat_data->power_off(dp->plat_data);
+
+	if (dp->plat_data->panel) {
+		if (drm_panel_unprepare(dp->plat_data->panel))
+			DRM_ERROR("failed to turnoff the panel\n");
+	}
+
+	pm_runtime_put_sync(dp->dev);
+
+	dp->dpms_mode = DRM_MODE_DPMS_OFF;
+}
+
+static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
+{
+	/* do nothing */
+}
+
+static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
+	.enable = analogix_dp_bridge_enable,
+	.disable = analogix_dp_bridge_disable,
+	.pre_enable = analogix_dp_bridge_nop,
+	.post_disable = analogix_dp_bridge_nop,
+	.attach = analogix_dp_bridge_attach,
+};
+
+static int analogix_dp_create_bridge(struct drm_device *drm_dev,
+				     struct analogix_dp_device *dp)
+{
+	struct drm_bridge *bridge;
+	int ret;
+
+	bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
+	if (!bridge) {
+		DRM_ERROR("failed to allocate for drm bridge\n");
+		return -ENOMEM;
+	}
+
+	dp->bridge = bridge;
+
+	dp->encoder->bridge = bridge;
+	bridge->driver_private = dp;
+	bridge->encoder = dp->encoder;
+	bridge->funcs = &analogix_dp_bridge_funcs;
+
+	ret = drm_bridge_attach(drm_dev, bridge);
+	if (ret) {
+		DRM_ERROR("failed to attach drm bridge\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+{
+	struct device_node *dp_node = dev->of_node;
+	struct video_info *dp_video_config;
+
+	dp_video_config = devm_kzalloc(dev,
+				sizeof(*dp_video_config), GFP_KERNEL);
+	if (!dp_video_config)
+		return ERR_PTR(-ENOMEM);
+
+	dp_video_config->h_sync_polarity =
+		of_property_read_bool(dp_node, "hsync-active-high");
+
+	dp_video_config->v_sync_polarity =
+		of_property_read_bool(dp_node, "vsync-active-high");
+
+	dp_video_config->interlaced =
+		of_property_read_bool(dp_node, "interlaced");
+
+	if (of_property_read_u32(dp_node, "samsung,color-space",
+				&dp_video_config->color_space)) {
+		dev_err(dev, "failed to get color-space\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
+				&dp_video_config->dynamic_range)) {
+		dev_err(dev, "failed to get dynamic-range\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+				&dp_video_config->ycbcr_coeff)) {
+		dev_err(dev, "failed to get ycbcr-coeff\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (of_property_read_u32(dp_node, "samsung,color-depth",
+				&dp_video_config->color_depth)) {
+		dev_err(dev, "failed to get color-depth\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (of_property_read_u32(dp_node, "samsung,link-rate",
+				&dp_video_config->link_rate)) {
+		dev_err(dev, "failed to get link-rate\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (of_property_read_u32(dp_node, "samsung,lane-count",
+				&dp_video_config->lane_count)) {
+		dev_err(dev, "failed to get lane-count\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	return dp_video_config;
+}
+
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct analogix_dp_plat_data *plat_data)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct analogix_dp_device *dp;
+	struct resource *res;
+	unsigned int irq_flags;
+	int ret;
+
+	if (!plat_data) {
+		dev_err(dev, "Invalided input plat_data\n");
+		return -EINVAL;
+	}
+
+	dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, dp);
+
+	dp->dev = &pdev->dev;
+	dp->dpms_mode = DRM_MODE_DPMS_OFF;
+
+	/*
+	 * platform dp driver need containor_of the plat_data to get
+	 * the driver private data, so we need to store the point of
+	 * plat_data, not the context of plat_data.
+	 */
+	dp->plat_data = plat_data;
+
+	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
+	if (IS_ERR(dp->video_info))
+		return PTR_ERR(dp->video_info);
+
+	dp->phy = devm_phy_get(dp->dev, "dp");
+	if (IS_ERR(dp->phy)) {
+		dev_err(dp->dev, "no DP phy configured\n");
+		ret = PTR_ERR(dp->phy);
+		if (ret) {
+			/*
+			 * phy itself is not enabled, so we can move forward
+			 * assigning NULL to phy pointer.
+			 */
+			if (ret == -ENOSYS || ret == -ENODEV)
+				dp->phy = NULL;
+			else
+				return ret;
+		}
+	}
+
+	dp->clock = devm_clk_get(&pdev->dev, "dp");
+	if (IS_ERR(dp->clock)) {
+		dev_err(&pdev->dev, "failed to get clock\n");
+		return PTR_ERR(dp->clock);
+	}
+
+	clk_prepare_enable(dp->clock);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(dp->reg_base))
+		return PTR_ERR(dp->reg_base);
+
+	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
+	if (!gpio_is_valid(dp->hpd_gpio))
+		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
+						 "samsung,hpd-gpio", 0);
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		/*
+		 * Set up the hotplug GPIO from the device tree as an interrupt.
+		 * Simply specifying a different interrupt in the device tree
+		 * doesn't work since we handle hotplug rather differently when
+		 * using a GPIO.  We also need the actual GPIO specifier so
+		 * that we can get the current state of the GPIO.
+		 */
+		ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
+					    "hpd_gpio");
+		if (ret) {
+			dev_err(&pdev->dev, "failed to get hpd gpio\n");
+			return ret;
+		}
+		dp->irq = gpio_to_irq(dp->hpd_gpio);
+		irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
+	} else {
+		dp->hpd_gpio = -ENODEV;
+		dp->irq = platform_get_irq(pdev, 0);
+		irq_flags = 0;
+	}
+
+	if (dp->irq == -ENXIO) {
+		dev_err(&pdev->dev, "failed to get irq\n");
+		return -ENODEV;
+	}
+
+	INIT_WORK(&dp->hotplug_work, analogix_dp_hotplug);
+
+	pm_runtime_enable(dev);
+
+	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
+			irq_flags, "analogix-dp", dp);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to request irq\n");
+		goto err_disable_pm_runtime;
+	}
+	disable_irq(dp->irq);
+
+	dp->drm_dev = drm_dev;
+	dp->encoder = dp->plat_data->encoder;
+
+	ret = analogix_dp_create_bridge(drm_dev, dp);
+	if (ret) {
+		DRM_ERROR("failed to create bridge (%d)\n", ret);
+		drm_encoder_cleanup(dp->encoder);
+		goto err_disable_pm_runtime;
+	}
+
+	return 0;
+
+err_disable_pm_runtime:
+	pm_runtime_disable(dev);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(analogix_dp_bind);
+
+void analogix_dp_unbind(struct device *dev, struct device *master,
+			void *data)
+{
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+
+	analogix_dp_bridge_disable(dp->bridge);
+	pm_runtime_disable(dev);
+}
+EXPORT_SYMBOL_GPL(analogix_dp_unbind);
+
+#ifdef CONFIG_PM
+int analogix_dp_suspend(struct device *dev)
+{
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(dp->clock);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(analogix_dp_suspend);
+
+int analogix_dp_resume(struct device *dev)
+{
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+	int ret;
+
+	ret = clk_prepare_enable(dp->clock);
+	if (ret < 0) {
+		DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(analogix_dp_resume);
+#endif
+
+MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
+MODULE_DESCRIPTION("Analogix DP Core Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
new file mode 100644
index 0000000..0fff745
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -0,0 +1,277 @@
+/*
+ * Header file for Analogix DP (Display Port) core interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _ANALOGIX_DP_CORE_H
+#define _ANALOGIX_DP_CORE_H
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_dp_helper.h>
+
+#define DP_TIMEOUT_LOOP_COUNT 100
+#define MAX_CR_LOOP 5
+#define MAX_EQ_LOOP 5
+
+enum link_rate_type {
+	LINK_RATE_1_62GBPS = 0x06,
+	LINK_RATE_2_70GBPS = 0x0a
+};
+
+enum link_lane_count_type {
+	LANE_COUNT1 = 1,
+	LANE_COUNT2 = 2,
+	LANE_COUNT4 = 4
+};
+
+enum link_training_state {
+	START,
+	CLOCK_RECOVERY,
+	EQUALIZER_TRAINING,
+	FINISHED,
+	FAILED
+};
+
+enum voltage_swing_level {
+	VOLTAGE_LEVEL_0,
+	VOLTAGE_LEVEL_1,
+	VOLTAGE_LEVEL_2,
+	VOLTAGE_LEVEL_3,
+};
+
+enum pre_emphasis_level {
+	PRE_EMPHASIS_LEVEL_0,
+	PRE_EMPHASIS_LEVEL_1,
+	PRE_EMPHASIS_LEVEL_2,
+	PRE_EMPHASIS_LEVEL_3,
+};
+
+enum pattern_set {
+	PRBS7,
+	D10_2,
+	TRAINING_PTN1,
+	TRAINING_PTN2,
+	DP_NONE
+};
+
+enum color_space {
+	COLOR_RGB,
+	COLOR_YCBCR422,
+	COLOR_YCBCR444
+};
+
+enum color_depth {
+	COLOR_6,
+	COLOR_8,
+	COLOR_10,
+	COLOR_12
+};
+
+enum color_coefficient {
+	COLOR_YCBCR601,
+	COLOR_YCBCR709
+};
+
+enum dynamic_range {
+	VESA,
+	CEA
+};
+
+enum pll_status {
+	PLL_UNLOCKED,
+	PLL_LOCKED
+};
+
+enum clock_recovery_m_value_type {
+	CALCULATED_M,
+	REGISTER_M
+};
+
+enum video_timing_recognition_type {
+	VIDEO_TIMING_FROM_CAPTURE,
+	VIDEO_TIMING_FROM_REGISTER
+};
+
+enum analog_power_block {
+	AUX_BLOCK,
+	CH0_BLOCK,
+	CH1_BLOCK,
+	CH2_BLOCK,
+	CH3_BLOCK,
+	ANALOG_TOTAL,
+	POWER_ALL
+};
+
+enum dp_irq_type {
+	DP_IRQ_TYPE_HP_CABLE_IN,
+	DP_IRQ_TYPE_HP_CABLE_OUT,
+	DP_IRQ_TYPE_HP_CHANGE,
+	DP_IRQ_TYPE_UNKNOWN,
+};
+
+struct video_info {
+	char *name;
+
+	bool h_sync_polarity;
+	bool v_sync_polarity;
+	bool interlaced;
+
+	enum color_space color_space;
+	enum dynamic_range dynamic_range;
+	enum color_coefficient ycbcr_coeff;
+	enum color_depth color_depth;
+
+	enum link_rate_type link_rate;
+	enum link_lane_count_type lane_count;
+};
+
+struct link_train {
+	int eq_loop;
+	int cr_loop[4];
+
+	u8 link_rate;
+	u8 lane_count;
+	u8 training_lane[4];
+
+	enum link_training_state lt_state;
+};
+
+struct analogix_dp_device {
+	struct drm_encoder	*encoder;
+	struct device		*dev;
+	struct drm_device	*drm_dev;
+	struct drm_connector	connector;
+	struct drm_bridge	*bridge;
+	struct clk		*clock;
+	unsigned int		irq;
+	void __iomem		*reg_base;
+
+	struct video_info	*video_info;
+	struct link_train	link_train;
+	struct work_struct	hotplug_work;
+	struct phy		*phy;
+	int			dpms_mode;
+	int			hpd_gpio;
+
+	struct analogix_dp_plat_data *plat_data;
+};
+
+/* analogix_dp_reg.c */
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_stop_video(struct analogix_dp_device *dp);
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
+void analogix_dp_reset(struct analogix_dp_device *dp);
+void analogix_dp_swreset(struct analogix_dp_device *dp);
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				       enum analog_power_block block,
+				       bool enable);
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
+void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
+void analogix_dp_reset_aux(struct analogix_dp_device *dp);
+void analogix_dp_init_aux(struct analogix_dp_device *dp);
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char data);
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char *data);
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[]);
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[]);
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr);
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int *data);
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char edid[]);
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
+void analogix_dp_reset_macro(struct analogix_dp_device *dp);
+void analogix_dp_init_video(struct analogix_dp_device *dp);
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+			enum clock_recovery_m_value_type type,
+			u32 m_value,
+			u32 n_value);
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_start_video(struct analogix_dp_device *dp);
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
+#endif /* _ANALOGIX_DP_CORE_H */
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
similarity index 84%
rename from drivers/gpu/drm/exynos/exynos_dp_reg.c
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index c1f87a2..0b926ea 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1,5 +1,5 @@
 /*
- * Samsung DP (Display port) register interface driver.
+ * Analogix DP (Display port) core register interface driver.
  *
  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  * Author: Jingoo Han <jg1.han@samsung.com>
@@ -15,8 +15,8 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
-#include "exynos_dp_core.h"
-#include "exynos_dp_reg.h"
+#include "analogix_dp_core.h"
+#include "analogix_dp_reg.h"
 
 #define COMMON_INT_MASK_1	0
 #define COMMON_INT_MASK_2	0
@@ -24,7 +24,7 @@
 #define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
 #define INT_STA_MASK		INT_HPD
 
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
 {
 	u32 reg;
 
@@ -39,7 +39,7 @@ void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
 	}
 }
 
-void exynos_dp_stop_video(struct exynos_dp_device *dp)
+void analogix_dp_stop_video(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -48,7 +48,7 @@ void exynos_dp_stop_video(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
 }
 
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
 {
 	u32 reg;
 
@@ -62,7 +62,7 @@ void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
 	writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
 }
 
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -84,7 +84,7 @@ void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
 }
 
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
 {
 	/* Set interrupt pin assertion polarity as high */
 	writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
@@ -104,12 +104,12 @@ void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
 	writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
 }
 
-void exynos_dp_reset(struct exynos_dp_device *dp)
+void analogix_dp_reset(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	exynos_dp_stop_video(dp);
-	exynos_dp_enable_video_mute(dp, 0);
+	analogix_dp_stop_video(dp);
+	analogix_dp_enable_video_mute(dp, 0);
 
 	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
@@ -123,7 +123,7 @@ void exynos_dp_reset(struct exynos_dp_device *dp)
 
 	usleep_range(20, 30);
 
-	exynos_dp_lane_swap(dp, 0);
+	analogix_dp_lane_swap(dp, 0);
 
 	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
 	writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
@@ -149,12 +149,12 @@ void exynos_dp_reset(struct exynos_dp_device *dp)
 	writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
 }
 
-void exynos_dp_swreset(struct exynos_dp_device *dp)
+void analogix_dp_swreset(struct analogix_dp_device *dp)
 {
 	writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
 }
 
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -175,7 +175,7 @@ void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
 }
 
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -186,7 +186,7 @@ enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
 		return PLL_UNLOCKED;
 }
 
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
 {
 	u32 reg;
 
@@ -201,7 +201,7 @@ void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
 	}
 }
 
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				enum analog_power_block block,
 				bool enable)
 {
@@ -288,12 +288,12 @@ void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
 	}
 }
 
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
 {
 	u32 reg;
 	int timeout_loop = 0;
 
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 
 	reg = PLL_LOCK_CHG;
 	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
@@ -303,10 +303,10 @@ void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
 
 	/* Power up PLL */
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-		exynos_dp_set_pll_power_down(dp, 0);
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		analogix_dp_set_pll_power_down(dp, 0);
 
-		while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
 			timeout_loop++;
 			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 				dev_err(dp->dev, "failed to get pll lock status\n");
@@ -323,7 +323,7 @@ void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 }
 
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -337,21 +337,21 @@ void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 }
 
-void exynos_dp_init_hpd(struct exynos_dp_device *dp)
+void analogix_dp_init_hpd(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
 	if (gpio_is_valid(dp->hpd_gpio))
 		return;
 
-	exynos_dp_clear_hotplug_interrupts(dp);
+	analogix_dp_clear_hotplug_interrupts(dp);
 
 	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 	reg &= ~(F_HPD | HPD_CTRL);
 	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
 }
 
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -378,7 +378,7 @@ enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
 	}
 }
 
-void exynos_dp_reset_aux(struct exynos_dp_device *dp)
+void analogix_dp_reset_aux(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -388,7 +388,7 @@ void exynos_dp_reset_aux(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 }
 
-void exynos_dp_init_aux(struct exynos_dp_device *dp)
+void analogix_dp_init_aux(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -396,7 +396,7 @@ void exynos_dp_init_aux(struct exynos_dp_device *dp)
 	reg = RPLY_RECEIV | AUX_ERR;
 	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
 
-	exynos_dp_reset_aux(dp);
+	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
 	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
@@ -413,7 +413,7 @@ void exynos_dp_init_aux(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
 }
 
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -429,7 +429,7 @@ int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
 	return -EINVAL;
 }
 
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -438,7 +438,7 @@ void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
 }
 
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
 {
 	int reg;
 	int retval = 0;
@@ -482,7 +482,7 @@ int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
 	return retval;
 }
 
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
 				unsigned int reg_addr,
 				unsigned char data)
 {
@@ -516,7 +516,7 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
 		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 
 		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
+		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
 		else
@@ -527,7 +527,7 @@ int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
 	return retval;
 }
 
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 				unsigned int reg_addr,
 				unsigned char *data)
 {
@@ -557,7 +557,7 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 
 		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
+		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
 		else
@@ -572,7 +572,7 @@ int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
 	return retval;
 }
 
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 				unsigned int reg_addr,
 				unsigned int count,
 				unsigned char data[])
@@ -622,7 +622,7 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 
 			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
+			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
 			else
@@ -636,7 +636,7 @@ int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
 	return retval;
 }
 
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 				unsigned int reg_addr,
 				unsigned int count,
 				unsigned char data[])
@@ -680,7 +680,7 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
 			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 
 			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
+			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
 			else
@@ -702,7 +702,7 @@ int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
 	return retval;
 }
 
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
 				unsigned int device_addr,
 				unsigned int reg_addr)
 {
@@ -728,14 +728,14 @@ int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
 	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 
 	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction(dp);
+	retval = analogix_dp_start_aux_transaction(dp);
 	if (retval != 0)
 		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 
 	return retval;
 }
 
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 				unsigned int device_addr,
 				unsigned int reg_addr,
 				unsigned int *data)
@@ -750,7 +750,7 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
 
 		/* Select EDID device */
-		retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
+		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
 		if (retval != 0)
 			continue;
 
@@ -764,7 +764,7 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
 
 		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
+		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
 		else
@@ -779,7 +779,7 @@ int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
 	return retval;
 }
 
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 				unsigned int device_addr,
 				unsigned int reg_addr,
 				unsigned int count,
@@ -807,7 +807,7 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 			 * request without sending address
 			 */
 			if (!defer)
-				retval = exynos_dp_select_i2c_device(dp,
+				retval = analogix_dp_select_i2c_device(dp,
 						device_addr, reg_addr + i);
 			else
 				defer = 0;
@@ -825,7 +825,7 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 					EXYNOS_DP_AUX_CH_CTL_1);
 
 				/* Start AUX transaction */
-				retval = exynos_dp_start_aux_transaction(dp);
+				retval = analogix_dp_start_aux_transaction(dp);
 				if (retval == 0)
 					break;
 				else
@@ -852,7 +852,7 @@ int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
 	return retval;
 }
 
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
 {
 	u32 reg;
 
@@ -861,7 +861,7 @@ void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
 		writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
 }
 
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
 {
 	u32 reg;
 
@@ -869,7 +869,7 @@ void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
 	*bwtype = reg;
 }
 
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
 {
 	u32 reg;
 
@@ -877,7 +877,7 @@ void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
 	writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
 }
 
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
 {
 	u32 reg;
 
@@ -885,7 +885,7 @@ void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
 	*count = reg;
 }
 
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
 {
 	u32 reg;
 
@@ -900,8 +900,8 @@ void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
 	}
 }
 
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern)
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				enum pattern_set pattern)
 {
 	u32 reg;
 
@@ -933,7 +933,7 @@ void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
 	}
 }
 
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
 {
 	u32 reg;
 
@@ -943,7 +943,7 @@ void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 }
 
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
 {
 	u32 reg;
 
@@ -953,7 +953,7 @@ void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 }
 
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
 {
 	u32 reg;
 
@@ -963,7 +963,7 @@ void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 }
 
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
 {
 	u32 reg;
 
@@ -973,7 +973,7 @@ void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
 	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 }
 
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
 					u32 training_lane)
 {
 	u32 reg;
@@ -982,7 +982,7 @@ void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
 	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
 }
 
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
 					u32 training_lane)
 {
 	u32 reg;
@@ -991,8 +991,8 @@ void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
 	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
 }
 
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1000,7 +1000,7 @@ void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
 	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
 }
 
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
 					u32 training_lane)
 {
 	u32 reg;
@@ -1009,7 +1009,7 @@ void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
 	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
 }
 
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -1017,7 +1017,7 @@ u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
 	return reg;
 }
 
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -1025,7 +1025,7 @@ u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
 	return reg;
 }
 
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -1033,7 +1033,7 @@ u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
 	return reg;
 }
 
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -1041,7 +1041,7 @@ u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
 	return reg;
 }
 
-void exynos_dp_reset_macro(struct exynos_dp_device *dp)
+void analogix_dp_reset_macro(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -1056,7 +1056,7 @@ void exynos_dp_reset_macro(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
 }
 
-void exynos_dp_init_video(struct exynos_dp_device *dp)
+void analogix_dp_init_video(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -1076,7 +1076,7 @@ void exynos_dp_init_video(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
 }
 
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -1096,7 +1096,7 @@ void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
 }
 
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -1124,7 +1124,7 @@ int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
 	return 0;
 }
 
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
 		enum clock_recovery_m_value_type type,
 		u32 m_value,
 		u32 n_value)
@@ -1159,7 +1159,7 @@ void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
 	}
 }
 
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
 {
 	u32 reg;
 
@@ -1174,7 +1174,7 @@ void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
 	}
 }
 
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
 {
 	u32 reg;
 
@@ -1191,7 +1191,7 @@ void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
 	}
 }
 
-void exynos_dp_start_video(struct exynos_dp_device *dp)
+void analogix_dp_start_video(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -1200,7 +1200,7 @@ void exynos_dp_start_video(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
 }
 
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -1216,7 +1216,7 @@ int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
 	return 0;
 }
 
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -1244,7 +1244,7 @@ void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
 }
 
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
@@ -1253,7 +1253,7 @@ void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
 	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
 }
 
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
similarity index 98%
rename from drivers/gpu/drm/exynos/exynos_dp_reg.h
rename to drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 2e9bd0e..b9661c9 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -1,5 +1,5 @@
 /*
- * Register definition file for Samsung DP driver
+ * Register definition file for Analogix DP core driver
  *
  * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  * Author: Jingoo Han <jg1.han@samsung.com>
@@ -9,8 +9,8 @@
  * published by the Free Software Foundation.
  */
 
-#ifndef _EXYNOS_DP_REG_H
-#define _EXYNOS_DP_REG_H
+#ifndef _ANALOGIX_DP_REG_H
+#define _ANALOGIX_DP_REG_H
 
 #define EXYNOS_DP_TX_SW_RESET			0x14
 #define EXYNOS_DP_FUNC_EN_1			0x18
@@ -363,4 +363,4 @@
 #define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
 #define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
 
-#endif /* _EXYNOS_DP_REG_H */
+#endif /* _ANALOGIX_DP_REG_H */
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index 83efca9..b3e90bd 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -71,8 +71,9 @@ config DRM_EXYNOS_DSI
 	  This enables support for Exynos MIPI-DSI device.
 
 config DRM_EXYNOS_DP
-	bool "Display Port"
+	bool "EXYNOS specific extensions for Analogix DP driver"
 	depends on DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON
+	select DRM_ANALOGIX_DP
 	default DRM_EXYNOS
 	select DRM_PANEL
 	help
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index 6496532..18244c5 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -13,7 +13,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON)	+= exynos5433_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON)	+= exynos7_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DPI)	+= exynos_drm_dpi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DSI)	+= exynos_drm_dsi.o
-exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o exynos_dp_reg.o
+exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_MIXER)	+= exynos_mixer.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)	+= exynos_hdmi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI)	+= exynos_drm_vidi.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 673164b..c6519b9 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -14,967 +14,75 @@
 #include <linux/platform_device.h>
 #include <linux/err.h>
 #include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/of.h>
-#include <linux/of_gpio.h>
 #include <linux/of_graph.h>
-#include <linux/gpio.h>
 #include <linux/component.h>
-#include <linux/phy/phy.h>
 #include <video/of_display_timing.h>
 #include <video/of_videomode.h>
 
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
-#include <drm/drm_atomic_helper.h>
 #include <drm/drm_panel.h>
 
-#include "exynos_dp_core.h"
+#include <drm/bridge/analogix_dp.h>
+#include <drm/exynos_drm.h>
+
 #include "exynos_drm_crtc.h"
 
-#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
-					connector)
+#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
 
-static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
-{
-	return to_exynos_crtc(dp->encoder.crtc);
-}
+struct exynos_dp_device {
+	struct drm_encoder         encoder;
+	struct drm_connector       connector;
+	struct drm_bridge          *ptn_bridge;
+	struct drm_device          *drm_dev;
+	struct device              *dev;
 
-static inline struct exynos_dp_device *encoder_to_dp(
-						struct drm_encoder *e)
-{
-	return container_of(e, struct exynos_dp_device, encoder);
-}
-
-struct bridge_init {
-	struct i2c_client *client;
-	struct device_node *node;
+	struct exynos_drm_panel_info priv;
+	struct analogix_dp_plat_data plat_data;
 };
 
-static void exynos_dp_init_dp(struct exynos_dp_device *dp)
-{
-	exynos_dp_reset(dp);
-
-	exynos_dp_swreset(dp);
-
-	exynos_dp_init_analog_param(dp);
-	exynos_dp_init_interrupt(dp);
-
-	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_function(dp);
-
-	exynos_dp_config_interrupt(dp);
-	exynos_dp_init_analog_func(dp);
-
-	exynos_dp_init_hpd(dp);
-	exynos_dp_init_aux(dp);
-}
-
-static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
-{
-	int timeout_loop = 0;
-
-	while (exynos_dp_get_plug_in_status(dp) != 0) {
-		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "failed to get hpd plug status\n");
-			return -ETIMEDOUT;
-		}
-		usleep_range(10, 11);
-	}
-
-	return 0;
-}
-
-static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
-{
-	int i;
-	unsigned char sum = 0;
-
-	for (i = 0; i < EDID_BLOCK_LENGTH; i++)
-		sum = sum + edid_data[i];
-
-	return sum;
-}
-
-static int exynos_dp_read_edid(struct exynos_dp_device *dp)
-{
-	unsigned char edid[EDID_BLOCK_LENGTH * 2];
-	unsigned int extend_block = 0;
-	unsigned char sum;
-	unsigned char test_vector;
-	int retval;
-
-	/*
-	 * EDID device address is 0x50.
-	 * However, if necessary, you must have set upper address
-	 * into E-EDID in I2C device, 0x30.
-	 */
-
-	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-				EDID_EXTENSION_FLAG,
-				&extend_block);
-	if (retval)
-		return retval;
-
-	if (extend_block > 0) {
-		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
-
-		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-						EDID_HEADER_PATTERN,
-						EDID_BLOCK_LENGTH,
-						&edid[EDID_HEADER_PATTERN]);
-		if (retval != 0) {
-			dev_err(dp->dev, "EDID Read failed!\n");
-			return -EIO;
-		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
-		if (sum != 0) {
-			dev_err(dp->dev, "EDID bad checksum!\n");
-			return -EIO;
-		}
-
-		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_BLOCK_LENGTH,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_BLOCK_LENGTH]);
-		if (retval != 0) {
-			dev_err(dp->dev, "EDID Read failed!\n");
-			return -EIO;
-		}
-		sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
-		if (sum != 0) {
-			dev_err(dp->dev, "EDID bad checksum!\n");
-			return -EIO;
-		}
-
-		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					&test_vector);
-		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
-		}
-	} else {
-		dev_info(dp->dev, "EDID data does not include any extensions.\n");
-
-		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_HEADER_PATTERN,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_HEADER_PATTERN]);
-		if (retval != 0) {
-			dev_err(dp->dev, "EDID Read failed!\n");
-			return -EIO;
-		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
-		if (sum != 0) {
-			dev_err(dp->dev, "EDID bad checksum!\n");
-			return -EIO;
-		}
-
-		exynos_dp_read_byte_from_dpcd(dp,
-			DP_TEST_REQUEST,
-			&test_vector);
-		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
-		}
-	}
-
-	dev_dbg(dp->dev, "EDID Read success!\n");
-	return 0;
-}
-
-static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
-{
-	u8 buf[12];
-	int i;
-	int retval;
-
-	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
-				12, buf);
-	if (retval)
-		return retval;
-
-	/* Read EDID */
-	for (i = 0; i < 3; i++) {
-		retval = exynos_dp_read_edid(dp);
-		if (!retval)
-			break;
-	}
-
-	return retval;
-}
-
-static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
-						bool enable)
-{
-	u8 data;
-
-	exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
-
-	if (enable)
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DP_LANE_COUNT_ENHANCED_FRAME_EN |
-			DPCD_LANE_COUNT_SET(data));
-	else
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DPCD_LANE_COUNT_SET(data));
-}
-
-static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
-{
-	u8 data;
-	int retval;
-
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
-	retval = DPCD_ENHANCED_FRAME_CAP(data);
-
-	return retval;
-}
-
-static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
-{
-	u8 data;
-
-	data = exynos_dp_is_enhanced_mode_available(dp);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, data);
-	exynos_dp_enable_enhanced_mode(dp, data);
-}
-
-static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
-{
-	exynos_dp_set_training_pattern(dp, DP_NONE);
-
-	exynos_dp_write_byte_to_dpcd(dp,
-		DP_TRAINING_PATTERN_SET,
-		DP_TRAINING_PATTERN_DISABLE);
-}
-
-static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
-					int pre_emphasis, int lane)
-{
-	switch (lane) {
-	case 0:
-		exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
-		break;
-	case 1:
-		exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
-		break;
-
-	case 2:
-		exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
-		break;
-
-	case 3:
-		exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
-		break;
-	}
-}
-
-static int exynos_dp_link_start(struct exynos_dp_device *dp)
-{
-	u8 buf[4];
-	int lane, lane_count, pll_tries, retval;
-
-	lane_count = dp->link_train.lane_count;
-
-	dp->link_train.lt_state = CLOCK_RECOVERY;
-	dp->link_train.eq_loop = 0;
-
-	for (lane = 0; lane < lane_count; lane++)
-		dp->link_train.cr_loop[lane] = 0;
-
-	/* Set link rate and count as you want to establish*/
-	exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
-	exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
-
-	/* Setup RX configuration */
-	buf[0] = dp->link_train.link_rate;
-	buf[1] = dp->link_train.lane_count;
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
-				2, buf);
-	if (retval)
-		return retval;
-
-	/* Set TX pre-emphasis to minimum */
-	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_lane_pre_emphasis(dp,
-			PRE_EMPHASIS_LEVEL_0, lane);
-
-	/* Wait for PLL lock */
-	pll_tries = 0;
-	while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-		if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
-			dev_err(dp->dev, "Wait for PLL lock timed out\n");
-			return -ETIMEDOUT;
-		}
-
-		pll_tries++;
-		usleep_range(90, 120);
-	}
-
-	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
-
-	/* Set RX training pattern */
-	retval = exynos_dp_write_byte_to_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
-	if (retval)
-		return retval;
-
-	for (lane = 0; lane < lane_count; lane++)
-		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
-			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
-
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, buf);
-
-	return retval;
-}
-
-static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
-{
-	int shift = (lane & 1) * 4;
-	u8 link_value = link_status[lane>>1];
-
-	return (link_value >> shift) & 0xf;
-}
-
-static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
-{
-	int lane;
-	u8 lane_status;
-
-	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
-		if ((lane_status & DP_LANE_CR_DONE) == 0)
-			return -EINVAL;
-	}
-	return 0;
-}
-
-static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				int lane_count)
+int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
+				bool enable)
 {
-	int lane;
-	u8 lane_status;
+	struct exynos_dp_device *dp = to_dp(plat_data);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct exynos_drm_crtc *crtc;
 
-	if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
-		return -EINVAL;
+	if (!encoder)
+		return -1;
 
-	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
-		lane_status &= DP_CHANNEL_EQ_BITS;
-		if (lane_status != DP_CHANNEL_EQ_BITS)
-			return -EINVAL;
-	}
+	crtc = to_exynos_crtc(encoder->crtc);
+	if (crtc && crtc->ops && crtc->ops->clock_enable)
+		crtc->ops->clock_enable(crtc, enable);
 
 	return 0;
 }
 
-static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							int lane)
-{
-	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
-
-	return (link_value >> shift) & 0x3;
-}
-
-static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
-					u8 adjust_request[2],
-					int lane)
-{
-	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
-
-	return ((link_value >> shift) & 0xc) >> 2;
-}
-
-static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
-					u8 training_lane_set, int lane)
-{
-	switch (lane) {
-	case 0:
-		exynos_dp_set_lane0_link_training(dp, training_lane_set);
-		break;
-	case 1:
-		exynos_dp_set_lane1_link_training(dp, training_lane_set);
-		break;
-
-	case 2:
-		exynos_dp_set_lane2_link_training(dp, training_lane_set);
-		break;
-
-	case 3:
-		exynos_dp_set_lane3_link_training(dp, training_lane_set);
-		break;
-	}
-}
-
-static unsigned int exynos_dp_get_lane_link_training(
-				struct exynos_dp_device *dp,
-				int lane)
-{
-	u32 reg;
-
-	switch (lane) {
-	case 0:
-		reg = exynos_dp_get_lane0_link_training(dp);
-		break;
-	case 1:
-		reg = exynos_dp_get_lane1_link_training(dp);
-		break;
-	case 2:
-		reg = exynos_dp_get_lane2_link_training(dp);
-		break;
-	case 3:
-		reg = exynos_dp_get_lane3_link_training(dp);
-		break;
-	default:
-		WARN_ON(1);
-		return 0;
-	}
-
-	return reg;
-}
-
-static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
-{
-	exynos_dp_training_pattern_dis(dp);
-	exynos_dp_set_enhanced_mode(dp);
-
-	dp->link_train.lt_state = FAILED;
-}
-
-static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
-					u8 adjust_request[2])
-{
-	int lane, lane_count;
-	u8 voltage_swing, pre_emphasis, training_lane;
-
-	lane_count = dp->link_train.lane_count;
-	for (lane = 0; lane < lane_count; lane++) {
-		voltage_swing = exynos_dp_get_adjust_request_voltage(
-						adjust_request, lane);
-		pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
-						adjust_request, lane);
-		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
-				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
-
-		if (voltage_swing == VOLTAGE_LEVEL_3)
-			training_lane |= DP_TRAIN_MAX_SWING_REACHED;
-		if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
-			training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
-		dp->link_train.training_lane[lane] = training_lane;
-	}
-}
-
-static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
-{
-	int lane, lane_count, retval;
-	u8 voltage_swing, pre_emphasis, training_lane;
-	u8 link_status[2], adjust_request[2];
-
-	usleep_range(100, 101);
-
-	lane_count = dp->link_train.lane_count;
-
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
-			DP_LANE0_1_STATUS, 2, link_status);
-	if (retval)
-		return retval;
-
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
-			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
-	if (retval)
-		return retval;
-
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
-		/* set training pattern 2 for EQ */
-		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
-
-		retval = exynos_dp_write_byte_to_dpcd(dp,
-				DP_TRAINING_PATTERN_SET,
-				DP_LINK_SCRAMBLING_DISABLE |
-				DP_TRAINING_PATTERN_2);
-		if (retval)
-			return retval;
-
-		dev_info(dp->dev, "Link Training Clock Recovery success\n");
-		dp->link_train.lt_state = EQUALIZER_TRAINING;
-	} else {
-		for (lane = 0; lane < lane_count; lane++) {
-			training_lane = exynos_dp_get_lane_link_training(
-							dp, lane);
-			voltage_swing = exynos_dp_get_adjust_request_voltage(
-							adjust_request, lane);
-			pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
-							adjust_request, lane);
-
-			if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
-					voltage_swing &&
-			    DPCD_PRE_EMPHASIS_GET(training_lane) ==
-					pre_emphasis)
-				dp->link_train.cr_loop[lane]++;
-
-			if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
-			    voltage_swing == VOLTAGE_LEVEL_3 ||
-			    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
-				dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
-					dp->link_train.cr_loop[lane],
-					voltage_swing, pre_emphasis);
-				exynos_dp_reduce_link_rate(dp);
-				return -EIO;
-			}
-		}
-	}
-
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
-
-	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
-			dp->link_train.training_lane[lane], lane);
-
-	retval = exynos_dp_write_bytes_to_dpcd(dp,
-			DP_TRAINING_LANE0_SET, lane_count,
-			dp->link_train.training_lane);
-	if (retval)
-		return retval;
-
-	return retval;
-}
-
-static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
-{
-	int lane, lane_count, retval;
-	u32 reg;
-	u8 link_align, link_status[2], adjust_request[2];
-
-	usleep_range(400, 401);
-
-	lane_count = dp->link_train.lane_count;
-
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
-			DP_LANE0_1_STATUS, 2, link_status);
-	if (retval)
-		return retval;
-
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
-		exynos_dp_reduce_link_rate(dp);
-		return -EIO;
-	}
-
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
-			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
-	if (retval)
-		return retval;
-
-	retval = exynos_dp_read_byte_from_dpcd(dp,
-			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
-	if (retval)
-		return retval;
-
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
-
-	if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
-		/* traing pattern Set to Normal */
-		exynos_dp_training_pattern_dis(dp);
-
-		dev_info(dp->dev, "Link Training success!\n");
-
-		exynos_dp_get_link_bandwidth(dp, &reg);
-		dp->link_train.link_rate = reg;
-		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
-			dp->link_train.link_rate);
-
-		exynos_dp_get_lane_count(dp, &reg);
-		dp->link_train.lane_count = reg;
-		dev_dbg(dp->dev, "final lane count = %.2x\n",
-			dp->link_train.lane_count);
-
-		/* set enhanced mode if available */
-		exynos_dp_set_enhanced_mode(dp);
-		dp->link_train.lt_state = FINISHED;
-
-		return 0;
-	}
-
-	/* not all locked */
-	dp->link_train.eq_loop++;
-
-	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
-		dev_err(dp->dev, "EQ Max loop\n");
-		exynos_dp_reduce_link_rate(dp);
-		return -EIO;
-	}
-
-	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
-			dp->link_train.training_lane[lane], lane);
-
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, dp->link_train.training_lane);
-
-	return retval;
-}
-
-static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
-					u8 *bandwidth)
-{
-	u8 data;
-
-	/*
-	 * For DP rev.1.1, Maximum link rate of Main Link lanes
-	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
-	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
-	*bandwidth = data;
-}
-
-static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
-					u8 *lane_count)
-{
-	u8 data;
-
-	/*
-	 * For DP rev.1.1, Maximum number of Main Link lanes
-	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
-	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
-	*lane_count = DPCD_MAX_LANE_COUNT(data);
-}
-
-static void exynos_dp_init_training(struct exynos_dp_device *dp,
-			enum link_lane_count_type max_lane,
-			enum link_rate_type max_rate)
-{
-	/*
-	 * MACRO_RST must be applied after the PLL_LOCK to avoid
-	 * the DP inter pair skew issue for at least 10 us
-	 */
-	exynos_dp_reset_macro(dp);
-
-	/* Initialize by reading RX's DPCD */
-	exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
-	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
-
-	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
-		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
-			dp->link_train.link_rate);
-		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
-	}
-
-	if (dp->link_train.lane_count == 0) {
-		dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
-			dp->link_train.lane_count);
-		dp->link_train.lane_count = (u8)LANE_COUNT1;
-	}
-
-	/* Setup TX lane count & rate */
-	if (dp->link_train.lane_count > max_lane)
-		dp->link_train.lane_count = max_lane;
-	if (dp->link_train.link_rate > max_rate)
-		dp->link_train.link_rate = max_rate;
-
-	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
-}
-
-static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
+static int exynos_dp_poweron(struct analogix_dp_plat_data *plat_data)
 {
-	int retval = 0, training_finished = 0;
-
-	dp->link_train.lt_state = START;
-
-	/* Process here */
-	while (!retval && !training_finished) {
-		switch (dp->link_train.lt_state) {
-		case START:
-			retval = exynos_dp_link_start(dp);
-			if (retval)
-				dev_err(dp->dev, "LT link start failed!\n");
-			break;
-		case CLOCK_RECOVERY:
-			retval = exynos_dp_process_clock_recovery(dp);
-			if (retval)
-				dev_err(dp->dev, "LT CR failed!\n");
-			break;
-		case EQUALIZER_TRAINING:
-			retval = exynos_dp_process_equalizer_training(dp);
-			if (retval)
-				dev_err(dp->dev, "LT EQ failed!\n");
-			break;
-		case FINISHED:
-			training_finished = 1;
-			break;
-		case FAILED:
-			return -EREMOTEIO;
-		}
-	}
-	if (retval)
-		dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
-
-	return retval;
+	return exynos_dp_crtc_clock_enable(plat_data, true);
 }
 
-static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
-				u32 count,
-				u32 bwtype)
+static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
 {
-	int i;
-	int retval;
-
-	for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
-		exynos_dp_init_training(dp, count, bwtype);
-		retval = exynos_dp_sw_link_training(dp);
-		if (retval == 0)
-			break;
-
-		usleep_range(100, 110);
-	}
-
-	return retval;
+	return exynos_dp_crtc_clock_enable(plat_data, false);
 }
 
-static int exynos_dp_config_video(struct exynos_dp_device *dp)
+static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data)
 {
-	int retval = 0;
-	int timeout_loop = 0;
-	int done_count = 0;
-
-	exynos_dp_config_video_slave_mode(dp);
-
-	exynos_dp_set_video_color_format(dp);
-
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-		dev_err(dp->dev, "PLL is not locked yet.\n");
-		return -EINVAL;
-	}
-
-	for (;;) {
-		timeout_loop++;
-		if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
-			break;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "Timeout of video streamclk ok\n");
-			return -ETIMEDOUT;
-		}
-
-		usleep_range(1, 2);
-	}
-
-	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
-
-	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
-
-	/* Disable video mute */
-	exynos_dp_enable_video_mute(dp, 0);
-
-	/* Configure video slave mode */
-	exynos_dp_enable_video_master(dp, 0);
-
-	timeout_loop = 0;
-
-	for (;;) {
-		timeout_loop++;
-		if (exynos_dp_is_video_stream_on(dp) == 0) {
-			done_count++;
-			if (done_count > 10)
-				break;
-		} else if (done_count) {
-			done_count = 0;
-		}
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "Timeout of video streamclk ok\n");
-			return -ETIMEDOUT;
-		}
-
-		usleep_range(1000, 1001);
-	}
-
-	if (retval != 0)
-		dev_err(dp->dev, "Video stream is not detected!\n");
-
-	return retval;
-}
-
-static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
-{
-	u8 data;
-
-	if (enable) {
-		exynos_dp_enable_scrambling(dp);
-
-		exynos_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
-	} else {
-		exynos_dp_disable_scrambling(dp);
-
-		exynos_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
-	}
-}
-
-static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
-{
-	struct exynos_dp_device *dp = arg;
-
-	enum dp_irq_type irq_type;
-
-	irq_type = exynos_dp_get_irq_type(dp);
-	switch (irq_type) {
-	case DP_IRQ_TYPE_HP_CABLE_IN:
-		dev_dbg(dp->dev, "Received irq - cable in\n");
-		schedule_work(&dp->hotplug_work);
-		exynos_dp_clear_hotplug_interrupts(dp);
-		break;
-	case DP_IRQ_TYPE_HP_CABLE_OUT:
-		dev_dbg(dp->dev, "Received irq - cable out\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
-		break;
-	case DP_IRQ_TYPE_HP_CHANGE:
-		/*
-		 * We get these change notifications once in a while, but there
-		 * is nothing we can do with them. Just ignore it for now and
-		 * only handle cable changes.
-		 */
-		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
-		break;
-	default:
-		dev_err(dp->dev, "Received irq - unknown type!\n");
-		break;
-	}
-	return IRQ_HANDLED;
-}
-
-static void exynos_dp_hotplug(struct work_struct *work)
-{
-	struct exynos_dp_device *dp;
-
-	dp = container_of(work, struct exynos_dp_device, hotplug_work);
-
-	if (dp->drm_dev)
-		drm_helper_hpd_irq_event(dp->drm_dev);
-}
-
-static void exynos_dp_commit(struct drm_encoder *encoder)
-{
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
-	int ret;
-
-	/* Keep the panel disabled while we configure video */
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel))
-			DRM_ERROR("failed to disable the panel\n");
-	}
-
-	ret = exynos_dp_detect_hpd(dp);
-	if (ret) {
-		/* Cable has been disconnected, we're done */
-		return;
-	}
-
-	ret = exynos_dp_handle_edid(dp);
-	if (ret) {
-		dev_err(dp->dev, "unable to handle edid\n");
-		return;
-	}
-
-	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
-					dp->video_info->link_rate);
-	if (ret) {
-		dev_err(dp->dev, "unable to do link train\n");
-		return;
-	}
-
-	exynos_dp_enable_scramble(dp, 1);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
-	exynos_dp_enable_enhanced_mode(dp, 1);
-
-	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
-	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
-	exynos_dp_init_video(dp);
-	ret = exynos_dp_config_video(dp);
-	if (ret)
-		dev_err(dp->dev, "unable to config video\n");
-
-	/* Safe to enable the panel now */
-	if (dp->panel) {
-		if (drm_panel_enable(dp->panel))
-			DRM_ERROR("failed to enable the panel\n");
-	}
-
-	/* Enable video */
-	exynos_dp_start_video(dp);
-}
-
-static enum drm_connector_status exynos_dp_detect(
-				struct drm_connector *connector, bool force)
-{
-	return connector_status_connected;
-}
-
-static void exynos_dp_connector_destroy(struct drm_connector *connector)
-{
-	drm_connector_unregister(connector);
-	drm_connector_cleanup(connector);
-}
-
-static const struct drm_connector_funcs exynos_dp_connector_funcs = {
-	.dpms = drm_atomic_helper_connector_dpms,
-	.fill_modes = drm_helper_probe_single_connector_modes,
-	.detect = exynos_dp_detect,
-	.destroy = exynos_dp_connector_destroy,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static int exynos_dp_get_modes(struct drm_connector *connector)
-{
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
+	struct exynos_dp_device *dp = to_dp(plat_data);
+	struct drm_connector *connector = &dp->connector;
 	struct drm_display_mode *mode;
+	int num_modes = 0;
 
-	if (dp->panel)
-		return drm_panel_get_modes(dp->panel);
+	if (dp->plat_data.panel)
+		return num_modes;
 
 	mode = drm_mode_create(connector->dev);
 	if (!mode) {
 		DRM_ERROR("failed to create a new display mode.\n");
-		return 0;
+		return num_modes;
 	}
 
 	drm_display_mode_from_videomode(&dp->priv.vm, mode);
@@ -987,171 +95,31 @@ static int exynos_dp_get_modes(struct drm_connector *connector)
 	drm_mode_set_name(mode);
 	drm_mode_probed_add(connector, mode);
 
-	return 1;
-}
-
-static struct drm_encoder *exynos_dp_best_encoder(
-			struct drm_connector *connector)
-{
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
-
-	return &dp->encoder;
-}
-
-static const struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
-	.get_modes = exynos_dp_get_modes,
-	.best_encoder = exynos_dp_best_encoder,
-};
-
-/* returns the number of bridges attached */
-static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
-		struct drm_encoder *encoder)
-{
-	int ret;
-
-	encoder->bridge->next = dp->ptn_bridge;
-	dp->ptn_bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
-	if (ret) {
-		DRM_ERROR("Failed to attach bridge to drm\n");
-		return ret;
-	}
-
-	return 0;
+	return num_modes + 1;
 }
 
-static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
+static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+				   struct drm_bridge *bridge,
+				   struct drm_connector *connector)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
+	struct exynos_dp_device *dp = to_dp(plat_data);
 	struct drm_encoder *encoder = &dp->encoder;
-	struct drm_connector *connector = &dp->connector;
 	int ret;
 
-	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->ptn_bridge) {
-		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
-		if (!ret)
-			return 0;
-	}
-
-	connector->polled = DRM_CONNECTOR_POLL_HPD;
-
-	ret = drm_connector_init(dp->drm_dev, connector,
-			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
-	if (ret) {
-		DRM_ERROR("Failed to initialize connector with drm\n");
-		return ret;
-	}
-
-	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
 	drm_connector_register(connector);
-	drm_mode_connector_attach_encoder(connector, encoder);
-
-	if (dp->panel)
-		ret = drm_panel_attach(dp->panel, &dp->connector);
-
-	return ret;
-}
-
-static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
-{
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
-
-	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
-		return;
-
-	pm_runtime_get_sync(dp->dev);
-
-	if (dp->panel) {
-		if (drm_panel_prepare(dp->panel)) {
-			DRM_ERROR("failed to setup the panel\n");
-			return;
-		}
-	}
-
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), true);
-
-	phy_power_on(dp->phy);
-	exynos_dp_init_dp(dp);
-	enable_irq(dp->irq);
-	exynos_dp_commit(&dp->encoder);
 
-	dp->dpms_mode = DRM_MODE_DPMS_ON;
-}
-
-static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
-{
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
-
-	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
-		return;
-
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel)) {
-			DRM_ERROR("failed to disable the panel\n");
-			return;
+	/* Pre-empt DP connector creation if there's a bridge */
+	if (dp->ptn_bridge) {
+		bridge->next = dp->ptn_bridge;
+		dp->ptn_bridge->encoder = encoder;
+		ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
+		if (ret) {
+			DRM_ERROR("Failed to attach bridge to drm\n");
+			bridge->next = NULL;
+			return ret;
 		}
 	}
 
-	disable_irq(dp->irq);
-	flush_work(&dp->hotplug_work);
-	phy_power_off(dp->phy);
-
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), false);
-
-	if (dp->panel) {
-		if (drm_panel_unprepare(dp->panel))
-			DRM_ERROR("failed to turnoff the panel\n");
-	}
-
-	pm_runtime_put_sync(dp->dev);
-
-	dp->dpms_mode = DRM_MODE_DPMS_OFF;
-}
-
-static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
-{
-	/* do nothing */
-}
-
-static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
-	.enable = exynos_dp_bridge_enable,
-	.disable = exynos_dp_bridge_disable,
-	.pre_enable = exynos_dp_bridge_nop,
-	.post_disable = exynos_dp_bridge_nop,
-	.attach = exynos_dp_bridge_attach,
-};
-
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
-{
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
-	struct drm_device *drm_dev = dp->drm_dev;
-	struct drm_bridge *bridge;
-	int ret;
-
-	bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
-	if (!bridge) {
-		DRM_ERROR("failed to allocate for drm bridge\n");
-		return -ENOMEM;
-	}
-
-	dp->bridge = bridge;
-
-	encoder->bridge = bridge;
-	bridge->driver_private = dp;
-	bridge->encoder = encoder;
-	bridge->funcs = &exynos_dp_bridge_funcs;
-
-	ret = drm_bridge_attach(drm_dev, bridge);
-	if (ret) {
-		DRM_ERROR("failed to attach drm bridge\n");
-		return -EINVAL;
-	}
-
 	return 0;
 }
 
@@ -1168,83 +136,22 @@ static void exynos_dp_mode_set(struct drm_encoder *encoder,
 {
 }
 
-static void exynos_dp_enable(struct drm_encoder *encoder)
-{
-}
-
-static void exynos_dp_disable(struct drm_encoder *encoder)
+static void exynos_dp_nop(struct drm_encoder *encoder)
 {
+	/* do nothing */
 }
 
 static const struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
 	.mode_fixup = exynos_dp_mode_fixup,
 	.mode_set = exynos_dp_mode_set,
-	.enable = exynos_dp_enable,
-	.disable = exynos_dp_disable,
+	.enable = exynos_dp_nop,
+	.disable = exynos_dp_nop,
 };
 
 static const struct drm_encoder_funcs exynos_dp_encoder_funcs = {
 	.destroy = drm_encoder_cleanup,
 };
 
-static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
-{
-	struct device_node *dp_node = dev->of_node;
-	struct video_info *dp_video_config;
-
-	dp_video_config = devm_kzalloc(dev,
-				sizeof(*dp_video_config), GFP_KERNEL);
-	if (!dp_video_config)
-		return ERR_PTR(-ENOMEM);
-
-	dp_video_config->h_sync_polarity =
-		of_property_read_bool(dp_node, "hsync-active-high");
-
-	dp_video_config->v_sync_polarity =
-		of_property_read_bool(dp_node, "vsync-active-high");
-
-	dp_video_config->interlaced =
-		of_property_read_bool(dp_node, "interlaced");
-
-	if (of_property_read_u32(dp_node, "samsung,color-space",
-				&dp_video_config->color_space)) {
-		dev_err(dev, "failed to get color-space\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				&dp_video_config->dynamic_range)) {
-		dev_err(dev, "failed to get dynamic-range\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				&dp_video_config->ycbcr_coeff)) {
-		dev_err(dev, "failed to get ycbcr-coeff\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				&dp_video_config->color_depth)) {
-		dev_err(dev, "failed to get color-depth\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				&dp_video_config->link_rate)) {
-		dev_err(dev, "failed to get link-rate\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				&dp_video_config->lane_count)) {
-		dev_err(dev, "failed to get lane-count\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	return dp_video_config;
-}
-
 static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
 {
 	int ret;
@@ -1261,97 +168,32 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
 static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-	struct platform_device *pdev = to_platform_device(dev);
-	struct drm_device *drm_dev = data;
 	struct drm_encoder *encoder = &dp->encoder;
-	struct resource *res;
-	unsigned int irq_flags;
-	int pipe, ret = 0;
+	struct drm_device *drm_dev = data;
+	int pipe, ret;
 
-	dp->dev = &pdev->dev;
-	dp->dpms_mode = DRM_MODE_DPMS_OFF;
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
 
-	dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
-	if (IS_ERR(dp->video_info))
-		return PTR_ERR(dp->video_info);
+	dp->dev = dev;
+	dp->drm_dev = drm_dev;
 
-	dp->phy = devm_phy_get(dp->dev, "dp");
-	if (IS_ERR(dp->phy)) {
-		dev_err(dp->dev, "no DP phy configured\n");
-		ret = PTR_ERR(dp->phy);
-		if (ret) {
-			/*
-			 * phy itself is not enabled, so we can move forward
-			 * assigning NULL to phy pointer.
-			 */
-			if (ret == -ENOSYS || ret == -ENODEV)
-				dp->phy = NULL;
-			else
-				return ret;
-		}
-	}
+	dp->plat_data.dev_type = EXYNOS_DP;
+	dp->plat_data.power_on = exynos_dp_poweron;
+	dp->plat_data.power_off = exynos_dp_poweroff;
+	dp->plat_data.attach = exynos_dp_bridge_attach;
+	dp->plat_data.get_modes = exynos_dp_get_modes;
 
-	if (!dp->panel && !dp->ptn_bridge) {
+	if (!dp->plat_data.panel && !dp->ptn_bridge) {
 		ret = exynos_dp_dt_parse_panel(dp);
 		if (ret)
 			return ret;
 	}
 
-	dp->clock = devm_clk_get(&pdev->dev, "dp");
-	if (IS_ERR(dp->clock)) {
-		dev_err(&pdev->dev, "failed to get clock\n");
-		return PTR_ERR(dp->clock);
-	}
-
-	clk_prepare_enable(dp->clock);
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
-	dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(dp->reg_base))
-		return PTR_ERR(dp->reg_base);
-
-	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		/*
-		 * Set up the hotplug GPIO from the device tree as an interrupt.
-		 * Simply specifying a different interrupt in the device tree
-		 * doesn't work since we handle hotplug rather differently when
-		 * using a GPIO.  We also need the actual GPIO specifier so
-		 * that we can get the current state of the GPIO.
-		 */
-		ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
-					    "hpd_gpio");
-		if (ret) {
-			dev_err(&pdev->dev, "failed to get hpd gpio\n");
-			return ret;
-		}
-		dp->irq = gpio_to_irq(dp->hpd_gpio);
-		irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
-	} else {
-		dp->hpd_gpio = -ENODEV;
-		dp->irq = platform_get_irq(pdev, 0);
-		irq_flags = 0;
-	}
-
-	if (dp->irq == -ENXIO) {
-		dev_err(&pdev->dev, "failed to get irq\n");
-		return -ENODEV;
-	}
-
-	INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
-
-	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
-			irq_flags, "exynos-dp", dp);
-	if (ret) {
-		dev_err(&pdev->dev, "failed to request irq\n");
-		return ret;
-	}
-	disable_irq(dp->irq);
-
-	dp->drm_dev = drm_dev;
-
 	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
 						  EXYNOS_DISPLAY_TYPE_LCD);
 	if (pipe < 0)
@@ -1366,22 +208,15 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 
 	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
 
-	ret = exynos_dp_create_connector(encoder);
-	if (ret) {
-		DRM_ERROR("failed to create connector ret = %d\n", ret);
-		drm_encoder_cleanup(encoder);
-		return ret;
-	}
+	dp->plat_data.encoder = encoder;
 
-	return 0;
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
 }
 
 static void exynos_dp_unbind(struct device *dev, struct device *master,
 				void *data)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-
-	exynos_dp_disable(&dp->encoder);
+	return analogix_dp_unbind(dev, master, data);
 }
 
 static const struct component_ops exynos_dp_ops = {
@@ -1394,21 +229,25 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct device_node *np = NULL, *endpoint = NULL;
 	struct exynos_dp_device *dp;
-	int ret;
 
 	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
 				GFP_KERNEL);
 	if (!dp)
 		return -ENOMEM;
 
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver would take charge of the drvdata.
+	 */
 	platform_set_drvdata(pdev, dp);
 
 	/* This is for the backward compatibility. */
 	np = of_parse_phandle(dev->of_node, "panel", 0);
 	if (np) {
-		dp->panel = of_drm_find_panel(np);
+		dp->plat_data.panel = of_drm_find_panel(np);
 		of_node_put(np);
-		if (!dp->panel)
+		if (!dp->plat_data.panel)
 			return -EPROBE_DEFER;
 		goto out;
 	}
@@ -1418,8 +257,8 @@ static int exynos_dp_probe(struct platform_device *pdev)
 		np = of_graph_get_remote_port_parent(endpoint);
 		if (np) {
 			/* The remote port can be either a panel or a bridge */
-			dp->panel = of_drm_find_panel(np);
-			if (!dp->panel) {
+			dp->plat_data.panel = of_drm_find_panel(np);
+			if (!dp->plat_data.panel) {
 				dp->ptn_bridge = of_drm_find_bridge(np);
 				if (!dp->ptn_bridge) {
 					of_node_put(np);
@@ -1437,23 +276,11 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	}
 
 out:
-	pm_runtime_enable(dev);
-
-	ret = component_add(&pdev->dev, &exynos_dp_ops);
-	if (ret)
-		goto err_disable_pm_runtime;
-
-	return ret;
-
-err_disable_pm_runtime:
-	pm_runtime_disable(dev);
-
-	return ret;
+	return component_add(&pdev->dev, &exynos_dp_ops);
 }
 
 static int exynos_dp_remove(struct platform_device *pdev)
 {
-	pm_runtime_disable(&pdev->dev);
 	component_del(&pdev->dev, &exynos_dp_ops);
 
 	return 0;
@@ -1462,25 +289,12 @@ static int exynos_dp_remove(struct platform_device *pdev)
 #ifdef CONFIG_PM
 static int exynos_dp_suspend(struct device *dev)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-
-	clk_disable_unprepare(dp->clock);
-
-	return 0;
+	return analogix_dp_suspend(dev);
 }
 
 static int exynos_dp_resume(struct device *dev)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-	int ret;
-
-	ret = clk_prepare_enable(dp->clock);
-	if (ret < 0) {
-		DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
-		return ret;
-	}
-
-	return 0;
+	return analogix_dp_resume(dev);
 }
 #endif
 
@@ -1506,5 +320,5 @@ struct platform_driver dp_driver = {
 };
 
 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
-MODULE_DESCRIPTION("Samsung SoC DP Driver");
+MODULE_DESCRIPTION("Samsung Specific Analogix-DP Driver Extension");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
deleted file mode 100644
index 66eec4b..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Header file for Samsung DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef _EXYNOS_DP_CORE_H
-#define _EXYNOS_DP_CORE_H
-
-#include <drm/drm_crtc.h>
-#include <drm/drm_dp_helper.h>
-#include <drm/exynos_drm.h>
-
-#include "exynos_drm_drv.h"
-
-#define DP_TIMEOUT_LOOP_COUNT 100
-#define MAX_CR_LOOP 5
-#define MAX_EQ_LOOP 5
-
-enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
-};
-
-enum link_lane_count_type {
-	LANE_COUNT1 = 1,
-	LANE_COUNT2 = 2,
-	LANE_COUNT4 = 4
-};
-
-enum link_training_state {
-	START,
-	CLOCK_RECOVERY,
-	EQUALIZER_TRAINING,
-	FINISHED,
-	FAILED
-};
-
-enum voltage_swing_level {
-	VOLTAGE_LEVEL_0,
-	VOLTAGE_LEVEL_1,
-	VOLTAGE_LEVEL_2,
-	VOLTAGE_LEVEL_3,
-};
-
-enum pre_emphasis_level {
-	PRE_EMPHASIS_LEVEL_0,
-	PRE_EMPHASIS_LEVEL_1,
-	PRE_EMPHASIS_LEVEL_2,
-	PRE_EMPHASIS_LEVEL_3,
-};
-
-enum pattern_set {
-	PRBS7,
-	D10_2,
-	TRAINING_PTN1,
-	TRAINING_PTN2,
-	DP_NONE
-};
-
-enum color_space {
-	COLOR_RGB,
-	COLOR_YCBCR422,
-	COLOR_YCBCR444
-};
-
-enum color_depth {
-	COLOR_6,
-	COLOR_8,
-	COLOR_10,
-	COLOR_12
-};
-
-enum color_coefficient {
-	COLOR_YCBCR601,
-	COLOR_YCBCR709
-};
-
-enum dynamic_range {
-	VESA,
-	CEA
-};
-
-enum pll_status {
-	PLL_UNLOCKED,
-	PLL_LOCKED
-};
-
-enum clock_recovery_m_value_type {
-	CALCULATED_M,
-	REGISTER_M
-};
-
-enum video_timing_recognition_type {
-	VIDEO_TIMING_FROM_CAPTURE,
-	VIDEO_TIMING_FROM_REGISTER
-};
-
-enum analog_power_block {
-	AUX_BLOCK,
-	CH0_BLOCK,
-	CH1_BLOCK,
-	CH2_BLOCK,
-	CH3_BLOCK,
-	ANALOG_TOTAL,
-	POWER_ALL
-};
-
-enum dp_irq_type {
-	DP_IRQ_TYPE_HP_CABLE_IN,
-	DP_IRQ_TYPE_HP_CABLE_OUT,
-	DP_IRQ_TYPE_HP_CHANGE,
-	DP_IRQ_TYPE_UNKNOWN,
-};
-
-struct video_info {
-	char *name;
-
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
-
-	enum color_space color_space;
-	enum dynamic_range dynamic_range;
-	enum color_coefficient ycbcr_coeff;
-	enum color_depth color_depth;
-
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
-};
-
-struct link_train {
-	int eq_loop;
-	int cr_loop[4];
-
-	u8 link_rate;
-	u8 lane_count;
-	u8 training_lane[4];
-
-	enum link_training_state lt_state;
-};
-
-struct exynos_dp_device {
-	struct drm_encoder	encoder;
-	struct device		*dev;
-	struct drm_device	*drm_dev;
-	struct drm_connector	connector;
-	struct drm_panel	*panel;
-	struct drm_bridge	*bridge;
-	struct drm_bridge	*ptn_bridge;
-	struct clk		*clock;
-	unsigned int		irq;
-	void __iomem		*reg_base;
-
-	struct video_info	*video_info;
-	struct link_train	link_train;
-	struct work_struct	hotplug_work;
-	struct phy		*phy;
-	int			dpms_mode;
-	int			hpd_gpio;
-
-	struct exynos_drm_panel_info priv;
-};
-
-/* exynos_dp_reg.c */
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_stop_video(struct exynos_dp_device *dp);
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
-void exynos_dp_reset(struct exynos_dp_device *dp);
-void exynos_dp_swreset(struct exynos_dp_device *dp);
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable);
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
-void exynos_dp_init_hpd(struct exynos_dp_device *dp);
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
-void exynos_dp_reset_aux(struct exynos_dp_device *dp);
-void exynos_dp_init_aux(struct exynos_dp_device *dp);
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern);
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
-void exynos_dp_reset_macro(struct exynos_dp_device *dp);
-void exynos_dp_init_video(struct exynos_dp_device *dp);
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_start_video(struct exynos_dp_device *dp);
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
-#endif /* _EXYNOS_DP_CORE_H */
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
new file mode 100644
index 0000000..d1188db
--- /dev/null
+++ b/include/drm/bridge/analogix_dp.h
@@ -0,0 +1,40 @@
+/*
+ * Analogix DP (Display Port) Core interface driver.
+ *
+ * Copyright (C) 2015 Rockchip Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _ANALOGIX_DP_H_
+#define _ANALOGIX_DP_H_
+
+#include <drm/drm_crtc.h>
+
+enum analogix_dp_devtype {
+	EXYNOS_DP,
+};
+
+struct analogix_dp_plat_data {
+	enum analogix_dp_devtype dev_type;
+	struct drm_panel *panel;
+	struct drm_encoder *encoder;
+	struct drm_connector *connector;
+
+	int (*power_on)(struct analogix_dp_plat_data *);
+	int (*power_off)(struct analogix_dp_plat_data *);
+	int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *,
+		      struct drm_connector *);
+	int (*get_modes)(struct analogix_dp_plat_data *);
+};
+
+int analogix_dp_resume(struct device *dev);
+int analogix_dp_suspend(struct device *dev);
+
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct analogix_dp_plat_data *plat_data);
+void analogix_dp_unbind(struct device *dev, struct device *master, void *data);
+
+#endif /* _ANALOGIX_DP_H_ */
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 02/17] drm/exynos: dp: rename implementation specific driver part
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
  2016-02-15 11:09 ` [PATCH v14 01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang
@ 2016-02-15 11:09 ` Yakir Yang
  2016-02-15 11:09 ` [PATCH v14 03/17] drm: bridge: analogix/dp: rename register constants Yakir Yang
                   ` (17 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:09 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

From: Heiko Stuebner <heiko@sntech.de>

The core functionality now resides in the generic bridge part so the
exynos-specific implementation details can get a more suitable nameing.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/exynos/Makefile                          | 2 +-
 drivers/gpu/drm/exynos/{exynos_dp_core.c => exynos_dp.c} | 0
 2 files changed, 1 insertion(+), 1 deletion(-)
 rename drivers/gpu/drm/exynos/{exynos_dp_core.c => exynos_dp.c} (100%)

diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index 18244c5..533151b 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -13,7 +13,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON)	+= exynos5433_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON)	+= exynos7_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DPI)	+= exynos_drm_dpi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DSI)	+= exynos_drm_dsi.o
-exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o
+exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_MIXER)	+= exynos_mixer.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)	+= exynos_hdmi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI)	+= exynos_drm_vidi.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp.c
similarity index 100%
rename from drivers/gpu/drm/exynos/exynos_dp_core.c
rename to drivers/gpu/drm/exynos/exynos_dp.c
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 03/17] drm: bridge: analogix/dp: rename register constants
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
  2016-02-15 11:09 ` [PATCH v14 01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang
  2016-02-15 11:09 ` [PATCH v14 02/17] drm/exynos: dp: rename implementation specific driver part Yakir Yang
@ 2016-02-15 11:09 ` Yakir Yang
  2016-02-15 11:09 ` [PATCH v14 04/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
                   ` (16 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:09 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

From: Heiko Stuebner <heiko@sntech.de>

In the original split we kept the register constants intact to keep the
diff small. Still the constants are Analogix-specific, so rename them now.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 456 +++++++++++-----------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 248 ++++++------
 2 files changed, 352 insertions(+), 352 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 0b926ea..442cc66 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -29,13 +29,13 @@ void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
 	u32 reg;
 
 	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
 		reg |= HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
 	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
 		reg &= ~HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
 	}
 }
 
@@ -43,9 +43,9 @@ void analogix_dp_stop_video(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
 	reg &= ~VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
 }
 
 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
@@ -59,7 +59,7 @@ void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
 		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
 			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
 
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
 }
 
 void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
@@ -67,41 +67,41 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
 	u32 reg;
 
 	reg = TX_TERMINAL_CTRL_50_OHM;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1);
 
 	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
 
 	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
+	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
 
 	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
 		TX_CUR1_2X | TX_CUR_16_MA;
-	writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1);
 
 	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
 		CH1_AMP_400_MV | CH0_AMP_400_MV;
-	writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL);
 }
 
 void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
 {
 	/* Set interrupt pin assertion polarity as high */
-	writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
+	writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL);
 
 	/* Clear pending regisers */
-	writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-	writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
-	writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
-	writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-	writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
+	writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
+	writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2);
+	writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3);
+	writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
+	writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA);
 
 	/* 0:mask,1: unmask */
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-	writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+	writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
 }
 
 void analogix_dp_reset(struct analogix_dp_device *dp)
@@ -114,44 +114,44 @@ void analogix_dp_reset(struct analogix_dp_device *dp)
 	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
 		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
 		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 
 	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
 		SERDES_FIFO_FUNC_EN_N |
 		LS_CLK_DOMAIN_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 
 	usleep_range(20, 30);
 
 	analogix_dp_lane_swap(dp, 0);
 
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 
-	writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
-	writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL);
 
-	writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
-	writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
+	writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L);
+	writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H);
 
-	writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
+	writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL);
 
-	writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST);
 
-	writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
-	writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD);
+	writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN);
 
-	writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
-	writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
+	writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH);
+	writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH);
 
-	writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
+	writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
 }
 
 void analogix_dp_swreset(struct analogix_dp_device *dp)
 {
-	writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
+	writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET);
 }
 
 void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
@@ -160,26 +160,26 @@ void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
 
 	/* 0: mask, 1: unmask */
 	reg = COMMON_INT_MASK_1;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1);
 
 	reg = COMMON_INT_MASK_2;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2);
 
 	reg = COMMON_INT_MASK_3;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3);
 
 	reg = COMMON_INT_MASK_4;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
 
 	reg = INT_STA_MASK;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
 }
 
 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
 	if (reg & PLL_LOCK)
 		return PLL_LOCKED;
 	else
@@ -191,13 +191,13 @@ void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
 	u32 reg;
 
 	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
 		reg |= DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
 	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
+		reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL);
 		reg &= ~DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
+		writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL);
 	}
 }
 
@@ -210,77 +210,77 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 	switch (block) {
 	case AUX_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
 			reg |= AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
 			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		}
 		break;
 	case CH0_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
 			reg |= CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
 			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		}
 		break;
 	case CH1_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
 			reg |= CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
 			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		}
 		break;
 	case CH2_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
 			reg |= CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
 			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		}
 		break;
 	case CH3_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
 			reg |= CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
 			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		}
 		break;
 	case ANALOG_TOTAL:
 		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
 			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
 			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		}
 		break;
 	case POWER_ALL:
 		if (enable) {
 			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		} else {
-			writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
+			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
 		}
 		break;
 	default:
@@ -296,11 +296,11 @@ void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
 	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
 
 	reg = PLL_LOCK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
 
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
+	reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
 	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL);
 
 	/* Power up PLL */
 	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
@@ -317,10 +317,10 @@ void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
 	}
 
 	/* Enable Serdes FIFO function and Link symbol clock domain module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
 		| AUX_FUNC_EN_N);
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 }
 
 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
@@ -331,10 +331,10 @@ void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
 		return;
 
 	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
 
 	reg = INT_HPD;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
 }
 
 void analogix_dp_init_hpd(struct analogix_dp_device *dp)
@@ -346,9 +346,9 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
 
 	analogix_dp_clear_hotplug_interrupts(dp);
 
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 	reg &= ~(F_HPD | HPD_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 }
 
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
@@ -363,7 +363,7 @@ enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
 			return DP_IRQ_TYPE_HP_CABLE_OUT;
 	} else {
 		/* Parse hotplug interrupt status register */
-		reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
+		reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4);
 
 		if (reg & PLUG)
 			return DP_IRQ_TYPE_HP_CABLE_IN;
@@ -383,9 +383,9 @@ void analogix_dp_reset_aux(struct analogix_dp_device *dp)
 	u32 reg;
 
 	/* Disable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 	reg |= AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 }
 
 void analogix_dp_init_aux(struct analogix_dp_device *dp)
@@ -394,23 +394,23 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 
 	/* Clear inerrupts related to AUX channel */
 	reg = RPLY_RECEIV | AUX_ERR;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA);
 
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
 	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
 		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
 	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL);
 
 	/* Enable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 	reg &= ~AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2);
 }
 
 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
@@ -421,7 +421,7 @@ int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
 		if (gpio_get_value(dp->hpd_gpio))
 			return 0;
 	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 		if (reg & HPD_STATUS)
 			return 0;
 	}
@@ -433,9 +433,9 @@ void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 	reg &= ~SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 }
 
 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
@@ -445,34 +445,34 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
 	int timeout_loop = 0;
 
 	/* Enable AUX CH operation */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
 	reg |= AUX_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
 
 	/* Is AUX CH command reply received? */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
 	while (!(reg & RPLY_RECEIV)) {
 		timeout_loop++;
 		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
 			dev_err(dp->dev, "AUX CH command reply failed!\n");
 			return -ETIMEDOUT;
 		}
-		reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
+		reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
 		usleep_range(10, 11);
 	}
 
 	/* Clear interrupt source for AUX CH command reply */
-	writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
+	writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA);
 
 	/* Clear interrupt source for AUX CH access error */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA);
 	if (reg & AUX_ERR) {
-		writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
+		writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA);
 		return -EREMOTEIO;
 	}
 
 	/* Check AUX CH error access status */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
+	reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA);
 	if ((reg & AUX_STATUS_MASK) != 0) {
 		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
 			reg & AUX_STATUS_MASK);
@@ -493,19 +493,19 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
 	for (i = 0; i < 3; i++) {
 		/* Clear AUX CH data buffer */
 		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 		/* Select DPCD device address */
 		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
 		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
 		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
 
 		/* Write data buffer */
 		reg = (unsigned int)data;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
 
 		/*
 		 * Set DisplayPort transaction and write 1 byte
@@ -513,7 +513,7 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
 		 * If Bit 3 is 0, I2C transaction.
 		 */
 		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
 
 		/* Start AUX transaction */
 		retval = analogix_dp_start_aux_transaction(dp);
@@ -538,15 +538,15 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 	for (i = 0; i < 3; i++) {
 		/* Clear AUX CH data buffer */
 		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 		/* Select DPCD device address */
 		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
 		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
 		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
 
 		/*
 		 * Set DisplayPort transaction and read 1 byte
@@ -554,7 +554,7 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 		 * If Bit 3 is 0, I2C transaction.
 		 */
 		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
 
 		/* Start AUX transaction */
 		retval = analogix_dp_start_aux_transaction(dp);
@@ -566,7 +566,7 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 	}
 
 	/* Read data buffer */
-	reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
+	reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
 	*data = (unsigned char)(reg & 0xff);
 
 	return retval;
@@ -586,7 +586,7 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 
 	/* Clear AUX CH data buffer */
 	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 	start_offset = 0;
 	while (start_offset < count) {
@@ -599,16 +599,16 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 		for (i = 0; i < 3; i++) {
 			/* Select DPCD device address */
 			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
 			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
 			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
 
 			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 			     cur_data_idx++) {
 				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
+				writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
 							  + 4 * cur_data_idx);
 			}
 
@@ -619,7 +619,7 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			 */
 			reg = AUX_LENGTH(cur_data_count) |
 				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
 
 			/* Start AUX transaction */
 			retval = analogix_dp_start_aux_transaction(dp);
@@ -650,7 +650,7 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 
 	/* Clear AUX CH data buffer */
 	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 	start_offset = 0;
 	while (start_offset < count) {
@@ -664,11 +664,11 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 		for (i = 0; i < 3; i++) {
 			/* Select DPCD device address */
 			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
 			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
 			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
 
 			/*
 			 * Set DisplayPort transaction and read
@@ -677,7 +677,7 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 			 */
 			reg = AUX_LENGTH(cur_data_count) |
 				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
 
 			/* Start AUX transaction */
 			retval = analogix_dp_start_aux_transaction(dp);
@@ -690,7 +690,7 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 
 		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 		    cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
 						 + 4 * cur_data_idx);
 			data[start_offset + cur_data_idx] =
 				(unsigned char)reg;
@@ -711,12 +711,12 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
 
 	/* Set EDID device address */
 	reg = device_addr;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8);
+	writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16);
 
 	/* Set offset from base address of EDID device */
-	writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
+	writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
 
 	/*
 	 * Set I2C transaction and write address
@@ -725,7 +725,7 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
 	 */
 	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
 		AUX_TX_COMM_WRITE;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
 
 	/* Start AUX transaction */
 	retval = analogix_dp_start_aux_transaction(dp);
@@ -747,7 +747,7 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 	for (i = 0; i < 3; i++) {
 		/* Clear AUX CH data buffer */
 		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
+		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 		/* Select EDID device */
 		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
@@ -761,7 +761,7 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		 */
 		reg = AUX_TX_COMM_I2C_TRANSACTION |
 			AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
+		writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1);
 
 		/* Start AUX transaction */
 		retval = analogix_dp_start_aux_transaction(dp);
@@ -774,7 +774,7 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 
 	/* Read data */
 	if (retval == 0)
-		*data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
+		*data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0);
 
 	return retval;
 }
@@ -795,12 +795,12 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 		for (j = 0; j < 3; j++) {
 			/* Clear AUX CH data buffer */
 			reg = BUF_CLR;
-			writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
+			writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 			/* Set normal AUX CH command */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
 			reg &= ~ADDR_ONLY;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
+			writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2);
 
 			/*
 			 * If Rx sends defer, Tx sends only reads
@@ -822,7 +822,7 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 					AUX_TX_COMM_I2C_TRANSACTION |
 					AUX_TX_COMM_READ;
 				writel(reg, dp->reg_base +
-					EXYNOS_DP_AUX_CH_CTL_1);
+					ANALOGIX_DP_AUX_CH_CTL_1);
 
 				/* Start AUX transaction */
 				retval = analogix_dp_start_aux_transaction(dp);
@@ -834,7 +834,7 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 						__func__);
 			}
 			/* Check if Rx sends defer */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
+			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
 			if (reg == AUX_RX_COMM_AUX_DEFER ||
 				reg == AUX_RX_COMM_I2C_DEFER) {
 				dev_err(dp->dev, "Defer: %d\n\n", reg);
@@ -843,7 +843,7 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 		}
 
 		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
+			reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0
 						 + 4 * cur_data_idx);
 			edid[i + cur_data_idx] = (unsigned char)reg;
 		}
@@ -858,14 +858,14 @@ void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
 
 	reg = bwtype;
 	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
-		writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
+		writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
 }
 
 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
+	reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
 	*bwtype = reg;
 }
 
@@ -874,14 +874,14 @@ void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
 	u32 reg;
 
 	reg = count;
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
+	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
 }
 
 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
+	reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET);
 	*count = reg;
 }
 
@@ -890,13 +890,13 @@ void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable
 	u32 reg;
 
 	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 		reg |= ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 		reg &= ~ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 	}
 }
 
@@ -908,25 +908,25 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
 	switch (pattern) {
 	case PRBS7:
 		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 		break;
 	case D10_2:
 		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 		break;
 	case TRAINING_PTN1:
 		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 		break;
 	case TRAINING_PTN2:
 		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 		break;
 	case DP_NONE:
 		reg = SCRAMBLING_ENABLE |
 			LINK_QUAL_PATTERN_SET_DISABLE |
 			SW_TRAINING_PATTERN_SET_NORMAL;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+		writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 		break;
 	default:
 		break;
@@ -937,40 +937,40 @@ void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
 	reg &= ~PRE_EMPHASIS_SET_MASK;
 	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
 }
 
 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
 	reg &= ~PRE_EMPHASIS_SET_MASK;
 	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
 }
 
 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
 	reg &= ~PRE_EMPHASIS_SET_MASK;
 	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
 }
 
 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
 	reg &= ~PRE_EMPHASIS_SET_MASK;
 	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
 }
 
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
@@ -979,7 +979,7 @@ void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
 	u32 reg;
 
 	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
 }
 
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
@@ -988,7 +988,7 @@ void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
 	u32 reg;
 
 	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
 }
 
 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
@@ -997,7 +997,7 @@ void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
 	u32 reg;
 
 	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
 }
 
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
@@ -1006,14 +1006,14 @@ void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
 	u32 reg;
 
 	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
 }
 
 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
 	return reg;
 }
 
@@ -1021,7 +1021,7 @@ u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
 	return reg;
 }
 
@@ -1029,7 +1029,7 @@ u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
 	return reg;
 }
 
@@ -1037,7 +1037,7 @@ u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
+	reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL);
 	return reg;
 }
 
@@ -1045,15 +1045,15 @@ void analogix_dp_reset_macro(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
+	reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST);
 	reg |= MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
 
 	/* 10 us is the minimum reset time. */
 	usleep_range(10, 20);
 
 	reg &= ~MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
+	writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST);
 }
 
 void analogix_dp_init_video(struct analogix_dp_device *dp)
@@ -1061,19 +1061,19 @@ void analogix_dp_init_video(struct analogix_dp_device *dp)
 	u32 reg;
 
 	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1);
 
 	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
 
 	reg = CHA_CRI(4) | CHA_CTRL;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
 
 	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 
 	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8);
 }
 
 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
@@ -1084,36 +1084,36 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
 	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
 		(dp->video_info->color_depth << IN_BPC_SHIFT) |
 		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
 	reg &= ~IN_YC_COEFFI_MASK;
 	if (dp->video_info->ycbcr_coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
 }
 
 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
 
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1);
 
 	if (!(reg & DET_STA)) {
 		dev_dbg(dp->dev, "Input stream clock not detected.\n");
 		return -EINVAL;
 	}
 
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
 
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2);
 	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
 
 	if (reg & CHA_STA) {
@@ -1132,30 +1132,30 @@ void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
 	u32 reg;
 
 	if (type == REGISTER_M) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 		reg |= FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 		reg = m_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0);
 		reg = (m_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1);
 		reg = (m_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
+		writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2);
 
 		reg = n_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0);
 		reg = (n_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1);
 		reg = (n_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
+		writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2);
 	} else  {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 		reg &= ~FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4);
 
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
-		writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0);
+		writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1);
+		writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2);
 	}
 }
 
@@ -1164,13 +1164,13 @@ void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
 	u32 reg;
 
 	if (type == VIDEO_TIMING_FROM_CAPTURE) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 		reg &= ~FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+		reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 		reg |= FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+		writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	}
 }
 
@@ -1179,15 +1179,15 @@ void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
 	u32 reg;
 
 	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
 		reg &= ~VIDEO_MODE_MASK;
 		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
 	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
+		reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
 		reg &= ~VIDEO_MODE_MASK;
 		reg |= VIDEO_MODE_SLAVE_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
+		writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
 	}
 }
 
@@ -1195,19 +1195,19 @@ void analogix_dp_start_video(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
 	reg |= VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1);
 }
 
 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 	if (!(reg & STRM_VALID)) {
 		dev_dbg(dp->dev, "Input video stream is not detected.\n");
 		return -EINVAL;
@@ -1220,44 +1220,44 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
+	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
 	reg |= MASTER_VID_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
+	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~INTERACE_SCAN_CFG;
 	reg |= (dp->video_info->interlaced << 2);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~VSYNC_POLARITY_CFG;
 	reg |= (dp->video_info->v_sync_polarity << 1);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~HSYNC_POLARITY_CFG;
 	reg |= (dp->video_info->h_sync_polarity << 0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-	writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL);
 }
 
 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 	reg &= ~SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 }
 
 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
 {
 	u32 reg;
 
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+	reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 	reg |= SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+	writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET);
 }
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index b9661c9..738db4c 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -12,93 +12,93 @@
 #ifndef _ANALOGIX_DP_REG_H
 #define _ANALOGIX_DP_REG_H
 
-#define EXYNOS_DP_TX_SW_RESET			0x14
-#define EXYNOS_DP_FUNC_EN_1			0x18
-#define EXYNOS_DP_FUNC_EN_2			0x1C
-#define EXYNOS_DP_VIDEO_CTL_1			0x20
-#define EXYNOS_DP_VIDEO_CTL_2			0x24
-#define EXYNOS_DP_VIDEO_CTL_3			0x28
-
-#define EXYNOS_DP_VIDEO_CTL_8			0x3C
-#define EXYNOS_DP_VIDEO_CTL_10			0x44
-
-#define EXYNOS_DP_LANE_MAP			0x35C
-
-#define EXYNOS_DP_ANALOG_CTL_1			0x370
-#define EXYNOS_DP_ANALOG_CTL_2			0x374
-#define EXYNOS_DP_ANALOG_CTL_3			0x378
-#define EXYNOS_DP_PLL_FILTER_CTL_1		0x37C
-#define EXYNOS_DP_TX_AMP_TUNING_CTL		0x380
-
-#define EXYNOS_DP_AUX_HW_RETRY_CTL		0x390
-
-#define EXYNOS_DP_COMMON_INT_STA_1		0x3C4
-#define EXYNOS_DP_COMMON_INT_STA_2		0x3C8
-#define EXYNOS_DP_COMMON_INT_STA_3		0x3CC
-#define EXYNOS_DP_COMMON_INT_STA_4		0x3D0
-#define EXYNOS_DP_INT_STA			0x3DC
-#define EXYNOS_DP_COMMON_INT_MASK_1		0x3E0
-#define EXYNOS_DP_COMMON_INT_MASK_2		0x3E4
-#define EXYNOS_DP_COMMON_INT_MASK_3		0x3E8
-#define EXYNOS_DP_COMMON_INT_MASK_4		0x3EC
-#define EXYNOS_DP_INT_STA_MASK			0x3F8
-#define EXYNOS_DP_INT_CTL			0x3FC
-
-#define EXYNOS_DP_SYS_CTL_1			0x600
-#define EXYNOS_DP_SYS_CTL_2			0x604
-#define EXYNOS_DP_SYS_CTL_3			0x608
-#define EXYNOS_DP_SYS_CTL_4			0x60C
-
-#define EXYNOS_DP_PKT_SEND_CTL			0x640
-#define EXYNOS_DP_HDCP_CTL			0x648
-
-#define EXYNOS_DP_LINK_BW_SET			0x680
-#define EXYNOS_DP_LANE_COUNT_SET		0x684
-#define EXYNOS_DP_TRAINING_PTN_SET		0x688
-#define EXYNOS_DP_LN0_LINK_TRAINING_CTL		0x68C
-#define EXYNOS_DP_LN1_LINK_TRAINING_CTL		0x690
-#define EXYNOS_DP_LN2_LINK_TRAINING_CTL		0x694
-#define EXYNOS_DP_LN3_LINK_TRAINING_CTL		0x698
-
-#define EXYNOS_DP_DEBUG_CTL			0x6C0
-#define EXYNOS_DP_HPD_DEGLITCH_L		0x6C4
-#define EXYNOS_DP_HPD_DEGLITCH_H		0x6C8
-#define EXYNOS_DP_LINK_DEBUG_CTL		0x6E0
-
-#define EXYNOS_DP_M_VID_0			0x700
-#define EXYNOS_DP_M_VID_1			0x704
-#define EXYNOS_DP_M_VID_2			0x708
-#define EXYNOS_DP_N_VID_0			0x70C
-#define EXYNOS_DP_N_VID_1			0x710
-#define EXYNOS_DP_N_VID_2			0x714
-
-#define EXYNOS_DP_PLL_CTL			0x71C
-#define EXYNOS_DP_PHY_PD			0x720
-#define EXYNOS_DP_PHY_TEST			0x724
-
-#define EXYNOS_DP_VIDEO_FIFO_THRD		0x730
-#define EXYNOS_DP_AUDIO_MARGIN			0x73C
-
-#define EXYNOS_DP_M_VID_GEN_FILTER_TH		0x764
-#define EXYNOS_DP_M_AUD_GEN_FILTER_TH		0x778
-#define EXYNOS_DP_AUX_CH_STA			0x780
-#define EXYNOS_DP_AUX_CH_DEFER_CTL		0x788
-#define EXYNOS_DP_AUX_RX_COMM			0x78C
-#define EXYNOS_DP_BUFFER_DATA_CTL		0x790
-#define EXYNOS_DP_AUX_CH_CTL_1			0x794
-#define EXYNOS_DP_AUX_ADDR_7_0			0x798
-#define EXYNOS_DP_AUX_ADDR_15_8			0x79C
-#define EXYNOS_DP_AUX_ADDR_19_16		0x7A0
-#define EXYNOS_DP_AUX_CH_CTL_2			0x7A4
-
-#define EXYNOS_DP_BUF_DATA_0			0x7C0
-
-#define EXYNOS_DP_SOC_GENERAL_CTL		0x800
-
-/* EXYNOS_DP_TX_SW_RESET */
+#define ANALOGIX_DP_TX_SW_RESET			0x14
+#define ANALOGIX_DP_FUNC_EN_1			0x18
+#define ANALOGIX_DP_FUNC_EN_2			0x1C
+#define ANALOGIX_DP_VIDEO_CTL_1			0x20
+#define ANALOGIX_DP_VIDEO_CTL_2			0x24
+#define ANALOGIX_DP_VIDEO_CTL_3			0x28
+
+#define ANALOGIX_DP_VIDEO_CTL_8			0x3C
+#define ANALOGIX_DP_VIDEO_CTL_10		0x44
+
+#define ANALOGIX_DP_LANE_MAP			0x35C
+
+#define ANALOGIX_DP_ANALOG_CTL_1		0x370
+#define ANALOGIX_DP_ANALOG_CTL_2		0x374
+#define ANALOGIX_DP_ANALOG_CTL_3		0x378
+#define ANALOGIX_DP_PLL_FILTER_CTL_1		0x37C
+#define ANALOGIX_DP_TX_AMP_TUNING_CTL		0x380
+
+#define ANALOGIX_DP_AUX_HW_RETRY_CTL		0x390
+
+#define ANALOGIX_DP_COMMON_INT_STA_1		0x3C4
+#define ANALOGIX_DP_COMMON_INT_STA_2		0x3C8
+#define ANALOGIX_DP_COMMON_INT_STA_3		0x3CC
+#define ANALOGIX_DP_COMMON_INT_STA_4		0x3D0
+#define ANALOGIX_DP_INT_STA			0x3DC
+#define ANALOGIX_DP_COMMON_INT_MASK_1		0x3E0
+#define ANALOGIX_DP_COMMON_INT_MASK_2		0x3E4
+#define ANALOGIX_DP_COMMON_INT_MASK_3		0x3E8
+#define ANALOGIX_DP_COMMON_INT_MASK_4		0x3EC
+#define ANALOGIX_DP_INT_STA_MASK		0x3F8
+#define ANALOGIX_DP_INT_CTL			0x3FC
+
+#define ANALOGIX_DP_SYS_CTL_1			0x600
+#define ANALOGIX_DP_SYS_CTL_2			0x604
+#define ANALOGIX_DP_SYS_CTL_3			0x608
+#define ANALOGIX_DP_SYS_CTL_4			0x60C
+
+#define ANALOGIX_DP_PKT_SEND_CTL		0x640
+#define ANALOGIX_DP_HDCP_CTL			0x648
+
+#define ANALOGIX_DP_LINK_BW_SET			0x680
+#define ANALOGIX_DP_LANE_COUNT_SET		0x684
+#define ANALOGIX_DP_TRAINING_PTN_SET		0x688
+#define ANALOGIX_DP_LN0_LINK_TRAINING_CTL	0x68C
+#define ANALOGIX_DP_LN1_LINK_TRAINING_CTL	0x690
+#define ANALOGIX_DP_LN2_LINK_TRAINING_CTL	0x694
+#define ANALOGIX_DP_LN3_LINK_TRAINING_CTL	0x698
+
+#define ANALOGIX_DP_DEBUG_CTL			0x6C0
+#define ANALOGIX_DP_HPD_DEGLITCH_L		0x6C4
+#define ANALOGIX_DP_HPD_DEGLITCH_H		0x6C8
+#define ANALOGIX_DP_LINK_DEBUG_CTL		0x6E0
+
+#define ANALOGIX_DP_M_VID_0			0x700
+#define ANALOGIX_DP_M_VID_1			0x704
+#define ANALOGIX_DP_M_VID_2			0x708
+#define ANALOGIX_DP_N_VID_0			0x70C
+#define ANALOGIX_DP_N_VID_1			0x710
+#define ANALOGIX_DP_N_VID_2			0x714
+
+#define ANALOGIX_DP_PLL_CTL			0x71C
+#define ANALOGIX_DP_PHY_PD			0x720
+#define ANALOGIX_DP_PHY_TEST			0x724
+
+#define ANALOGIX_DP_VIDEO_FIFO_THRD		0x730
+#define ANALOGIX_DP_AUDIO_MARGIN		0x73C
+
+#define ANALOGIX_DP_M_VID_GEN_FILTER_TH		0x764
+#define ANALOGIX_DP_M_AUD_GEN_FILTER_TH		0x778
+#define ANALOGIX_DP_AUX_CH_STA			0x780
+#define ANALOGIX_DP_AUX_CH_DEFER_CTL		0x788
+#define ANALOGIX_DP_AUX_RX_COMM			0x78C
+#define ANALOGIX_DP_BUFFER_DATA_CTL		0x790
+#define ANALOGIX_DP_AUX_CH_CTL_1		0x794
+#define ANALOGIX_DP_AUX_ADDR_7_0		0x798
+#define ANALOGIX_DP_AUX_ADDR_15_8		0x79C
+#define ANALOGIX_DP_AUX_ADDR_19_16		0x7A0
+#define ANALOGIX_DP_AUX_CH_CTL_2		0x7A4
+
+#define ANALOGIX_DP_BUF_DATA_0			0x7C0
+
+#define ANALOGIX_DP_SOC_GENERAL_CTL		0x800
+
+/* ANALOGIX_DP_TX_SW_RESET */
 #define RESET_DP_TX				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_1 */
+/* ANALOGIX_DP_FUNC_EN_1 */
 #define MASTER_VID_FUNC_EN_N			(0x1 << 7)
 #define SLAVE_VID_FUNC_EN_N			(0x1 << 5)
 #define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
@@ -107,17 +107,17 @@
 #define CRC_FUNC_EN_N				(0x1 << 1)
 #define SW_FUNC_EN_N				(0x1 << 0)
 
-/* EXYNOS_DP_FUNC_EN_2 */
+/* ANALOGIX_DP_FUNC_EN_2 */
 #define SSC_FUNC_EN_N				(0x1 << 7)
 #define AUX_FUNC_EN_N				(0x1 << 2)
 #define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
 #define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define VIDEO_EN				(0x1 << 7)
 #define HDCP_VIDEO_MUTE				(0x1 << 6)
 
-/* EXYNOS_DP_VIDEO_CTL_1 */
+/* ANALOGIX_DP_VIDEO_CTL_1 */
 #define IN_D_RANGE_MASK				(0x1 << 7)
 #define IN_D_RANGE_SHIFT			(7)
 #define IN_D_RANGE_CEA				(0x1 << 7)
@@ -134,7 +134,7 @@
 #define IN_COLOR_F_YCBCR422			(0x1 << 0)
 #define IN_COLOR_F_RGB				(0x0 << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_3 */
+/* ANALOGIX_DP_VIDEO_CTL_3 */
 #define IN_YC_COEFFI_MASK			(0x1 << 7)
 #define IN_YC_COEFFI_SHIFT			(7)
 #define IN_YC_COEFFI_ITU709			(0x1 << 7)
@@ -144,17 +144,17 @@
 #define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
 #define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
 
-/* EXYNOS_DP_VIDEO_CTL_8 */
+/* ANALOGIX_DP_VIDEO_CTL_8 */
 #define VID_HRES_TH(x)				(((x) & 0xf) << 4)
 #define VID_VRES_TH(x)				(((x) & 0xf) << 0)
 
-/* EXYNOS_DP_VIDEO_CTL_10 */
+/* ANALOGIX_DP_VIDEO_CTL_10 */
 #define FORMAT_SEL				(0x1 << 4)
 #define INTERACE_SCAN_CFG			(0x1 << 2)
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
-/* EXYNOS_DP_LANE_MAP */
+/* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
 #define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
@@ -172,30 +172,30 @@
 #define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
 #define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_1 */
+/* ANALOGIX_DP_ANALOG_CTL_1 */
 #define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
 
-/* EXYNOS_DP_ANALOG_CTL_2 */
+/* ANALOGIX_DP_ANALOG_CTL_2 */
 #define SEL_24M					(0x1 << 3)
 #define TX_DVDD_BIT_1_0625V			(0x4 << 0)
 
-/* EXYNOS_DP_ANALOG_CTL_3 */
+/* ANALOGIX_DP_ANALOG_CTL_3 */
 #define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
 #define VCO_BIT_600_MICRO			(0x5 << 0)
 
-/* EXYNOS_DP_PLL_FILTER_CTL_1 */
+/* ANALOGIX_DP_PLL_FILTER_CTL_1 */
 #define PD_RING_OSC				(0x1 << 6)
 #define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
 #define TX_CUR1_2X				(0x1 << 2)
 #define TX_CUR_16_MA				(0x3 << 0)
 
-/* EXYNOS_DP_TX_AMP_TUNING_CTL */
+/* ANALOGIX_DP_TX_AMP_TUNING_CTL */
 #define CH3_AMP_400_MV				(0x0 << 24)
 #define CH2_AMP_400_MV				(0x0 << 16)
 #define CH1_AMP_400_MV				(0x0 << 8)
 #define CH0_AMP_400_MV				(0x0 << 0)
 
-/* EXYNOS_DP_AUX_HW_RETRY_CTL */
+/* ANALOGIX_DP_AUX_HW_RETRY_CTL */
 #define AUX_BIT_PERIOD_EXPECTED_DELAY(x)	(((x) & 0x7) << 8)
 #define AUX_HW_RETRY_INTERVAL_MASK		(0x3 << 3)
 #define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS	(0x0 << 3)
@@ -204,7 +204,7 @@
 #define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS	(0x3 << 3)
 #define AUX_HW_RETRY_COUNT_SEL(x)		(((x) & 0x7) << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_1 */
+/* ANALOGIX_DP_COMMON_INT_STA_1 */
 #define VSYNC_DET				(0x1 << 7)
 #define PLL_LOCK_CHG				(0x1 << 6)
 #define SPDIF_ERR				(0x1 << 5)
@@ -214,19 +214,19 @@
 #define VID_CLK_CHG				(0x1 << 1)
 #define SW_INT					(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_2 */
+/* ANALOGIX_DP_COMMON_INT_STA_2 */
 #define ENC_EN_CHG				(0x1 << 6)
 #define HW_BKSV_RDY				(0x1 << 3)
 #define HW_SHA_DONE				(0x1 << 2)
 #define HW_AUTH_STATE_CHG			(0x1 << 1)
 #define HW_AUTH_DONE				(0x1 << 0)
 
-/* EXYNOS_DP_COMMON_INT_STA_3 */
+/* ANALOGIX_DP_COMMON_INT_STA_3 */
 #define AFIFO_UNDER				(0x1 << 7)
 #define AFIFO_OVER				(0x1 << 6)
 #define R0_CHK_FLAG				(0x1 << 5)
 
-/* EXYNOS_DP_COMMON_INT_STA_4 */
+/* ANALOGIX_DP_COMMON_INT_STA_4 */
 #define PSR_ACTIVE				(0x1 << 7)
 #define PSR_INACTIVE				(0x1 << 6)
 #define SPDIF_BI_PHASE_ERR			(0x1 << 5)
@@ -234,29 +234,29 @@
 #define HPD_LOST				(0x1 << 1)
 #define PLUG					(0x1 << 0)
 
-/* EXYNOS_DP_INT_STA */
+/* ANALOGIX_DP_INT_STA */
 #define INT_HPD					(0x1 << 6)
 #define HW_TRAINING_FINISH			(0x1 << 5)
 #define RPLY_RECEIV				(0x1 << 1)
 #define AUX_ERR					(0x1 << 0)
 
-/* EXYNOS_DP_INT_CTL */
+/* ANALOGIX_DP_INT_CTL */
 #define SOFT_INT_CTRL				(0x1 << 2)
 #define INT_POL1				(0x1 << 1)
 #define INT_POL0				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_1 */
+/* ANALOGIX_DP_SYS_CTL_1 */
 #define DET_STA					(0x1 << 2)
 #define FORCE_DET				(0x1 << 1)
 #define DET_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_2 */
+/* ANALOGIX_DP_SYS_CTL_2 */
 #define CHA_CRI(x)				(((x) & 0xf) << 4)
 #define CHA_STA					(0x1 << 2)
 #define FORCE_CHA				(0x1 << 1)
 #define CHA_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_3 */
+/* ANALOGIX_DP_SYS_CTL_3 */
 #define HPD_STATUS				(0x1 << 6)
 #define F_HPD					(0x1 << 5)
 #define HPD_CTRL				(0x1 << 4)
@@ -265,13 +265,13 @@
 #define F_VALID					(0x1 << 1)
 #define VALID_CTRL				(0x1 << 0)
 
-/* EXYNOS_DP_SYS_CTL_4 */
+/* ANALOGIX_DP_SYS_CTL_4 */
 #define FIX_M_AUD				(0x1 << 4)
 #define ENHANCED				(0x1 << 3)
 #define FIX_M_VID				(0x1 << 2)
 #define M_VID_UPDATE_CTRL			(0x3 << 0)
 
-/* EXYNOS_DP_TRAINING_PTN_SET */
+/* ANALOGIX_DP_TRAINING_PTN_SET */
 #define SCRAMBLER_TYPE				(0x1 << 9)
 #define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
 #define SCRAMBLING_DISABLE			(0x1 << 5)
@@ -285,24 +285,24 @@
 #define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
 #define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
 
-/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+/* ANALOGIX_DP_LN0_LINK_TRAINING_CTL */
 #define PRE_EMPHASIS_SET_MASK			(0x3 << 3)
 #define PRE_EMPHASIS_SET_SHIFT			(3)
 
-/* EXYNOS_DP_DEBUG_CTL */
+/* ANALOGIX_DP_DEBUG_CTL */
 #define PLL_LOCK				(0x1 << 4)
 #define F_PLL_LOCK				(0x1 << 3)
 #define PLL_LOCK_CTRL				(0x1 << 2)
 #define PN_INV					(0x1 << 0)
 
-/* EXYNOS_DP_PLL_CTL */
+/* ANALOGIX_DP_PLL_CTL */
 #define DP_PLL_PD				(0x1 << 7)
 #define DP_PLL_RESET				(0x1 << 6)
 #define DP_PLL_LOOP_BIT_DEFAULT			(0x1 << 4)
 #define DP_PLL_REF_BIT_1_1250V			(0x5 << 0)
 #define DP_PLL_REF_BIT_1_2500V			(0x7 << 0)
 
-/* EXYNOS_DP_PHY_PD */
+/* ANALOGIX_DP_PHY_PD */
 #define DP_PHY_PD				(0x1 << 5)
 #define AUX_PD					(0x1 << 4)
 #define CH3_PD					(0x1 << 3)
@@ -310,28 +310,28 @@
 #define CH1_PD					(0x1 << 1)
 #define CH0_PD					(0x1 << 0)
 
-/* EXYNOS_DP_PHY_TEST */
+/* ANALOGIX_DP_PHY_TEST */
 #define MACRO_RST				(0x1 << 5)
 #define CH1_TEST				(0x1 << 1)
 #define CH0_TEST				(0x1 << 0)
 
-/* EXYNOS_DP_AUX_CH_STA */
+/* ANALOGIX_DP_AUX_CH_STA */
 #define AUX_BUSY				(0x1 << 4)
 #define AUX_STATUS_MASK				(0xf << 0)
 
-/* EXYNOS_DP_AUX_CH_DEFER_CTL */
+/* ANALOGIX_DP_AUX_CH_DEFER_CTL */
 #define DEFER_CTRL_EN				(0x1 << 7)
 #define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
 
-/* EXYNOS_DP_AUX_RX_COMM */
+/* ANALOGIX_DP_AUX_RX_COMM */
 #define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
 #define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
 
-/* EXYNOS_DP_BUFFER_DATA_CTL */
+/* ANALOGIX_DP_BUFFER_DATA_CTL */
 #define BUF_CLR					(0x1 << 7)
 #define BUF_DATA_COUNT(x)			(((x) & 0x1f) << 0)
 
-/* EXYNOS_DP_AUX_CH_CTL_1 */
+/* ANALOGIX_DP_AUX_CH_CTL_1 */
 #define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
 #define AUX_TX_COMM_MASK			(0xf << 0)
 #define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
@@ -340,20 +340,20 @@
 #define AUX_TX_COMM_WRITE			(0x0 << 0)
 #define AUX_TX_COMM_READ			(0x1 << 0)
 
-/* EXYNOS_DP_AUX_ADDR_7_0 */
+/* ANALOGIX_DP_AUX_ADDR_7_0 */
 #define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_15_8 */
+/* ANALOGIX_DP_AUX_ADDR_15_8 */
 #define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
 
-/* EXYNOS_DP_AUX_ADDR_19_16 */
+/* ANALOGIX_DP_AUX_ADDR_19_16 */
 #define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
 
-/* EXYNOS_DP_AUX_CH_CTL_2 */
+/* ANALOGIX_DP_AUX_CH_CTL_2 */
 #define ADDR_ONLY				(0x1 << 1)
 #define AUX_EN					(0x1 << 0)
 
-/* EXYNOS_DP_SOC_GENERAL_CTL */
+/* ANALOGIX_DP_SOC_GENERAL_CTL */
 #define AUDIO_MODE_SPDIF_MODE			(0x1 << 8)
 #define AUDIO_MODE_MASTER_MODE			(0x0 << 8)
 #define MASTER_VIDEO_INTERLACE_EN		(0x1 << 4)
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 04/17] drm: bridge: analogix/dp: fix some obvious code style
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (2 preceding siblings ...)
  2016-02-15 11:09 ` [PATCH v14 03/17] drm: bridge: analogix/dp: rename register constants Yakir Yang
@ 2016-02-15 11:09 ` Yakir Yang
  2016-03-17 21:48   ` Heiko Stübner
  2016-03-17 21:50   ` [PATCH v14.1 " Heiko Stübner
  2016-02-15 11:10 ` [PATCH v14 05/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
                   ` (15 subsequent siblings)
  19 siblings, 2 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:09 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12:
- Add the ack from Jingoo

Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
  from exynos_dp code, and rephrase reasonable commit message, and
  remove some controversial style (Krzysztof)
    -		analogix_dp_write_byte_to_dpcd(
    - 				dp, DP_TEST_RESPONSE,
    +		analogix_dp_write_byte_to_dpcd(dp,
    +				DP_TEST_RESPONSE,
				DP_TEST_EDID_CHECKSUM_WRITE);

Changes in v4: None
Changes in v3: None
Changes in v2:
- Improved commit message more readable, and avoid using some
  uncommon style like bellow: (Joe Preches)
    -  retval = exynos_dp_read_bytes_from_i2c(...
  				  ...);
    +  retval =
    +  exynos_dp_read_bytes_from_i2c(......);

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++++++++++-----------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  72 ++++++------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 124 ++++++++++----------
 drivers/gpu/drm/exynos/exynos_dp.c                 |   6 +-
 4 files changed, 166 insertions(+), 165 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 392c296..6901a6f 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -64,7 +64,7 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 
 	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
 			return -ETIMEDOUT;
 		}
@@ -101,8 +101,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
 	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-				EDID_EXTENSION_FLAG,
-				&extend_block);
+						EDID_EXTENSION_FLAG,
+						&extend_block);
 	if (retval)
 		return retval;
 
@@ -110,7 +110,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
+						I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -141,7 +142,7 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		}
 
 		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					&test_vector);
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
@@ -155,10 +156,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 		/* Read EDID data */
 		retval = analogix_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_HEADER_PATTERN,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_HEADER_PATTERN]);
+				I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
+				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -169,16 +168,13 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 			return -EIO;
 		}
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TEST_REQUEST,
-			&test_vector);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
+				DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
+				DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE);
 		}
 	}
 
@@ -193,8 +189,7 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
-				12, buf);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
 	if (retval)
 		return retval;
 
@@ -208,8 +203,9 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
-						bool enable)
+static void
+analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
+				       bool enable)
 {
 	u8 data;
 
@@ -217,11 +213,11 @@ static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp
 
 	if (enable)
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DP_LANE_COUNT_ENHANCED_FRAME_EN |
-			DPCD_LANE_COUNT_SET(data));
+					       DP_LANE_COUNT_ENHANCED_FRAME_EN |
+					       DPCD_LANE_COUNT_SET(data));
 	else
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DPCD_LANE_COUNT_SET(data));
+					       DPCD_LANE_COUNT_SET(data));
 }
 
 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
@@ -248,13 +244,13 @@ static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
 	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	analogix_dp_write_byte_to_dpcd(dp,
-		DP_TRAINING_PATTERN_SET,
-		DP_TRAINING_PATTERN_DISABLE);
+	analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+				       DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
-					int pre_emphasis, int lane)
+static void
+analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
+				       int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -294,8 +290,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
-				2, buf);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
 	if (retval)
 		return retval;
 
@@ -331,7 +326,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
 	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, buf);
+						 lane_count, buf);
 
 	return retval;
 }
@@ -339,7 +334,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = link_status[lane>>1];
+	u8 link_value = link_status[lane >> 1];
 
 	return (link_value >> shift) & 0xf;
 }
@@ -358,7 +353,7 @@ static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 }
 
 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				int lane_count)
+				     int lane_count)
 {
 	int lane;
 	u8 lane_status;
@@ -376,11 +371,11 @@ static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							int lane)
+static unsigned char
+analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return (link_value >> shift) & 0x3;
 }
@@ -390,13 +385,13 @@ static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
-					u8 training_lane_set, int lane)
+					       u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -416,9 +411,9 @@ static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 	}
 }
 
-static unsigned int analogix_dp_get_lane_link_training(
-				struct analogix_dp_device *dp,
-				int lane)
+static unsigned int
+analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
+				   int lane)
 {
 	u32 reg;
 
@@ -452,7 +447,7 @@ static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
-					u8 adjust_request[2])
+						 u8 adjust_request[2])
 {
 	int lane, lane_count;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -625,7 +620,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
-					u8 *bandwidth)
+					     u8 *bandwidth)
 {
 	u8 data;
 
@@ -638,7 +633,7 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
-					u8 *lane_count)
+					      u8 *lane_count)
 {
 	u8 data;
 
@@ -651,8 +646,8 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_init_training(struct analogix_dp_device *dp,
-			enum link_lane_count_type max_lane,
-			enum link_rate_type max_rate)
+				      enum link_lane_count_type max_lane,
+				      enum link_rate_type max_rate)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
@@ -665,7 +660,7 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -725,8 +720,7 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 }
 
 static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
-				u32 count,
-				u32 bwtype)
+				      u32 count, u32 bwtype)
 {
 	int i;
 	int retval;
@@ -762,7 +756,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		timeout_loop++;
 		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -793,7 +787,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		} else if (done_count) {
 			done_count = 0;
 		}
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -807,25 +801,24 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
+					bool enable)
 {
 	u8 data;
 
 	if (enable) {
 		analogix_dp_enable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
 		analogix_dp_disable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
@@ -898,7 +891,7 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	}
 
 	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					dp->video_info->link_rate);
+					 dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1130,8 +1123,8 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
 
-	dp_video_config = devm_kzalloc(dev,
-				sizeof(*dp_video_config), GFP_KERNEL);
+	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
+				       GFP_KERNEL);
 	if (!dp_video_config)
 		return ERR_PTR(-ENOMEM);
 
@@ -1145,37 +1138,37 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 		of_property_read_bool(dp_node, "interlaced");
 
 	if (of_property_read_u32(dp_node, "samsung,color-space",
-				&dp_video_config->color_space)) {
+				 &dp_video_config->color_space)) {
 		dev_err(dev, "failed to get color-space\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				&dp_video_config->dynamic_range)) {
+				 &dp_video_config->dynamic_range)) {
 		dev_err(dev, "failed to get dynamic-range\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				&dp_video_config->ycbcr_coeff)) {
+				 &dp_video_config->ycbcr_coeff)) {
 		dev_err(dev, "failed to get ycbcr-coeff\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				&dp_video_config->color_depth)) {
+				 &dp_video_config->color_depth)) {
 		dev_err(dev, "failed to get color-depth\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				&dp_video_config->link_rate)) {
+				 &dp_video_config->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				&dp_video_config->lane_count)) {
+				 &dp_video_config->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
 		return ERR_PTR(-EINVAL);
 	}
@@ -1284,7 +1277,7 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	pm_runtime_enable(dev);
 
 	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
-			irq_flags, "analogix-dp", dp);
+			       irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		goto err_disable_pm_runtime;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 0fff745..d4c4ae2 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -187,50 +187,55 @@ int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
+				   unsigned int reg_addr,
+				   unsigned char data);
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
+				    unsigned int reg_addr,
+				    unsigned char *data);
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[]);
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[]);
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
+				  unsigned int device_addr,
+				  unsigned int reg_addr);
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data);
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[]);
 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable);
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern);
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+				      enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
@@ -241,11 +246,12 @@ void analogix_dp_init_video(struct analogix_dp_device *dp);
 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value,
+				 u32 n_value);
 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
-void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
+				     bool enable);
 void analogix_dp_start_video(struct analogix_dp_device *dp);
 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 442cc66..a388c0a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -54,10 +54,10 @@ void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
 
 	if (enable)
 		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+		      LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
 	else
 		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+		      LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
 
 	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
 }
@@ -202,8 +202,8 @@ void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
 }
 
 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
+				       enum analog_power_block block,
+				       bool enable)
 {
 	u32 reg;
 
@@ -399,8 +399,8 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
+	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
@@ -483,8 +483,8 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
 }
 
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
+				   unsigned int reg_addr,
+				   unsigned char data)
 {
 	u32 reg;
 	int i;
@@ -519,17 +519,16 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	return retval;
 }
 
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
+				    unsigned int reg_addr,
+				    unsigned char *data)
 {
 	u32 reg;
 	int i;
@@ -560,9 +559,8 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data buffer */
@@ -573,9 +571,9 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -608,8 +606,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 			     cur_data_idx++) {
 				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
+				writel(reg, dp->reg_base +
+				       ANALOGIX_DP_BUF_DATA_0 +
+				       4 * cur_data_idx);
 			}
 
 			/*
@@ -625,9 +624,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		start_offset += cur_data_count;
@@ -637,9 +636,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -683,9 +682,9 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
@@ -703,8 +702,8 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
+				  unsigned int device_addr,
+				  unsigned int reg_addr)
 {
 	u32 reg;
 	int retval;
@@ -736,9 +735,9 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data)
 {
 	u32 reg;
 	int i;
@@ -750,7 +749,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 		/* Select EDID device */
-		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+		retval = analogix_dp_select_i2c_device(dp, device_addr,
+						       reg_addr);
 		if (retval != 0)
 			continue;
 
@@ -767,9 +767,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data */
@@ -780,10 +779,10 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[])
 {
 	u32 reg;
 	unsigned int i, j;
@@ -828,15 +827,14 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 				retval = analogix_dp_start_aux_transaction(dp);
 				if (retval == 0)
 					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
+
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
 			}
 			/* Check if Rx sends defer */
 			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
 			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
+			    reg == AUX_RX_COMM_I2C_DEFER) {
 				dev_err(dp->dev, "Defer: %d\n\n", reg);
 				defer = 1;
 			}
@@ -885,7 +883,8 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
 	*count = reg;
 }
 
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable)
 {
 	u32 reg;
 
@@ -901,7 +900,7 @@ void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable
 }
 
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern)
+				      enum pattern_set pattern)
 {
 	u32 reg;
 
@@ -933,7 +932,8 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
 	}
 }
 
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -943,7 +943,8 @@ void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -953,7 +954,8 @@ void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -963,7 +965,8 @@ void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -974,7 +977,7 @@ void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level
 }
 
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -983,7 +986,7 @@ void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1001,7 +1004,7 @@ void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1125,9 +1128,8 @@ int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
 }
 
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value, u32 n_value)
 {
 	u32 reg;
 
@@ -1221,7 +1223,7 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 	u32 reg;
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
 	reg |= MASTER_VID_FUNC_EN_N;
 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
index c6519b9..7650b2b 100644
--- a/drivers/gpu/drm/exynos/exynos_dp.c
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -157,7 +157,7 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
 	int ret;
 
 	ret = of_get_videomode(dp->dev->of_node, &dp->priv.vm,
-			OF_USE_NATIVE_MODE);
+			       OF_USE_NATIVE_MODE);
 	if (ret) {
 		DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
 		return ret;
@@ -214,7 +214,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 }
 
 static void exynos_dp_unbind(struct device *dev, struct device *master,
-				void *data)
+			     void *data)
 {
 	return analogix_dp_unbind(dev, master, data);
 }
@@ -231,7 +231,7 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	struct exynos_dp_device *dp;
 
 	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
-				GFP_KERNEL);
+			  GFP_KERNEL);
 	if (!dp)
 		return -ENOMEM;
 
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 05/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (3 preceding siblings ...)
  2016-02-15 11:09 ` [PATCH v14 04/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
@ 2016-02-15 11:10 ` Yakir Yang
  2016-02-15 11:10 ` [PATCH v14 06/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
                   ` (14 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:10 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.

Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12:
- Remove the enum link_rate_type struct, using the marcos in drm_dp_helper.h (Jingoo)

Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04

Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
  directly, but we can take those as hardware limite. For example, RK3288
  only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
  like "link-rate = 0x0a" "lane-count = 4". (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 14 +++++++-------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  7 +------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  2 +-
 3 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 6901a6f..b948636 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -627,6 +627,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 	/*
 	 * For DP rev.1.1, Maximum link rate of Main Link lanes
 	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+	 * For DP rev.1.2, Maximum link rate of Main Link lanes
+	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
 	 */
 	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
 	*bandwidth = data;
@@ -647,7 +649,7 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 
 static void analogix_dp_init_training(struct analogix_dp_device *dp,
 				      enum link_lane_count_type max_lane,
-				      enum link_rate_type max_rate)
+				      int max_rate)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
@@ -659,11 +661,12 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
-	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	if ((dp->link_train.link_rate != DP_LINK_BW_1_62) &&
+	    (dp->link_train.link_rate != DP_LINK_BW_2_7) &&
+	    (dp->link_train.link_rate != DP_LINK_BW_5_4)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
-		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
+		dp->link_train.link_rate = DP_LINK_BW_1_62;
 	}
 
 	if (dp->link_train.lane_count == 0) {
@@ -901,9 +904,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
 	analogix_dp_enable_enhanced_mode(dp, 1);
 
-	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
-	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
 	analogix_dp_init_video(dp);
 	ret = analogix_dp_config_video(dp);
 	if (ret)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index d4c4ae2..afb0a53 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,11 +20,6 @@
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
 
-enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
-};
-
 enum link_lane_count_type {
 	LANE_COUNT1 = 1,
 	LANE_COUNT2 = 2,
@@ -128,7 +123,7 @@ struct video_info {
 	enum color_coefficient ycbcr_coeff;
 	enum color_depth color_depth;
 
-	enum link_rate_type link_rate;
+	int link_rate;
 	enum link_lane_count_type lane_count;
 };
 
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index a388c0a..eb0b63c 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -855,7 +855,7 @@ void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
 	u32 reg;
 
 	reg = bwtype;
-	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
+	if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62))
 		writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET);
 }
 
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 06/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (4 preceding siblings ...)
  2016-02-15 11:10 ` [PATCH v14 05/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
@ 2016-02-15 11:10 ` Yakir Yang
  2016-02-15 11:10 ` [PATCH v14 07/17] dt-bindings: add document for analogix display port driver Yakir Yang
                   ` (13 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:10 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.

But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
  compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
  to avoid -EOVERFLOW error (Krzysztof)

Changes in v6: None
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
  to get the backword timing values. Krzysztof suggest me that driver could use
  the "of_property_read_bool" to get backword timing values, but that interfacs
  would modify the original drm_display_mode timing directly (whether those
  properties exists or not).

Changes in v4:
- Provide backword compatibility with samsung. (Krzysztof)

Changes in v3:
- Dynamic parse video timing info from struct drm_display_mode and
  struct drm_display_info. (Thierry)

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |   2 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  14 +-
 3 files changed, 103 insertions(+), 61 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index b948636..26359f4 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -893,8 +893,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					 dp->video_info->link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
+					 dp->video_info.link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1077,6 +1077,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
 }
 
+static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
+					struct drm_display_mode *orig_mode,
+					struct drm_display_mode *mode)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_display_info *display_info = &dp->connector.display_info;
+	struct video_info *video = &dp->video_info;
+	struct device_node *dp_node = dp->dev->of_node;
+	int vic;
+
+	/* Input video interlaces & hsync pol & vsync pol */
+	video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+	video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+	video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+	/* Input video dynamic_range & colorimetry */
+	vic = drm_match_cea_mode(mode);
+	if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
+	    (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR601;
+	} else if (vic) {
+		video->dynamic_range = CEA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	} else {
+		video->dynamic_range = VESA;
+		video->ycbcr_coeff = COLOR_YCBCR709;
+	}
+
+	/* Input vide bpc and color_formats */
+	switch (display_info->bpc) {
+	case 12:
+		video->color_depth = COLOR_12;
+		break;
+	case 10:
+		video->color_depth = COLOR_10;
+		break;
+	case 8:
+		video->color_depth = COLOR_8;
+		break;
+	case 6:
+		video->color_depth = COLOR_6;
+		break;
+	default:
+		video->color_depth = COLOR_8;
+		break;
+	}
+	if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
+		video->color_space = COLOR_YCBCR444;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
+		video->color_space = COLOR_YCBCR422;
+	else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
+		video->color_space = COLOR_RGB;
+	else
+		video->color_space = COLOR_RGB;
+
+	/*
+	 * NOTE: those property parsing code is used for providing backward
+	 * compatibility for samsung platform.
+	 * Due to we used the "of_property_read_u32" interfaces, when this
+	 * property isn't present, the "video_info" can keep the original
+	 * values and wouldn't be modified.
+	 */
+	of_property_read_u32(dp_node, "samsung,color-space",
+			     &video->color_space);
+	of_property_read_u32(dp_node, "samsung,dynamic-range",
+			     &video->dynamic_range);
+	of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+			     &video->ycbcr_coeff);
+	of_property_read_u32(dp_node, "samsung,color-depth",
+			     &video->color_depth);
+	if (of_property_read_bool(dp_node, "hsync-active-high"))
+		video->h_sync_polarity = true;
+	if (of_property_read_bool(dp_node, "vsync-active-high"))
+		video->v_sync_polarity = true;
+	if (of_property_read_bool(dp_node, "interlaced"))
+		video->interlaced = true;
+}
+
 static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
 {
 	/* do nothing */
@@ -1087,6 +1166,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
 	.disable = analogix_dp_bridge_disable,
 	.pre_enable = analogix_dp_bridge_nop,
 	.post_disable = analogix_dp_bridge_nop,
+	.mode_set = analogix_dp_bridge_mode_set,
 	.attach = analogix_dp_bridge_attach,
 };
 
@@ -1118,62 +1198,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
 	return 0;
 }
 
-static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 {
-	struct device_node *dp_node = dev->of_node;
-	struct video_info *dp_video_config;
-
-	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
-				       GFP_KERNEL);
-	if (!dp_video_config)
-		return ERR_PTR(-ENOMEM);
-
-	dp_video_config->h_sync_polarity =
-		of_property_read_bool(dp_node, "hsync-active-high");
-
-	dp_video_config->v_sync_polarity =
-		of_property_read_bool(dp_node, "vsync-active-high");
-
-	dp_video_config->interlaced =
-		of_property_read_bool(dp_node, "interlaced");
-
-	if (of_property_read_u32(dp_node, "samsung,color-space",
-				 &dp_video_config->color_space)) {
-		dev_err(dev, "failed to get color-space\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				 &dp_video_config->dynamic_range)) {
-		dev_err(dev, "failed to get dynamic-range\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				 &dp_video_config->ycbcr_coeff)) {
-		dev_err(dev, "failed to get ycbcr-coeff\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				 &dp_video_config->color_depth)) {
-		dev_err(dev, "failed to get color-depth\n");
-		return ERR_PTR(-EINVAL);
-	}
+	struct device_node *dp_node = dp->dev->of_node;
+	struct video_info *video_info = &dp->video_info;
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &dp_video_config->link_rate)) {
-		dev_err(dev, "failed to get link-rate\n");
-		return ERR_PTR(-EINVAL);
+				 &video_info->link_rate)) {
+		dev_err(dp->dev, "failed to get link-rate\n");
+		return -EINVAL;
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &dp_video_config->lane_count)) {
-		dev_err(dev, "failed to get lane-count\n");
-		return ERR_PTR(-EINVAL);
+				 &video_info->lane_count)) {
+		dev_err(dp->dev, "failed to get lane-count\n");
+		return -EINVAL;
 	}
 
-	return dp_video_config;
+	return 0;
 }
 
 int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
@@ -1206,9 +1248,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	 */
 	dp->plat_data = plat_data;
 
-	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
-	if (IS_ERR(dp->video_info))
-		return PTR_ERR(dp->video_info);
+	ret = analogix_dp_dt_parse_pdata(dp);
+	if (ret)
+		return ret;
 
 	dp->phy = devm_phy_get(dp->dev, "dp");
 	if (IS_ERR(dp->phy)) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index afb0a53..123030f 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -148,7 +148,7 @@ struct analogix_dp_device {
 	unsigned int		irq;
 	void __iomem		*reg_base;
 
-	struct video_info	*video_info;
+	struct video_info	video_info;
 	struct link_train	link_train;
 	struct work_struct	hotplug_work;
 	struct phy		*phy;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index eb0b63c..3858df5 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
 	u32 reg;
 
 	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info.color_depth << IN_BPC_SHIFT) |
+		(dp->video_info.color_space << IN_COLOR_F_SHIFT);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
 
 	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
 	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
+	if (dp->video_info.ycbcr_coeff)
 		reg |= IN_YC_COEFFI_ITU709;
 	else
 		reg |= IN_YC_COEFFI_ITU601;
@@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
+	reg |= (dp->video_info.interlaced << 2);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
+	reg |= (dp->video_info.v_sync_polarity << 1);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
+	reg |= (dp->video_info.h_sync_polarity << 0);
 	writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
 
 	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 07/17] dt-bindings: add document for analogix display port driver
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (5 preceding siblings ...)
  2016-02-15 11:10 ` [PATCH v14 06/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
@ 2016-02-15 11:10 ` Yakir Yang
  2016-02-15 11:10 ` [PATCH v14 08/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
                   ` (12 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:10 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt

Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10:
- Add the ack from Rob Herring

Changes in v9: None
Changes in v8:
- Correct the right document path of display-timing.txt (Heiko)
- Correct the misspell of 'from' to 'frm'. (Heiko)

Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Split all DTS changes, and provide backward compatibility. Mark old
  properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
    "analogix,color-space" & "analogix,color-depth"   &
    "analogix,link-rate"   & "analogix,lane-count"    &
    "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
    "vsync-active-high"    & "hsync-active-high"      & "interlaces"

Changes in v3:
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
  devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.

Changes in v2: None

 .../bindings/display/bridge/analogix_dp.txt        | 50 ++++++++++++
 .../bindings/display/exynos/exynos_dp.txt          | 92 ++++++----------------
 2 files changed, 76 insertions(+), 66 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/bridge/analogix_dp.txt

diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
new file mode 100644
index 0000000..7659a7a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
@@ -0,0 +1,50 @@
+Analogix Display Port bridge bindings
+
+Required properties for dp-controller:
+	-compatible:
+		platform specific such as:
+		 * "samsung,exynos5-dp"
+		 * "rockchip,rk3288-dp"
+	-reg:
+		physical base address of the controller and length
+		of memory mapped region.
+	-interrupts:
+		interrupt combiner values.
+	-clocks:
+		from common clock binding: handle to dp clock.
+	-clock-names:
+		from common clock binding: Shall be "dp".
+	-interrupt-parent:
+		phandle to Interrupt combiner node.
+	-phys:
+		from general PHY binding: the phandle for the PHY device.
+	-phy-names:
+		from general PHY binding: Should be "dp".
+
+Optional properties for dp-controller:
+	-hpd-gpios:
+		Hotplug detect GPIO.
+		Indicates which GPIO should be used for hotplug detection
+	-port@[X]: SoC specific port nodes with endpoint definitions as defined
+		in Documentation/devicetree/bindings/media/video-interfaces.txt,
+		please refer to the SoC specific binding document:
+		* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+-------------------------------------------------------------------------------
+
+Example:
+
+	dp-controller {
+		compatible = "samsung,exynos5-dp";
+		reg = <0x145b0000 0x10000>;
+		interrupts = <10 3>;
+		interrupt-parent = <&combiner>;
+		clocks = <&clock 342>;
+		clock-names = "dp";
+
+		phys = <&dp_phy>;
+		phy-names = "dp";
+	};
diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
index fe4a7a2..4fa8aca 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
@@ -1,20 +1,3 @@
-Device-Tree bindings for Samsung Exynos Embedded DisplayPort Transmitter(eDP)
-
-DisplayPort is industry standard to accommodate the growing board adoption
-of digital display technology within the PC and CE industries.
-It consolidates the internal and external connection methods to reduce device
-complexity and cost. It also supports necessary features for important cross
-industry applications and provides performance scalability to enable the next
-generation of displays that feature higher color depths, refresh rates, and
-display resolutions.
-
-eDP (embedded display port) device is compliant with Embedded DisplayPort
-standard as follows,
-- DisplayPort standard 1.1a for Exynos5250 and Exynos5260.
-- DisplayPort standard 1.3 for Exynos5422s and Exynos5800.
-
-eDP resides between FIMD and panel or FIMD and bridge such as LVDS.
-
 The Exynos display port interface should be configured based on
 the type of panel connected to it.
 
@@ -48,26 +31,6 @@ Required properties for dp-controller:
 		from general PHY binding: the phandle for the PHY device.
 	-phy-names:
 		from general PHY binding: Should be "dp".
-	-samsung,color-space:
-		input video data format.
-			COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
-	-samsung,dynamic-range:
-		dynamic range for input video data.
-			VESA = 0, CEA = 1
-	-samsung,ycbcr-coeff:
-		YCbCr co-efficients for input video.
-			COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
-	-samsung,color-depth:
-		number of bits per colour component.
-			COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
-	-samsung,link-rate:
-		link rate supported by the panel.
-			LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
-	-samsung,lane-count:
-		number of lanes supported by the panel.
-			LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
-	- display-timings: timings for the connected panel as described by
-		Documentation/devicetree/bindings/display/display-timing.txt
 
 Optional properties for dp-controller:
 	-interlaced:
@@ -83,17 +46,30 @@ Optional properties for dp-controller:
 		Hotplug detect GPIO.
 			Indicates which GPIO should be used for hotplug
 			detection
-Video interfaces:
-  Device node can contain video interface port nodes according to [1].
-  The following are properties specific to those nodes:
-
-  endpoint node connected to bridge or panel node:
-   - remote-endpoint: specifies the endpoint in panel or bridge node.
-		      This node is required in all kinds of exynos dp
-		      to represent the connection between dp and bridge
-		      or dp and panel.
-
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+	-video interfaces: Device node can contain video interface port
+			nodes according to [1].
+	- display-timings: timings for the connected panel as described by
+		Documentation/devicetree/bindings/display/panel/display-timing.txt
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
+	-phys (required)
+	-phy-names (required)
+	-hpd-gpios (optional)
+
+Deprecated properties for DisplayPort:
+-interlaced:            deprecated prop that can parsed from drm_display_mode.
+-vsync-active-high:     deprecated prop that can parsed from drm_display_mode.
+-hsync-active-high:     deprecated prop that can parsed from drm_display_mode.
+-samsung,ycbcr-coeff:   deprecated prop that can parsed from drm_display_mode.
+-samsung,dynamic-range: deprecated prop that can parsed from drm_display_mode.
+-samsung,color-space:   deprecated prop that can parsed from drm_display_info.
+-samsung,color-depth:   deprecated prop that can parsed from drm_display_info.
+-samsung,link-rate:     deprecated prop that can reading from monitor by dpcd method.
+-samsung,lane-count:    deprecated prop that can reading from monitor by dpcd method.
+-samsung,hpd-gpio:      deprecated name for hpd-gpios.
+
+-------------------------------------------------------------------------------
 
 Example:
 
@@ -112,13 +88,6 @@ SOC specific portion:
 
 Board Specific portion:
 	dp-controller {
-		samsung,color-space = <0>;
-		samsung,dynamic-range = <0>;
-		samsung,ycbcr-coeff = <0>;
-		samsung,color-depth = <1>;
-		samsung,link-rate = <0x0a>;
-		samsung,lane-count = <4>;
-
 		display-timings {
 			native-mode = <&lcd_timing>;
 			lcd_timing: 1366x768 {
@@ -135,18 +104,9 @@ Board Specific portion:
 		};
 
 		ports {
-			port {
+			port@0 {
 				dp_out: endpoint {
-					remote-endpoint = <&dp_in>;
-				};
-			};
-		};
-
-		panel {
-			...
-			port {
-				dp_in: endpoint {
-					remote-endpoint = <&dp_out>;
+					remote-endpoint = <&bridge_in>;
 				};
 			};
 		};
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 08/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (6 preceding siblings ...)
  2016-02-15 11:10 ` [PATCH v14 07/17] dt-bindings: add document for analogix display port driver Yakir Yang
@ 2016-02-15 11:10 ` Yakir Yang
  2016-02-15 11:10 ` [PATCH v14 09/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
                   ` (11 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:10 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.

Beside the backward compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6:
- Fix Peach Pit hpd property name error:
-       hpd-gpio = <&gpx2 6 0>;
+       hpd-gpios = <&gpx2 6 0>;

Changes in v5:
- Correct the misspell in commit message. (Krzysztof)

Changes in v4:
- Separate all DTS changes to a separate patch. (Krzysztof)

Changes in v3: None
Changes in v2: None

 arch/arm/boot/dts/exynos5250-arndale.dts      | 2 --
 arch/arm/boot/dts/exynos5250-smdk5250.dts     | 2 --
 arch/arm/boot/dts/exynos5250-snow-common.dtsi | 4 +---
 arch/arm/boot/dts/exynos5250-spring.dts       | 4 +---
 arch/arm/boot/dts/exynos5420-peach-pit.dts    | 4 +---
 arch/arm/boot/dts/exynos5420-smdk5420.dts     | 2 --
 arch/arm/boot/dts/exynos5800-peach-pi.dts     | 2 --
 7 files changed, 3 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index c000532..b1790cf 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -124,8 +124,6 @@
 &dp {
 	status = "okay";
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 0f5dcd4..f30c2db 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -80,8 +80,6 @@
 
 &dp {
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index 5cb33ba..b96624b 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -236,12 +236,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
 
 	ports {
 		port@0 {
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index c1edd6d..91881d7 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -74,12 +74,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <1>;
-	samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
 };
 
 &ehci {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 35cfb07..2f37c87 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -148,12 +148,10 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x06>;
 	samsung,lane-count = <2>;
-	samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+	hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
 
 	ports {
 		port@0 {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index ac35aef..f67344f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -93,8 +93,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 064176f..5d33fb2 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -148,8 +148,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&dp_hpd_gpio>;
 	samsung,color-space = <0>;
-	samsung,dynamic-range = <0>;
-	samsung,ycbcr-coeff = <0>;
 	samsung,color-depth = <1>;
 	samsung,link-rate = <0x0a>;
 	samsung,lane-count = <2>;
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 09/17] drm: rockchip: dp: add rockchip platform dp driver
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (7 preceding siblings ...)
  2016-02-15 11:10 ` [PATCH v14 08/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
@ 2016-02-15 11:10 ` Yakir Yang
  2016-03-17 21:51   ` [PATCH v14.1 " Heiko Stübner
  2016-03-23  1:08   ` [PATCH v14 " Mark yao
  2016-02-15 11:10 ` [PATCH v14 10/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
                   ` (10 subsequent siblings)
  19 siblings, 2 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:10 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v14: None
Changes in v13:
- Use .enable instead of preprare/commit in encoder_helper_funcs (Heiko)
- Fix the missing parameters with drm_encoder_init() helper function. (Heiko)

Changes in v12: None
Changes in v11: None
Changes in v10:
- Correct the ROCKCHIP_ANALOGIX_DP indentation in Kconfig to tabs here (Heiko)

Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
  numbers in the example DT node, and remove the regulator iomux setting
  in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
  support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)

Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.

Changes in v3:
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
  and leave "sclk_edp" to analogix dp core driver which name to "dp",
  and leave "pclk_edp" to rockchip dp platform driver which name to
  "pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
  node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.

Changes in v2:
- Get panel node with remote-endpoint method, and create devicetree binding
  for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.

 drivers/gpu/drm/rockchip/Kconfig                |   9 +
 drivers/gpu/drm/rockchip/Makefile               |   1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 384 ++++++++++++++++++++++++
 include/drm/bridge/analogix_dp.h                |   1 +
 4 files changed, 395 insertions(+)
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 8573985..9fe4e32 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -35,3 +35,12 @@ config ROCKCHIP_DW_MIPI_DSI
 	 for the Synopsys DesignWare HDMI driver. If you want to
 	 enable MIPI DSI on RK3288 based SoC, you should selet this
 	 option.
+
+config ROCKCHIP_ANALOGIX_DP
+	tristate "Rockchip specific extensions for Analogix DP driver"
+	depends on DRM_ROCKCHIP
+	select DRM_ANALOGIX_DP
+	help
+	  This selects support for Rockchip SoC specific extensions
+	  for the Analogix Core DP driver. If you want to enable DP
+	  on RK3288 based SoC, you should selet this option.
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index f6a809a..921fabf 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -8,5 +8,6 @@ rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
 
 obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
 obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
+obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 
 obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_vop_reg.o
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
new file mode 100644
index 0000000..b7af1b7
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -0,0 +1,384 @@
+/*
+ * Rockchip SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ *         Yakir Yang <ykk@rock-chips.com>
+ *         Jeff Chen <jeff.chen@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)
+
+/* dp grf register offset */
+#define GRF_SOC_CON6                            0x025c
+#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
+#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
+#define GRF_EDP_SEL_VOP_BIG                     0
+
+struct rockchip_dp_device {
+	struct drm_device        *drm_dev;
+	struct device            *dev;
+	struct drm_encoder       encoder;
+	struct drm_display_mode  mode;
+
+	struct clk               *pclk;
+	struct regmap            *grf;
+	struct reset_control     *rst;
+
+	struct analogix_dp_plat_data plat_data;
+};
+
+static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+{
+	reset_control_assert(dp->rst);
+	usleep_range(10, 20);
+	reset_control_deassert(dp->rst);
+
+	return 0;
+}
+
+static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+	int ret;
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+
+	clk_disable_unprepare(dp->pclk);
+
+	return 0;
+}
+
+static bool
+rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
+				   const struct drm_display_mode *mode,
+				   struct drm_display_mode *adjusted_mode)
+{
+	/* do nothing */
+	return true;
+}
+
+static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
+					     struct drm_display_mode *mode,
+					     struct drm_display_mode *adjusted)
+{
+	/* do nothing */
+}
+
+static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
+{
+	struct rockchip_dp_device *dp = to_dp(encoder);
+	int ret;
+	u32 val;
+
+	/*
+	 * FIXME(Yakir): driver should configure the CRTC output video
+	 * mode with the display information which indicated the monitor
+	 * support colorimetry.
+	 *
+	 * But don't know why the CRTC driver seems could only output the
+	 * RGBaaa rightly. For example, if connect the "innolux,n116bge"
+	 * eDP screen, EDID would indicated that screen only accepted the
+	 * 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
+	 * screen would show a blue picture (RGB888 show a green picture).
+	 * But if I configure CTRC to RGBaaa, and eDP driver still keep
+	 * RGB666 input video mode, then screen would works prefect.
+	 */
+	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					    DRM_MODE_CONNECTOR_eDP,
+					    ROCKCHIP_OUT_MODE_AAAA);
+	if (ret < 0) {
+		dev_err(dp->dev, "Could not set crtc mode config (%d)\n", ret);
+		return;
+	}
+
+	ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
+	if (ret < 0)
+		return;
+
+	if (ret)
+		val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
+	else
+		val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
+
+	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+		return;
+	}
+}
+
+static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
+{
+	/* do nothing */
+}
+
+static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
+	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
+	.mode_set = rockchip_dp_drm_encoder_mode_set,
+	.enable = rockchip_dp_drm_encoder_enable,
+	.disable = rockchip_dp_drm_encoder_nop,
+};
+
+static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
+	.destroy = rockchip_dp_drm_encoder_destroy,
+};
+
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+	struct device *dev = dp->dev;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "failed to get rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	dp->pclk = devm_clk_get(dev, "pclk");
+	if (IS_ERR(dp->pclk)) {
+		dev_err(dev, "failed to get pclk property\n");
+		return PTR_ERR(dp->pclk);
+	}
+
+	dp->rst = devm_reset_control_get(dev, "dp");
+	if (IS_ERR(dp->rst)) {
+		dev_err(dev, "failed to get dp reset control\n");
+		return PTR_ERR(dp->rst);
+	}
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
+{
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct device *dev = dp->dev;
+	int ret;
+
+	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+							     dev->of_node);
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
+			       DRM_MODE_ENCODER_TMDS, NULL);
+	if (ret) {
+		DRM_ERROR("failed to initialize encoder with drm\n");
+		return ret;
+	}
+
+	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
+
+	return 0;
+}
+
+static int rockchip_dp_bind(struct device *dev, struct device *master,
+			    void *data)
+{
+	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_device *drm_dev = data;
+	int ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	ret = rockchip_dp_init(dp);
+	if (ret < 0)
+		return ret;
+
+	dp->drm_dev = drm_dev;
+
+	ret = rockchip_dp_drm_create_encoder(dp);
+	if (ret) {
+		DRM_ERROR("failed to create drm encoder\n");
+		return ret;
+	}
+
+	dp->plat_data.encoder = &dp->encoder;
+
+	dp->plat_data.dev_type = RK3288_DP;
+	dp->plat_data.power_on = rockchip_dp_poweron;
+	dp->plat_data.power_off = rockchip_dp_powerdown;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
+}
+
+static void rockchip_dp_unbind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops rockchip_dp_component_ops = {
+	.bind = rockchip_dp_bind,
+	.unbind = rockchip_dp_unbind,
+};
+
+static int rockchip_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *port, *endpoint;
+	struct rockchip_dp_device *dp;
+	struct drm_panel *panel;
+
+	port = of_graph_get_port_by_id(dev->of_node, 1);
+	if (!port) {
+		dev_err(dev, "can't find output port\n");
+		return -EINVAL;
+	}
+
+	endpoint = of_get_child_by_name(port, "endpoint");
+	of_node_put(port);
+	if (!endpoint) {
+		dev_err(dev, "no output endpoint found\n");
+		return -EINVAL;
+	}
+
+	panel_node = of_graph_get_remote_port_parent(endpoint);
+	of_node_put(endpoint);
+	if (!panel_node) {
+		dev_err(dev, "no output node found\n");
+		return -EINVAL;
+	}
+
+	panel = of_drm_find_panel(panel_node);
+	if (!panel) {
+		DRM_ERROR("failed to find panel\n");
+		of_node_put(panel_node);
+		return -EPROBE_DEFER;
+	}
+
+	of_node_put(panel_node);
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->plat_data.panel = panel;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver could take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	return component_add(dev, &rockchip_dp_component_ops);
+}
+
+static int rockchip_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &rockchip_dp_component_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int rockchip_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops rockchip_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
+};
+
+static const struct of_device_id rockchip_dp_dt_ids[] = {
+	{.compatible = "rockchip,rk3288-dp",},
+	{}
+};
+MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
+
+static struct platform_driver rockchip_dp_driver = {
+	.probe = rockchip_dp_probe,
+	.remove = rockchip_dp_remove,
+	.driver = {
+		   .name = "rockchip-dp",
+		   .owner = THIS_MODULE,
+		   .pm = &rockchip_dp_pm_ops,
+		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
+	},
+};
+
+module_platform_driver(rockchip_dp_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index d1188db..25afb31 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -15,6 +15,7 @@
 
 enum analogix_dp_devtype {
 	EXYNOS_DP,
+	RK3288_DP,
 };
 
 struct analogix_dp_plat_data {
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 10/17] dt-bindings: add document for rockchip variant of analogix_dp
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (8 preceding siblings ...)
  2016-02-15 11:10 ` [PATCH v14 09/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
@ 2016-02-15 11:10 ` Yakir Yang
  2016-02-15 11:10 ` [PATCH v14 11/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
                   ` (9 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:10 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10:
- Add the ack from Rob Herring

Changes in v9:
- Document more details for 'ports' property.

Changes in v8:
- Modify the commit subject name. (Heiko)

Changes in v7: None
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)

Changes in v4: None
Changes in v3: None
Changes in v2: None

 .../display/rockchip/analogix_dp-rockchip.txt      | 91 ++++++++++++++++++++++
 1 file changed, 91 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt

diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..04d99e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -0,0 +1,91 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+	  of memory mapped region.
+
+- clock-names: from common clock binding:
+	       Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+	  See ../reset/reset.txt for details.
+
+- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
+- pinctrl-0: pin-control mode. should be <&edp_hpd>
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: there are 2 port nodes with endpoint definitions as defined in
+  Documentation/devicetree/bindings/media/video-interfaces.txt.
+    Port 0: contained 2 endpoints, connecting to the output of vop.
+    Port 1: contained 1 endpoint, connecting to the input of panel.
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+	dp-controller: dp@ff970000 {
+		compatible = "rockchip,rk3288-dp";
+		reg = <0xff970000 0x4000>;
+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+		clock-names = "dp", "pclk";
+		phys = <&dp_phy>;
+		phy-names = "dp";
+
+		rockchip,grf = <&grf>;
+		resets = <&cru 111>;
+		reset-names = "dp";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&edp_hpd>;
+
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			edp_in: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_in_vopb: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&vopb_out_edp>;
+				};
+				edp_in_vopl: endpoint@1 {
+					reg = <1>;
+					remote-endpoint = <&vopl_out_edp>;
+				};
+			};
+
+			edp_out: port@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				edp_out_panel: endpoint {
+					reg = <0>;
+					remote-endpoint = <&panel_in_edp>
+				};
+			};
+		};
+	};
+
+	pinctrl {
+		edp {
+			edp_hpd: edp-hpd {
+				rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
+			};
+		};
+	};
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 11/17] drm: bridge: analogix/dp: add some rk3288 special registers setting
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (9 preceding siblings ...)
  2016-02-15 11:10 ` [PATCH v14 10/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
@ 2016-02-15 11:10 ` Yakir Yang
  2016-03-18  6:56   ` Caesar Wang
  2016-02-15 11:11 ` [PATCH v14 12/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
                   ` (8 subsequent siblings)
  19 siblings, 1 reply; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:10 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error

 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++++++++++++++---------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 ++++
 2 files changed, 60 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 3858df5..1e24b37 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -15,6 +15,8 @@
 #include <linux/delay.h>
 #include <linux/gpio.h>
 
+#include <drm/bridge/analogix_dp.h>
+
 #include "analogix_dp_core.h"
 #include "analogix_dp_reg.h"
 
@@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
 	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
 
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
+		writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
+		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
+		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
+		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
+	}
+
 	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
 	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
 
@@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable)
 {
 	u32 reg;
+	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		phy_pd_addr = ANALOGIX_DP_PD;
 
 	switch (block) {
 	case AUX_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH0_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH1_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH2_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case CH3_BLOCK:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case ANALOG_TOTAL:
 		if (enable) {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+			reg = readl(dp->reg_base + phy_pd_addr);
 			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	case POWER_ALL:
 		if (enable) {
 			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
 				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(reg, dp->reg_base + phy_pd_addr);
 		} else {
-			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+			writel(0x00, dp->reg_base + phy_pd_addr);
 		}
 		break;
 	default:
@@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
-	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
+		      AUX_HW_RETRY_COUNT_SEL(3) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	else
+		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
+		      AUX_HW_RETRY_COUNT_SEL(0) |
+		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 738db4c..337912b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -22,6 +22,14 @@
 #define ANALOGIX_DP_VIDEO_CTL_8			0x3C
 #define ANALOGIX_DP_VIDEO_CTL_10		0x44
 
+#define ANALOGIX_DP_PLL_REG_1			0xfc
+#define ANALOGIX_DP_PLL_REG_2			0x9e4
+#define ANALOGIX_DP_PLL_REG_3			0x9e8
+#define ANALOGIX_DP_PLL_REG_4			0x9ec
+#define ANALOGIX_DP_PLL_REG_5			0xa00
+
+#define ANALOGIX_DP_PD				0x12c
+
 #define ANALOGIX_DP_LANE_MAP			0x35C
 
 #define ANALOGIX_DP_ANALOG_CTL_1		0x370
@@ -154,6 +162,10 @@
 #define VSYNC_POLARITY_CFG			(0x1 << 1)
 #define HSYNC_POLARITY_CFG			(0x1 << 0)
 
+/* ANALOGIX_DP_PLL_REG_1 */
+#define REF_CLK_24M				(0x1 << 1)
+#define REF_CLK_27M				(0x0 << 1)
+
 /* ANALOGIX_DP_LANE_MAP */
 #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
 #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 12/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (10 preceding siblings ...)
  2016-02-15 11:10 ` [PATCH v14 11/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
@ 2016-02-15 11:11 ` Yakir Yang
  2016-02-15 11:11 ` [PATCH v14 13/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
                   ` (7 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:11 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10:
- Remove the surplus "plat_data" check. (Heiko)
-       switch (dp->plat_data && dp->plat_data->dev_type) {
+       switch (dp->plat_data->dev_type) {

Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
  flag. (Thierry)

Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 33 ++++++++++++++--------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  4 +--
 2 files changed, 23 insertions(+), 14 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 26359f4..a62e8d0 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -893,8 +893,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 		return;
 	}
 
-	ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
-					 dp->video_info.link_rate);
+	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
+					 dp->video_info.max_link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1203,16 +1203,25 @@ static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
 	struct device_node *dp_node = dp->dev->of_node;
 	struct video_info *video_info = &dp->video_info;
 
-	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				 &video_info->link_rate)) {
-		dev_err(dp->dev, "failed to get link-rate\n");
-		return -EINVAL;
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				 &video_info->lane_count)) {
-		dev_err(dp->dev, "failed to get lane-count\n");
-		return -EINVAL;
+	switch (dp->plat_data->dev_type) {
+	case RK3288_DP:
+		/*
+		 * Like Rk3288 DisplayPort TRM indicate that "Main link
+		 * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
+		 */
+		video_info->max_link_rate = 0x0A;
+		video_info->max_lane_count = 0x04;
+		break;
+	case EXYNOS_DP:
+		/*
+		 * NOTE: those property parseing code is used for
+		 * providing backward compatibility for samsung platform.
+		 */
+		of_property_read_u32(dp_node, "samsung,link-rate",
+				     &video_info->max_link_rate);
+		of_property_read_u32(dp_node, "samsung,lane-count",
+				     &video_info->max_lane_count);
+		break;
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 123030f..02c0ecf 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -123,8 +123,8 @@ struct video_info {
 	enum color_coefficient ycbcr_coeff;
 	enum color_depth color_depth;
 
-	int link_rate;
-	enum link_lane_count_type lane_count;
+	int max_link_rate;
+	enum link_lane_count_type max_lane_count;
 };
 
 struct link_train {
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 13/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (11 preceding siblings ...)
  2016-02-15 11:11 ` [PATCH v14 12/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
@ 2016-02-15 11:11 ` Yakir Yang
  2016-02-15 11:11 ` [PATCH v14 14/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
                   ` (6 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:11 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.

This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11:
- Rename the "analogix,need-force-hpd" to common 'force-hpd' (Rob)
- Add the ack from Rob Herring

Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
  hpd when hpd detect failed.

Changes in v2: None

 .../bindings/display/bridge/analogix_dp.txt        |  4 ++-
 .../bindings/display/exynos/exynos_dp.txt          |  1 +
 .../display/rockchip/analogix_dp-rockchip.txt      |  1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 35 ++++++++++++++++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  2 ++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  |  9 ++++++
 6 files changed, 46 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
index 7659a7a..4f2ba8c 100644
--- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
+++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
@@ -22,6 +22,9 @@ Required properties for dp-controller:
 		from general PHY binding: Should be "dp".
 
 Optional properties for dp-controller:
+	-force-hpd:
+		Indicate driver need force hpd when hpd detect failed, this
+		is used for some eDP screen which don't have hpd signal.
 	-hpd-gpios:
 		Hotplug detect GPIO.
 		Indicates which GPIO should be used for hotplug detection
@@ -31,7 +34,6 @@ Optional properties for dp-controller:
 		* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
 		* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
 
-
 [1]: Documentation/devicetree/bindings/media/video-interfaces.txt
 -------------------------------------------------------------------------------
 
diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
index 4fa8aca..ade5d8e 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
@@ -56,6 +56,7 @@ For the below properties, please refer to Analogix DP binding document:
 	-phys (required)
 	-phy-names (required)
 	-hpd-gpios (optional)
+	 force-hpd (optional)
 
 Deprecated properties for DisplayPort:
 -interlaced:            deprecated prop that can parsed from drm_display_mode.
diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
index 04d99e3..e832ff9 100644
--- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -32,6 +32,7 @@ For the below properties, please refer to Analogix DP binding document:
 - phys (required)
 - phy-names (required)
 - hpd-gpios (optional)
+- force-hpd (optional)
 -------------------------------------------------------------------------------
 
 Example:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index a62e8d0..13986b7 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -62,15 +62,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 {
 	int timeout_loop = 0;
 
-	while (analogix_dp_get_plug_in_status(dp) != 0) {
+	while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
+		if (analogix_dp_get_plug_in_status(dp) == 0)
+			return 0;
+
 		timeout_loop++;
-		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
-			dev_err(dp->dev, "failed to get hpd plug status\n");
-			return -ETIMEDOUT;
-		}
 		usleep_range(10, 11);
 	}
 
+	/*
+	 * Some edp screen do not have hpd signal, so we can't just
+	 * return failed when hpd plug in detect failed, DT property
+	 * "force-hpd" would indicate whether driver need this.
+	 */
+	if (!dp->force_hpd)
+		return -ETIMEDOUT;
+
+	/*
+	 * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
+	 * will not work, so we need to give a force hpd action to
+	 * set HPD_STATUS manually.
+	 */
+	dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
+
+	analogix_dp_force_hpd(dp);
+
+	if (analogix_dp_get_plug_in_status(dp) != 0) {
+		dev_err(dp->dev, "failed to get hpd plug in status\n");
+		return -EINVAL;
+	}
+
+	dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
+
 	return 0;
 }
 
@@ -1291,6 +1314,8 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	if (IS_ERR(dp->reg_base))
 		return PTR_ERR(dp->reg_base);
 
+	dp->force_hpd = of_property_read_bool(dev->of_node, "force-hpd");
+
 	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
 	if (!gpio_is_valid(dp->hpd_gpio))
 		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 02c0ecf..22aff07 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -154,6 +154,7 @@ struct analogix_dp_device {
 	struct phy		*phy;
 	int			dpms_mode;
 	int			hpd_gpio;
+	bool                    force_hpd;
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -174,6 +175,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
 				       bool enable);
 void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
 void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+void analogix_dp_force_hpd(struct analogix_dp_device *dp);
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
 void analogix_dp_reset_aux(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 1e24b37..cba3ffd 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
 	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
 }
 
+void analogix_dp_force_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+	reg = (F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
 {
 	u32 reg;
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 14/17] drm: bridge: analogix/dp: move hpd detect to connector detect function
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (12 preceding siblings ...)
  2016-02-15 11:11 ` [PATCH v14 13/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
@ 2016-02-15 11:11 ` Yakir Yang
  2016-02-15 11:11 ` [PATCH v14 15/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
                   ` (5 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:11 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().

Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
	drm/exynos: do not start enabling DP at bind() phase

But for now the connector status don't hardcode to connected,
need to operate dp phy in .detect function, so we need to revert
parts if Gustavo Padovan's changes, add phy poweron
function in bind time.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11:
- Revert parts of Gustavo Padovan's changes in commit:
	drm/exynos: do not start enabling DP at bind() phase
  Add dp phy poweron function in bind time.
- Move the panel prepare from get_modes time to bind time, and move
  the panel unprepare from bridge->disable to unbind time. (Heiko)

Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit messages.

Changes in v3:
- move dp hpd detect to connector detect function.

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 38 ++++++++++++----------
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 13986b7..cfdf695 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -904,12 +904,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_detect_hpd(dp);
-	if (ret) {
-		/* Cable has been disconnected, we're done */
-		return;
-	}
-
 	ret = analogix_dp_handle_edid(dp);
 	if (ret) {
 		dev_err(dp->dev, "unable to handle edid\n");
@@ -972,6 +966,11 @@ static const struct drm_connector_helper_funcs analogix_dp_connector_helper_func
 enum drm_connector_status
 analogix_dp_detect(struct drm_connector *connector, bool force)
 {
+	struct analogix_dp_device *dp = to_dp(connector);
+
+	if (analogix_dp_detect_hpd(dp))
+		return connector_status_disconnected;
+
 	return connector_status_connected;
 }
 
@@ -1051,13 +1050,6 @@ static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
 
 	pm_runtime_get_sync(dp->dev);
 
-	if (dp->plat_data->panel) {
-		if (drm_panel_prepare(dp->plat_data->panel)) {
-			DRM_ERROR("failed to setup the panel\n");
-			return;
-		}
-	}
-
 	if (dp->plat_data->power_on)
 		dp->plat_data->power_on(dp->plat_data);
 
@@ -1090,11 +1082,6 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 	if (dp->plat_data->power_off)
 		dp->plat_data->power_off(dp->plat_data);
 
-	if (dp->plat_data->panel) {
-		if (drm_panel_unprepare(dp->plat_data->panel))
-			DRM_ERROR("failed to turnoff the panel\n");
-	}
-
 	pm_runtime_put_sync(dp->dev);
 
 	dp->dpms_mode = DRM_MODE_DPMS_OFF;
@@ -1352,6 +1339,15 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 
 	pm_runtime_enable(dev);
 
+	phy_power_on(dp->phy);
+
+	if (dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
+			DRM_ERROR("failed to setup the panel\n");
+			return -EBUSY;
+		}
+	}
+
 	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
 			       irq_flags, "analogix-dp", dp);
 	if (ret) {
@@ -1385,6 +1381,12 @@ void analogix_dp_unbind(struct device *dev, struct device *master,
 	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
 	analogix_dp_bridge_disable(dp->bridge);
+
+	if (dp->plat_data->panel) {
+		if (drm_panel_unprepare(dp->plat_data->panel))
+			DRM_ERROR("failed to turnoff the panel\n");
+	}
+
 	pm_runtime_disable(dev);
 }
 EXPORT_SYMBOL_GPL(analogix_dp_unbind);
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 15/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (13 preceding siblings ...)
  2016-02-15 11:11 ` [PATCH v14 14/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
@ 2016-02-15 11:11 ` Yakir Yang
  2016-02-15 11:11 ` [PATCH v14 16/17] drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time Yakir Yang
                   ` (4 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:11 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.

Note: Gustavo Padovan try to remove the controller and phy
power on function in bind time at bellow commit:
	drm/exynos: do not start enabling DP at bind() phase

But for now driver need to read edid message in .get_modes()
function, so controller must be inited in bind time, so we
need to add controller init back.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel should
  power on before driver try to read edid message.

Changes in v3:
- Add edid modes parse support

Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 17 ++++----
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 46 +++++++++++-----------
 2 files changed, 33 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index cfdf695..bc59e8d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -110,7 +110,7 @@ static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
 
 static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 {
-	unsigned char edid[EDID_BLOCK_LENGTH * 2];
+	unsigned char *edid = dp->edid;
 	unsigned int extend_block = 0;
 	unsigned char sum;
 	unsigned char test_vector;
@@ -904,12 +904,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 			DRM_ERROR("failed to disable the panel\n");
 	}
 
-	ret = analogix_dp_handle_edid(dp);
-	if (ret) {
-		dev_err(dp->dev, "unable to handle edid\n");
-		return;
-	}
-
 	ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
 					 dp->video_info.max_link_rate);
 	if (ret) {
@@ -939,8 +933,14 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 int analogix_dp_get_modes(struct drm_connector *connector)
 {
 	struct analogix_dp_device *dp = to_dp(connector);
+	struct edid *edid = (struct edid *)dp->edid;
 	int num_modes = 0;
 
+	if (analogix_dp_handle_edid(dp) == 0) {
+		drm_mode_connector_update_edid_property(&dp->connector, edid);
+		num_modes += drm_add_edid_modes(&dp->connector, edid);
+	}
+
 	if (dp->plat_data->panel)
 		num_modes += drm_panel_get_modes(dp->plat_data->panel);
 
@@ -978,6 +978,7 @@ static void analogix_dp_connector_destroy(struct drm_connector *connector)
 {
 	drm_connector_unregister(connector);
 	drm_connector_cleanup(connector);
+
 }
 
 static const struct drm_connector_funcs analogix_dp_connector_funcs = {
@@ -1348,6 +1349,8 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 		}
 	}
 
+	analogix_dp_init_dp(dp);
+
 	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
 			       irq_flags, "analogix-dp", dp);
 	if (ret) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 22aff07..48b4a87 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,28 @@
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
 
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
 enum link_lane_count_type {
 	LANE_COUNT1 = 1,
 	LANE_COUNT2 = 2,
@@ -155,6 +177,7 @@ struct analogix_dp_device {
 	int			dpms_mode;
 	int			hpd_gpio;
 	bool                    force_hpd;
+	unsigned char           edid[EDID_BLOCK_LENGTH * 2];
 
 	struct analogix_dp_plat_data *plat_data;
 };
@@ -254,27 +277,4 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
 #endif /* _ANALOGIX_DP_CORE_H */
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 16/17] drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (14 preceding siblings ...)
  2016-02-15 11:11 ` [PATCH v14 15/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
@ 2016-02-15 11:11 ` Yakir Yang
  2016-02-15 11:11 ` [PATCH v14 17/17] drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time Yakir Yang
                   ` (3 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:11 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Turn off the panel power in suspend time would help to reduce
power waste.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index bc59e8d..5292b28 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -1400,6 +1400,12 @@ int analogix_dp_suspend(struct device *dev)
 	struct analogix_dp_device *dp = dev_get_drvdata(dev);
 
 	clk_disable_unprepare(dp->clock);
+
+	if (dp->plat_data->panel) {
+		if (drm_panel_unprepare(dp->plat_data->panel))
+			DRM_ERROR("failed to turnoff the panel\n");
+	}
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(analogix_dp_suspend);
@@ -1415,6 +1421,13 @@ int analogix_dp_resume(struct device *dev)
 		return ret;
 	}
 
+	if (dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
+			DRM_ERROR("failed to setup the panel\n");
+			return -EBUSY;
+		}
+	}
+
 	return 0;
 }
 EXPORT_SYMBOL_GPL(analogix_dp_resume);
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14 17/17] drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (15 preceding siblings ...)
  2016-02-15 11:11 ` [PATCH v14 16/17] drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time Yakir Yang
@ 2016-02-15 11:11 ` Yakir Yang
  2016-03-18  6:41 ` [PATCH v14 0/17] Add Analogix Core Display Port Driver Caesar Wang
                   ` (2 subsequent siblings)
  19 siblings, 0 replies; 57+ messages in thread
From: Yakir Yang @ 2016-02-15 11:11 UTC (permalink / raw)
  To: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Heiko Stuebner, Mark Yao
  Cc: Russell King, djkurtz, Sean Paul, Kukjin Kim, Kumar Gala,
	emil.l.velikov, Ian Campbell, Gustavo Padovan,
	Kishon Vijay Abraham I, Pawel Moll, ajaynumb, robherring2,
	javier, Andy Yan, Yakir Yang, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

It may caused a dead lock if we flush the hpd work in bridge disable time.

The normal flow would like:
  IN --> DRM IOCTL
        1. Acquire crtc_ww_class_mutex (DRM IOCTL)
  IN --> analogix_dp_bridge
        2. Acquire hpd work lock (Flush hpd work)
        3. HPD work already in idle, no need to run the work function.
  OUT <-- analogix_dp_bridge
  OUT <-- DRM IOCTL

The dead lock flow would like:
  IN --> DRM IOCTL
        1. Acquire crtc_ww_class_mutex (DRM IOCTL)
  IN --> analogix_dp_bridge
        2. Acquire hpd work lock (Flush hpd work)
  IN --> analogix_dp_hotplug
  IN --> drm_helper_hpd_irq_event
        3. Acquire mode_config lock (This lock already have been acquired in previous step 1)
** Dead Lock Now **

It's wrong to flush the hpd work in bridge->disable time, I guess the
original code just want to ensure the delay work must be finish before
encoder disabled.

The flush work in bridge disable time is try to ensure the HPD event
won't be missed before display card disabled, actually we can take a
fast respond way(interrupt thread) to update DRM HPD event to fix the
delay update and possible dead lock.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v14: None
Changes in v13: None
Changes in v12: None
Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 62 ++++++++++------------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  3 +-
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 26 +++++++++
 3 files changed, 55 insertions(+), 36 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 5292b28..7699597 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -851,47 +851,40 @@ static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
 	}
 }
 
-static irqreturn_t analogix_dp_irq_handler(int irq, void *arg)
+static irqreturn_t analogix_dp_hardirq(int irq, void *arg)
 {
 	struct analogix_dp_device *dp = arg;
-
+	irqreturn_t ret = IRQ_NONE;
 	enum dp_irq_type irq_type;
 
 	irq_type = analogix_dp_get_irq_type(dp);
-	switch (irq_type) {
-	case DP_IRQ_TYPE_HP_CABLE_IN:
-		dev_dbg(dp->dev, "Received irq - cable in\n");
-		schedule_work(&dp->hotplug_work);
-		analogix_dp_clear_hotplug_interrupts(dp);
-		break;
-	case DP_IRQ_TYPE_HP_CABLE_OUT:
-		dev_dbg(dp->dev, "Received irq - cable out\n");
-		analogix_dp_clear_hotplug_interrupts(dp);
-		break;
-	case DP_IRQ_TYPE_HP_CHANGE:
-		/*
-		 * We get these change notifications once in a while, but there
-		 * is nothing we can do with them. Just ignore it for now and
-		 * only handle cable changes.
-		 */
-		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
-		analogix_dp_clear_hotplug_interrupts(dp);
-		break;
-	default:
-		dev_err(dp->dev, "Received irq - unknown type!\n");
-		break;
+	if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
+		analogix_dp_mute_hpd_interrupt(dp);
+		ret = IRQ_WAKE_THREAD;
 	}
-	return IRQ_HANDLED;
+
+	return ret;
 }
 
-static void analogix_dp_hotplug(struct work_struct *work)
+static irqreturn_t analogix_dp_irq_thread(int irq, void *arg)
 {
-	struct analogix_dp_device *dp;
+	struct analogix_dp_device *dp = arg;
+	enum dp_irq_type irq_type;
+
+	irq_type = analogix_dp_get_irq_type(dp);
+	if (irq_type & DP_IRQ_TYPE_HP_CABLE_IN ||
+	    irq_type & DP_IRQ_TYPE_HP_CABLE_OUT) {
+		dev_dbg(dp->dev, "Detected cable status changed!\n");
+		if (dp->drm_dev)
+			drm_helper_hpd_irq_event(dp->drm_dev);
+	}
 
-	dp = container_of(work, struct analogix_dp_device, hotplug_work);
+	if (irq_type != DP_IRQ_TYPE_UNKNOWN) {
+		analogix_dp_clear_hotplug_interrupts(dp);
+		analogix_dp_unmute_hpd_interrupt(dp);
+	}
 
-	if (dp->drm_dev)
-		drm_helper_hpd_irq_event(dp->drm_dev);
+	return IRQ_HANDLED;
 }
 
 static void analogix_dp_commit(struct analogix_dp_device *dp)
@@ -1077,7 +1070,6 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
 	}
 
 	disable_irq(dp->irq);
-	flush_work(&dp->hotplug_work);
 	phy_power_off(dp->phy);
 
 	if (dp->plat_data->power_off)
@@ -1336,8 +1328,6 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 		return -ENODEV;
 	}
 
-	INIT_WORK(&dp->hotplug_work, analogix_dp_hotplug);
-
 	pm_runtime_enable(dev);
 
 	phy_power_on(dp->phy);
@@ -1351,8 +1341,10 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 
 	analogix_dp_init_dp(dp);
 
-	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
-			       irq_flags, "analogix-dp", dp);
+	ret = devm_request_threaded_irq(&pdev->dev, dp->irq,
+					analogix_dp_hardirq,
+					analogix_dp_irq_thread,
+					irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		goto err_disable_pm_runtime;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 48b4a87..f09275d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -172,7 +172,6 @@ struct analogix_dp_device {
 
 	struct video_info	video_info;
 	struct link_train	link_train;
-	struct work_struct	hotplug_work;
 	struct phy		*phy;
 	int			dpms_mode;
 	int			hpd_gpio;
@@ -191,6 +190,8 @@ void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
 void analogix_dp_reset(struct analogix_dp_device *dp);
 void analogix_dp_swreset(struct analogix_dp_device *dp);
 void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
+void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp);
+void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp);
 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index cba3ffd..49205ef 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -185,6 +185,32 @@ void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
 	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
 }
 
+void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* 0: mask, 1: unmask */
+	reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+	reg &= ~COMMON_INT_MASK_4;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+
+	reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+	reg &= ~INT_STA_MASK;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
+void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* 0: mask, 1: unmask */
+	reg = COMMON_INT_MASK_4;
+	writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4);
+
+	reg = INT_STA_MASK;
+	writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK);
+}
+
 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
 {
 	u32 reg;
-- 
1.9.1

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14.1 01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
  2016-02-15 11:09 ` [PATCH v14 01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Yakir Yang
@ 2016-03-17 21:47   ` Heiko Stübner
  2016-03-18  7:01     ` Caesar Wang
  2016-06-07 17:06     ` Javier Martinez Canillas
  2016-03-30 20:32   ` [v14, " Guenter Roeck
  1 sibling, 2 replies; 57+ messages in thread
From: Heiko Stübner @ 2016-03-17 21:47 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Mark Yao, Russell King, djkurtz, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, javier, Andy Yan, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.

Beside the new analogix_dp driver would export six hooks.
"analogix_dp_bind()" and "analogix_dp_unbind()"
"analogix_dp_suspned()" and "analogix_dp_resume()"
"analogix_dp_detect()" and "analogix_dp_get_modes()"

The bind/unbind symbols is used for analogix platform driver to connect
with analogix_dp core driver. And the detect/get_modes is used for analogix
platform driver to init the connector.

They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v14.1:
- Rebase against drm-next from 2016-03-17
  (adapt to another round of exynos-dp changes)

Changes in v14:
- Rebase the new changes in imx-dp driver
- Split up this patch into 3 parts, make this easy to review (Heiko)

Changes in v13: None
Changes in v12:
- Move the connector init to analogix_dp driver, and using ATOMIC helper (Heiko)

Changes in v11:
- Uses tabs to fix the indentation issues in analogix_dp_core.h (Heiko)

Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6:
- Fix the Kconfig recursive dependency (Javier)

Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
  the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
  attch function. Cause once platform failed at attach, core driver should
  still failed, so no need to init connector before platform attached (Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
  patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)

Changes in v4:
- Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
- Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
- Create a separate folder for analogix code in bridge/ (Archit)

Changes in v3:
- Move exynos's video_timing code to analogix_dp-exynos platform driver,
  add get_modes method to struct analogix_dp_plat_data. (Thierry)
- Rename some "samsung*" dts propery to "analogix*". (Heiko)

Changes in v2:
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell


 drivers/gpu/drm/bridge/Kconfig                     |    2 +
 drivers/gpu/drm/bridge/Makefile                    |    1 +
 drivers/gpu/drm/bridge/analogix/Kconfig            |    3 +
 drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1351 +++++++++++++++++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  277 ++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1263 ++++++++++++++++++
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h  |  366 ++++++
 drivers/gpu/drm/exynos/Kconfig                     |    3 +-
 drivers/gpu/drm/exynos/Makefile                    |    2 +-
 drivers/gpu/drm/exynos/exynos_dp_core.c            | 1353 ++------------------
 drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 ----
 drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 ------------------
 drivers/gpu/drm/exynos/exynos_dp_reg.h             |  366 ------
 include/drm/bridge/analogix_dp.h                   |   40 +
 15 files changed, 3391 insertions(+), 3182 deletions(-)
 create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
 create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
 create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
 delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.h
 create mode 100644 include/drm/bridge/analogix_dp.h

diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index 27e2022..efd94e0 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -40,4 +40,6 @@ config DRM_PARADE_PS8622
 	---help---
 	  Parade eDP-LVDS bridge chip driver.
 
+source "drivers/gpu/drm/bridge/analogix/Kconfig"
+
 endmenu
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index f13c33d..ff821f4 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
 obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
new file mode 100644
index 0000000..80f286f
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Kconfig
@@ -0,0 +1,3 @@
+config DRM_ANALOGIX_DP
+	tristate
+	depends on DRM
diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
new file mode 100644
index 0000000..9107b86
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
new file mode 100644
index 0000000..392c296
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -0,0 +1,1351 @@
+/*
+* Analogix DP (Display Port) core interface driver.
+*
+* Copyright (C) 2012 Samsung Electronics Co., Ltd.
+* Author: Jingoo Han <jg1.han@samsung.com>
+*
+* This program is free software; you can redistribute it and/or modify it
+* under the terms of the GNU General Public License as published by the
+* Free Software Foundation; either version 2 of the License, or (at your
+* option) any later version.
+*/
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/interrupt.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/gpio.h>
+#include <linux/component.h>
+#include <linux/phy/phy.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_panel.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "analogix_dp_core.h"
+
+#define to_dp(nm)	container_of(nm, struct analogix_dp_device, nm)
+
+struct bridge_init {
+	struct i2c_client *client;
+	struct device_node *node;
+};
+
+static void analogix_dp_init_dp(struct analogix_dp_device *dp)
+{
+	analogix_dp_reset(dp);
+
+	analogix_dp_swreset(dp);
+
+	analogix_dp_init_analog_param(dp);
+	analogix_dp_init_interrupt(dp);
+
+	/* SW defined function Normal operation */
+	analogix_dp_enable_sw_function(dp);
+
+	analogix_dp_config_interrupt(dp);
+	analogix_dp_init_analog_func(dp);
+
+	analogix_dp_init_hpd(dp);
+	analogix_dp_init_aux(dp);
+}
+
+static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
+{
+	int timeout_loop = 0;
+
+	while (analogix_dp_get_plug_in_status(dp) != 0) {
+		timeout_loop++;
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "failed to get hpd plug status\n");
+			return -ETIMEDOUT;
+		}
+		usleep_range(10, 11);
+	}
+
+	return 0;
+}
+
+static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
+{
+	int i;
+	unsigned char sum = 0;
+
+	for (i = 0; i < EDID_BLOCK_LENGTH; i++)
+		sum = sum + edid_data[i];
+
+	return sum;
+}
+
+static int analogix_dp_read_edid(struct analogix_dp_device *dp)
+{
+	unsigned char edid[EDID_BLOCK_LENGTH * 2];
+	unsigned int extend_block = 0;
+	unsigned char sum;
+	unsigned char test_vector;
+	int retval;
+
+	/*
+	 * EDID device address is 0x50.
+	 * However, if necessary, you must have set upper address
+	 * into E-EDID in I2C device, 0x30.
+	 */
+
+	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
+	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+				EDID_EXTENSION_FLAG,
+				&extend_block);
+	if (retval)
+		return retval;
+
+	if (extend_block > 0) {
+		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
+
+		/* Read EDID data */
+		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+						EDID_HEADER_PATTERN,
+						EDID_BLOCK_LENGTH,
+						&edid[EDID_HEADER_PATTERN]);
+		if (retval != 0) {
+			dev_err(dp->dev, "EDID Read failed!\n");
+			return -EIO;
+		}
+		sum = analogix_dp_calc_edid_check_sum(edid);
+		if (sum != 0) {
+			dev_err(dp->dev, "EDID bad checksum!\n");
+			return -EIO;
+		}
+
+		/* Read additional EDID data */
+		retval = analogix_dp_read_bytes_from_i2c(dp,
+				I2C_EDID_DEVICE_ADDR,
+				EDID_BLOCK_LENGTH,
+				EDID_BLOCK_LENGTH,
+				&edid[EDID_BLOCK_LENGTH]);
+		if (retval != 0) {
+			dev_err(dp->dev, "EDID Read failed!\n");
+			return -EIO;
+		}
+		sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
+		if (sum != 0) {
+			dev_err(dp->dev, "EDID bad checksum!\n");
+			return -EIO;
+		}
+
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+					&test_vector);
+		if (test_vector & DP_TEST_LINK_EDID_READ) {
+			analogix_dp_write_byte_to_dpcd(dp,
+				DP_TEST_EDID_CHECKSUM,
+				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
+			analogix_dp_write_byte_to_dpcd(dp,
+				DP_TEST_RESPONSE,
+				DP_TEST_EDID_CHECKSUM_WRITE);
+		}
+	} else {
+		dev_info(dp->dev, "EDID data does not include any extensions.\n");
+
+		/* Read EDID data */
+		retval = analogix_dp_read_bytes_from_i2c(dp,
+				I2C_EDID_DEVICE_ADDR,
+				EDID_HEADER_PATTERN,
+				EDID_BLOCK_LENGTH,
+				&edid[EDID_HEADER_PATTERN]);
+		if (retval != 0) {
+			dev_err(dp->dev, "EDID Read failed!\n");
+			return -EIO;
+		}
+		sum = analogix_dp_calc_edid_check_sum(edid);
+		if (sum != 0) {
+			dev_err(dp->dev, "EDID bad checksum!\n");
+			return -EIO;
+		}
+
+		analogix_dp_read_byte_from_dpcd(dp,
+			DP_TEST_REQUEST,
+			&test_vector);
+		if (test_vector & DP_TEST_LINK_EDID_READ) {
+			analogix_dp_write_byte_to_dpcd(dp,
+				DP_TEST_EDID_CHECKSUM,
+				edid[EDID_CHECKSUM]);
+			analogix_dp_write_byte_to_dpcd(dp,
+				DP_TEST_RESPONSE,
+				DP_TEST_EDID_CHECKSUM_WRITE);
+		}
+	}
+
+	dev_dbg(dp->dev, "EDID Read success!\n");
+	return 0;
+}
+
+static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
+{
+	u8 buf[12];
+	int i;
+	int retval;
+
+	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
+				12, buf);
+	if (retval)
+		return retval;
+
+	/* Read EDID */
+	for (i = 0; i < 3; i++) {
+		retval = analogix_dp_read_edid(dp);
+		if (!retval)
+			break;
+	}
+
+	return retval;
+}
+
+static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
+						bool enable)
+{
+	u8 data;
+
+	analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
+
+	if (enable)
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+			DP_LANE_COUNT_ENHANCED_FRAME_EN |
+			DPCD_LANE_COUNT_SET(data));
+	else
+		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
+			DPCD_LANE_COUNT_SET(data));
+}
+
+static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
+{
+	u8 data;
+	int retval;
+
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	retval = DPCD_ENHANCED_FRAME_CAP(data);
+
+	return retval;
+}
+
+static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
+{
+	u8 data;
+
+	data = analogix_dp_is_enhanced_mode_available(dp);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, data);
+	analogix_dp_enable_enhanced_mode(dp, data);
+}
+
+static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
+{
+	analogix_dp_set_training_pattern(dp, DP_NONE);
+
+	analogix_dp_write_byte_to_dpcd(dp,
+		DP_TRAINING_PATTERN_SET,
+		DP_TRAINING_PATTERN_DISABLE);
+}
+
+static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
+					int pre_emphasis, int lane)
+{
+	switch (lane) {
+	case 0:
+		analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
+		break;
+	case 1:
+		analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
+		break;
+
+	case 2:
+		analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
+		break;
+
+	case 3:
+		analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
+		break;
+	}
+}
+
+static int analogix_dp_link_start(struct analogix_dp_device *dp)
+{
+	u8 buf[4];
+	int lane, lane_count, pll_tries, retval;
+
+	lane_count = dp->link_train.lane_count;
+
+	dp->link_train.lt_state = CLOCK_RECOVERY;
+	dp->link_train.eq_loop = 0;
+
+	for (lane = 0; lane < lane_count; lane++)
+		dp->link_train.cr_loop[lane] = 0;
+
+	/* Set link rate and count as you want to establish*/
+	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
+	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
+
+	/* Setup RX configuration */
+	buf[0] = dp->link_train.link_rate;
+	buf[1] = dp->link_train.lane_count;
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
+				2, buf);
+	if (retval)
+		return retval;
+
+	/* Set TX pre-emphasis to minimum */
+	for (lane = 0; lane < lane_count; lane++)
+		analogix_dp_set_lane_lane_pre_emphasis(dp,
+			PRE_EMPHASIS_LEVEL_0, lane);
+
+	/* Wait for PLL lock */
+	pll_tries = 0;
+	while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
+			dev_err(dp->dev, "Wait for PLL lock timed out\n");
+			return -ETIMEDOUT;
+		}
+
+		pll_tries++;
+		usleep_range(90, 120);
+	}
+
+	/* Set training pattern 1 */
+	analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
+
+	/* Set RX training pattern */
+	retval = analogix_dp_write_byte_to_dpcd(dp,
+			DP_TRAINING_PATTERN_SET,
+			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
+	if (retval)
+		return retval;
+
+	for (lane = 0; lane < lane_count; lane++)
+		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
+			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
+
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+			lane_count, buf);
+
+	return retval;
+}
+
+static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
+{
+	int shift = (lane & 1) * 4;
+	u8 link_value = link_status[lane>>1];
+
+	return (link_value >> shift) & 0xf;
+}
+
+static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
+{
+	int lane;
+	u8 lane_status;
+
+	for (lane = 0; lane < lane_count; lane++) {
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
+		if ((lane_status & DP_LANE_CR_DONE) == 0)
+			return -EINVAL;
+	}
+	return 0;
+}
+
+static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
+				int lane_count)
+{
+	int lane;
+	u8 lane_status;
+
+	if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
+		return -EINVAL;
+
+	for (lane = 0; lane < lane_count; lane++) {
+		lane_status = analogix_dp_get_lane_status(link_status, lane);
+		lane_status &= DP_CHANNEL_EQ_BITS;
+		if (lane_status != DP_CHANNEL_EQ_BITS)
+			return -EINVAL;
+	}
+
+	return 0;
+}
+
+static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
+							int lane)
+{
+	int shift = (lane & 1) * 4;
+	u8 link_value = adjust_request[lane>>1];
+
+	return (link_value >> shift) & 0x3;
+}
+
+static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
+					u8 adjust_request[2],
+					int lane)
+{
+	int shift = (lane & 1) * 4;
+	u8 link_value = adjust_request[lane>>1];
+
+	return ((link_value >> shift) & 0xc) >> 2;
+}
+
+static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
+					u8 training_lane_set, int lane)
+{
+	switch (lane) {
+	case 0:
+		analogix_dp_set_lane0_link_training(dp, training_lane_set);
+		break;
+	case 1:
+		analogix_dp_set_lane1_link_training(dp, training_lane_set);
+		break;
+
+	case 2:
+		analogix_dp_set_lane2_link_training(dp, training_lane_set);
+		break;
+
+	case 3:
+		analogix_dp_set_lane3_link_training(dp, training_lane_set);
+		break;
+	}
+}
+
+static unsigned int analogix_dp_get_lane_link_training(
+				struct analogix_dp_device *dp,
+				int lane)
+{
+	u32 reg;
+
+	switch (lane) {
+	case 0:
+		reg = analogix_dp_get_lane0_link_training(dp);
+		break;
+	case 1:
+		reg = analogix_dp_get_lane1_link_training(dp);
+		break;
+	case 2:
+		reg = analogix_dp_get_lane2_link_training(dp);
+		break;
+	case 3:
+		reg = analogix_dp_get_lane3_link_training(dp);
+		break;
+	default:
+		WARN_ON(1);
+		return 0;
+	}
+
+	return reg;
+}
+
+static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
+{
+	analogix_dp_training_pattern_dis(dp);
+	analogix_dp_set_enhanced_mode(dp);
+
+	dp->link_train.lt_state = FAILED;
+}
+
+static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
+					u8 adjust_request[2])
+{
+	int lane, lane_count;
+	u8 voltage_swing, pre_emphasis, training_lane;
+
+	lane_count = dp->link_train.lane_count;
+	for (lane = 0; lane < lane_count; lane++) {
+		voltage_swing = analogix_dp_get_adjust_request_voltage(
+						adjust_request, lane);
+		pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
+						adjust_request, lane);
+		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
+				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
+
+		if (voltage_swing == VOLTAGE_LEVEL_3)
+			training_lane |= DP_TRAIN_MAX_SWING_REACHED;
+		if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
+			training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+
+		dp->link_train.training_lane[lane] = training_lane;
+	}
+}
+
+static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
+{
+	int lane, lane_count, retval;
+	u8 voltage_swing, pre_emphasis, training_lane;
+	u8 link_status[2], adjust_request[2];
+
+	usleep_range(100, 101);
+
+	lane_count = dp->link_train.lane_count;
+
+	retval =  analogix_dp_read_bytes_from_dpcd(dp,
+			DP_LANE0_1_STATUS, 2, link_status);
+	if (retval)
+		return retval;
+
+	retval =  analogix_dp_read_bytes_from_dpcd(dp,
+			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
+	if (retval)
+		return retval;
+
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
+		/* set training pattern 2 for EQ */
+		analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
+
+		retval = analogix_dp_write_byte_to_dpcd(dp,
+				DP_TRAINING_PATTERN_SET,
+				DP_LINK_SCRAMBLING_DISABLE |
+				DP_TRAINING_PATTERN_2);
+		if (retval)
+			return retval;
+
+		dev_info(dp->dev, "Link Training Clock Recovery success\n");
+		dp->link_train.lt_state = EQUALIZER_TRAINING;
+	} else {
+		for (lane = 0; lane < lane_count; lane++) {
+			training_lane = analogix_dp_get_lane_link_training(
+							dp, lane);
+			voltage_swing = analogix_dp_get_adjust_request_voltage(
+							adjust_request, lane);
+			pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
+							adjust_request, lane);
+
+			if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
+					voltage_swing &&
+			    DPCD_PRE_EMPHASIS_GET(training_lane) ==
+					pre_emphasis)
+				dp->link_train.cr_loop[lane]++;
+
+			if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
+			    voltage_swing == VOLTAGE_LEVEL_3 ||
+			    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
+				dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
+					dp->link_train.cr_loop[lane],
+					voltage_swing, pre_emphasis);
+				analogix_dp_reduce_link_rate(dp);
+				return -EIO;
+			}
+		}
+	}
+
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
+
+	for (lane = 0; lane < lane_count; lane++)
+		analogix_dp_set_lane_link_training(dp,
+			dp->link_train.training_lane[lane], lane);
+
+	retval = analogix_dp_write_bytes_to_dpcd(dp,
+			DP_TRAINING_LANE0_SET, lane_count,
+			dp->link_train.training_lane);
+	if (retval)
+		return retval;
+
+	return retval;
+}
+
+static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
+{
+	int lane, lane_count, retval;
+	u32 reg;
+	u8 link_align, link_status[2], adjust_request[2];
+
+	usleep_range(400, 401);
+
+	lane_count = dp->link_train.lane_count;
+
+	retval = analogix_dp_read_bytes_from_dpcd(dp,
+			DP_LANE0_1_STATUS, 2, link_status);
+	if (retval)
+		return retval;
+
+	if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
+		analogix_dp_reduce_link_rate(dp);
+		return -EIO;
+	}
+
+	retval = analogix_dp_read_bytes_from_dpcd(dp,
+			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
+	if (retval)
+		return retval;
+
+	retval = analogix_dp_read_byte_from_dpcd(dp,
+			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
+	if (retval)
+		return retval;
+
+	analogix_dp_get_adjust_training_lane(dp, adjust_request);
+
+	if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
+		/* traing pattern Set to Normal */
+		analogix_dp_training_pattern_dis(dp);
+
+		dev_info(dp->dev, "Link Training success!\n");
+
+		analogix_dp_get_link_bandwidth(dp, &reg);
+		dp->link_train.link_rate = reg;
+		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
+			dp->link_train.link_rate);
+
+		analogix_dp_get_lane_count(dp, &reg);
+		dp->link_train.lane_count = reg;
+		dev_dbg(dp->dev, "final lane count = %.2x\n",
+			dp->link_train.lane_count);
+
+		/* set enhanced mode if available */
+		analogix_dp_set_enhanced_mode(dp);
+		dp->link_train.lt_state = FINISHED;
+
+		return 0;
+	}
+
+	/* not all locked */
+	dp->link_train.eq_loop++;
+
+	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
+		dev_err(dp->dev, "EQ Max loop\n");
+		analogix_dp_reduce_link_rate(dp);
+		return -EIO;
+	}
+
+	for (lane = 0; lane < lane_count; lane++)
+		analogix_dp_set_lane_link_training(dp,
+			dp->link_train.training_lane[lane], lane);
+
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
+			lane_count, dp->link_train.training_lane);
+
+	return retval;
+}
+
+static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
+					u8 *bandwidth)
+{
+	u8 data;
+
+	/*
+	 * For DP rev.1.1, Maximum link rate of Main Link lanes
+	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+	 */
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
+	*bandwidth = data;
+}
+
+static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
+					u8 *lane_count)
+{
+	u8 data;
+
+	/*
+	 * For DP rev.1.1, Maximum number of Main Link lanes
+	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
+	 */
+	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
+	*lane_count = DPCD_MAX_LANE_COUNT(data);
+}
+
+static void analogix_dp_init_training(struct analogix_dp_device *dp,
+			enum link_lane_count_type max_lane,
+			enum link_rate_type max_rate)
+{
+	/*
+	 * MACRO_RST must be applied after the PLL_LOCK to avoid
+	 * the DP inter pair skew issue for at least 10 us
+	 */
+	analogix_dp_reset_macro(dp);
+
+	/* Initialize by reading RX's DPCD */
+	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
+	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
+
+	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
+	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
+			dp->link_train.link_rate);
+		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
+	}
+
+	if (dp->link_train.lane_count == 0) {
+		dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
+			dp->link_train.lane_count);
+		dp->link_train.lane_count = (u8)LANE_COUNT1;
+	}
+
+	/* Setup TX lane count & rate */
+	if (dp->link_train.lane_count > max_lane)
+		dp->link_train.lane_count = max_lane;
+	if (dp->link_train.link_rate > max_rate)
+		dp->link_train.link_rate = max_rate;
+
+	/* All DP analog module power up */
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
+}
+
+static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
+{
+	int retval = 0, training_finished = 0;
+
+	dp->link_train.lt_state = START;
+
+	/* Process here */
+	while (!retval && !training_finished) {
+		switch (dp->link_train.lt_state) {
+		case START:
+			retval = analogix_dp_link_start(dp);
+			if (retval)
+				dev_err(dp->dev, "LT link start failed!\n");
+			break;
+		case CLOCK_RECOVERY:
+			retval = analogix_dp_process_clock_recovery(dp);
+			if (retval)
+				dev_err(dp->dev, "LT CR failed!\n");
+			break;
+		case EQUALIZER_TRAINING:
+			retval = analogix_dp_process_equalizer_training(dp);
+			if (retval)
+				dev_err(dp->dev, "LT EQ failed!\n");
+			break;
+		case FINISHED:
+			training_finished = 1;
+			break;
+		case FAILED:
+			return -EREMOTEIO;
+		}
+	}
+	if (retval)
+		dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
+
+	return retval;
+}
+
+static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
+				u32 count,
+				u32 bwtype)
+{
+	int i;
+	int retval;
+
+	for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
+		analogix_dp_init_training(dp, count, bwtype);
+		retval = analogix_dp_sw_link_training(dp);
+		if (retval == 0)
+			break;
+
+		usleep_range(100, 110);
+	}
+
+	return retval;
+}
+
+static int analogix_dp_config_video(struct analogix_dp_device *dp)
+{
+	int retval = 0;
+	int timeout_loop = 0;
+	int done_count = 0;
+
+	analogix_dp_config_video_slave_mode(dp);
+
+	analogix_dp_set_video_color_format(dp);
+
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		dev_err(dp->dev, "PLL is not locked yet.\n");
+		return -EINVAL;
+	}
+
+	for (;;) {
+		timeout_loop++;
+		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
+			break;
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "Timeout of video streamclk ok\n");
+			return -ETIMEDOUT;
+		}
+
+		usleep_range(1, 2);
+	}
+
+	/* Set to use the register calculated M/N video */
+	analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
+
+	/* For video bist, Video timing must be generated by register */
+	analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
+
+	/* Disable video mute */
+	analogix_dp_enable_video_mute(dp, 0);
+
+	/* Configure video slave mode */
+	analogix_dp_enable_video_master(dp, 0);
+
+	timeout_loop = 0;
+
+	for (;;) {
+		timeout_loop++;
+		if (analogix_dp_is_video_stream_on(dp) == 0) {
+			done_count++;
+			if (done_count > 10)
+				break;
+		} else if (done_count) {
+			done_count = 0;
+		}
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "Timeout of video streamclk ok\n");
+			return -ETIMEDOUT;
+		}
+
+		usleep_range(1000, 1001);
+	}
+
+	if (retval != 0)
+		dev_err(dp->dev, "Video stream is not detected!\n");
+
+	return retval;
+}
+
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
+{
+	u8 data;
+
+	if (enable) {
+		analogix_dp_enable_scrambling(dp);
+
+		analogix_dp_read_byte_from_dpcd(dp,
+			DP_TRAINING_PATTERN_SET,
+			&data);
+		analogix_dp_write_byte_to_dpcd(dp,
+			DP_TRAINING_PATTERN_SET,
+			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
+	} else {
+		analogix_dp_disable_scrambling(dp);
+
+		analogix_dp_read_byte_from_dpcd(dp,
+			DP_TRAINING_PATTERN_SET,
+			&data);
+		analogix_dp_write_byte_to_dpcd(dp,
+			DP_TRAINING_PATTERN_SET,
+			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
+	}
+}
+
+static irqreturn_t analogix_dp_irq_handler(int irq, void *arg)
+{
+	struct analogix_dp_device *dp = arg;
+
+	enum dp_irq_type irq_type;
+
+	irq_type = analogix_dp_get_irq_type(dp);
+	switch (irq_type) {
+	case DP_IRQ_TYPE_HP_CABLE_IN:
+		dev_dbg(dp->dev, "Received irq - cable in\n");
+		schedule_work(&dp->hotplug_work);
+		analogix_dp_clear_hotplug_interrupts(dp);
+		break;
+	case DP_IRQ_TYPE_HP_CABLE_OUT:
+		dev_dbg(dp->dev, "Received irq - cable out\n");
+		analogix_dp_clear_hotplug_interrupts(dp);
+		break;
+	case DP_IRQ_TYPE_HP_CHANGE:
+		/*
+		 * We get these change notifications once in a while, but there
+		 * is nothing we can do with them. Just ignore it for now and
+		 * only handle cable changes.
+		 */
+		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
+		analogix_dp_clear_hotplug_interrupts(dp);
+		break;
+	default:
+		dev_err(dp->dev, "Received irq - unknown type!\n");
+		break;
+	}
+	return IRQ_HANDLED;
+}
+
+static void analogix_dp_hotplug(struct work_struct *work)
+{
+	struct analogix_dp_device *dp;
+
+	dp = container_of(work, struct analogix_dp_device, hotplug_work);
+
+	if (dp->drm_dev)
+		drm_helper_hpd_irq_event(dp->drm_dev);
+}
+
+static void analogix_dp_commit(struct analogix_dp_device *dp)
+{
+	int ret;
+
+	/* Keep the panel disabled while we configure video */
+	if (dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel))
+			DRM_ERROR("failed to disable the panel\n");
+	}
+
+	ret = analogix_dp_detect_hpd(dp);
+	if (ret) {
+		/* Cable has been disconnected, we're done */
+		return;
+	}
+
+	ret = analogix_dp_handle_edid(dp);
+	if (ret) {
+		dev_err(dp->dev, "unable to handle edid\n");
+		return;
+	}
+
+	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
+					dp->video_info->link_rate);
+	if (ret) {
+		dev_err(dp->dev, "unable to do link train\n");
+		return;
+	}
+
+	analogix_dp_enable_scramble(dp, 1);
+	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
+	analogix_dp_enable_enhanced_mode(dp, 1);
+
+	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
+	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
+
+	analogix_dp_init_video(dp);
+	ret = analogix_dp_config_video(dp);
+	if (ret)
+		dev_err(dp->dev, "unable to config video\n");
+
+	/* Safe to enable the panel now */
+	if (dp->plat_data->panel) {
+		if (drm_panel_enable(dp->plat_data->panel))
+			DRM_ERROR("failed to enable the panel\n");
+	}
+
+	/* Enable video */
+	analogix_dp_start_video(dp);
+}
+
+int analogix_dp_get_modes(struct drm_connector *connector)
+{
+	struct analogix_dp_device *dp = to_dp(connector);
+	int num_modes = 0;
+
+	if (dp->plat_data->panel)
+		num_modes += drm_panel_get_modes(dp->plat_data->panel);
+
+	if (dp->plat_data->get_modes)
+		num_modes += dp->plat_data->get_modes(dp->plat_data);
+
+	return num_modes;
+}
+
+static struct drm_encoder *
+analogix_dp_best_encoder(struct drm_connector *connector)
+{
+	struct analogix_dp_device *dp = to_dp(connector);
+
+	return dp->encoder;
+}
+
+static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
+	.get_modes = analogix_dp_get_modes,
+	.best_encoder = analogix_dp_best_encoder,
+};
+
+enum drm_connector_status
+analogix_dp_detect(struct drm_connector *connector, bool force)
+{
+	return connector_status_connected;
+}
+
+static void analogix_dp_connector_destroy(struct drm_connector *connector)
+{
+	drm_connector_unregister(connector);
+	drm_connector_cleanup(connector);
+}
+
+static const struct drm_connector_funcs analogix_dp_connector_funcs = {
+	.dpms = drm_atomic_helper_connector_dpms,
+	.fill_modes = drm_helper_probe_single_connector_modes,
+	.detect = analogix_dp_detect,
+	.destroy = analogix_dp_connector_destroy,
+	.reset = drm_atomic_helper_connector_reset,
+	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+	struct drm_encoder *encoder = dp->encoder;
+	struct drm_connector *connector = &dp->connector;
+	int ret;
+
+	if (!bridge->encoder) {
+		DRM_ERROR("Parent encoder object not found");
+		return -ENODEV;
+	}
+
+	connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+	ret = drm_connector_init(dp->drm_dev, connector,
+				 &analogix_dp_connector_funcs,
+				 DRM_MODE_CONNECTOR_eDP);
+	if (ret) {
+		DRM_ERROR("Failed to initialize connector with drm\n");
+		return ret;
+	}
+
+	drm_connector_helper_add(connector,
+				 &analogix_dp_connector_helper_funcs);
+	drm_mode_connector_attach_encoder(connector, encoder);
+
+	/*
+	 * NOTE: the connector registration is implemented in analogix
+	 * platform driver, that to say connector would be exist after
+	 * plat_data->attch return, that's why we record the connector
+	 * point after plat attached.
+	 */
+	 if (dp->plat_data->attach) {
+		 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
+		 if (ret) {
+			 DRM_ERROR("Failed at platform attch func\n");
+			 return ret;
+		 }
+	}
+
+	if (dp->plat_data->panel) {
+		ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
+		if (ret) {
+			DRM_ERROR("Failed to attach panel\n");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+
+	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
+		return;
+
+	pm_runtime_get_sync(dp->dev);
+
+	if (dp->plat_data->panel) {
+		if (drm_panel_prepare(dp->plat_data->panel)) {
+			DRM_ERROR("failed to setup the panel\n");
+			return;
+		}
+	}
+
+	if (dp->plat_data->power_on)
+		dp->plat_data->power_on(dp->plat_data);
+
+	phy_power_on(dp->phy);
+	analogix_dp_init_dp(dp);
+	enable_irq(dp->irq);
+	analogix_dp_commit(dp);
+
+	dp->dpms_mode = DRM_MODE_DPMS_ON;
+}
+
+static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
+{
+	struct analogix_dp_device *dp = bridge->driver_private;
+
+	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
+		return;
+
+	if (dp->plat_data->panel) {
+		if (drm_panel_disable(dp->plat_data->panel)) {
+			DRM_ERROR("failed to disable the panel\n");
+			return;
+		}
+	}
+
+	disable_irq(dp->irq);
+	flush_work(&dp->hotplug_work);
+	phy_power_off(dp->phy);
+
+	if (dp->plat_data->power_off)
+		dp->plat_data->power_off(dp->plat_data);
+
+	if (dp->plat_data->panel) {
+		if (drm_panel_unprepare(dp->plat_data->panel))
+			DRM_ERROR("failed to turnoff the panel\n");
+	}
+
+	pm_runtime_put_sync(dp->dev);
+
+	dp->dpms_mode = DRM_MODE_DPMS_OFF;
+}
+
+static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
+{
+	/* do nothing */
+}
+
+static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
+	.enable = analogix_dp_bridge_enable,
+	.disable = analogix_dp_bridge_disable,
+	.pre_enable = analogix_dp_bridge_nop,
+	.post_disable = analogix_dp_bridge_nop,
+	.attach = analogix_dp_bridge_attach,
+};
+
+static int analogix_dp_create_bridge(struct drm_device *drm_dev,
+				     struct analogix_dp_device *dp)
+{
+	struct drm_bridge *bridge;
+	int ret;
+
+	bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
+	if (!bridge) {
+		DRM_ERROR("failed to allocate for drm bridge\n");
+		return -ENOMEM;
+	}
+
+	dp->bridge = bridge;
+
+	dp->encoder->bridge = bridge;
+	bridge->driver_private = dp;
+	bridge->encoder = dp->encoder;
+	bridge->funcs = &analogix_dp_bridge_funcs;
+
+	ret = drm_bridge_attach(drm_dev, bridge);
+	if (ret) {
+		DRM_ERROR("failed to attach drm bridge\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+{
+	struct device_node *dp_node = dev->of_node;
+	struct video_info *dp_video_config;
+
+	dp_video_config = devm_kzalloc(dev,
+				sizeof(*dp_video_config), GFP_KERNEL);
+	if (!dp_video_config)
+		return ERR_PTR(-ENOMEM);
+
+	dp_video_config->h_sync_polarity =
+		of_property_read_bool(dp_node, "hsync-active-high");
+
+	dp_video_config->v_sync_polarity =
+		of_property_read_bool(dp_node, "vsync-active-high");
+
+	dp_video_config->interlaced =
+		of_property_read_bool(dp_node, "interlaced");
+
+	if (of_property_read_u32(dp_node, "samsung,color-space",
+				&dp_video_config->color_space)) {
+		dev_err(dev, "failed to get color-space\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
+				&dp_video_config->dynamic_range)) {
+		dev_err(dev, "failed to get dynamic-range\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+				&dp_video_config->ycbcr_coeff)) {
+		dev_err(dev, "failed to get ycbcr-coeff\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (of_property_read_u32(dp_node, "samsung,color-depth",
+				&dp_video_config->color_depth)) {
+		dev_err(dev, "failed to get color-depth\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (of_property_read_u32(dp_node, "samsung,link-rate",
+				&dp_video_config->link_rate)) {
+		dev_err(dev, "failed to get link-rate\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (of_property_read_u32(dp_node, "samsung,lane-count",
+				&dp_video_config->lane_count)) {
+		dev_err(dev, "failed to get lane-count\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	return dp_video_config;
+}
+
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct analogix_dp_plat_data *plat_data)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+	struct analogix_dp_device *dp;
+	struct resource *res;
+	unsigned int irq_flags;
+	int ret;
+
+	if (!plat_data) {
+		dev_err(dev, "Invalided input plat_data\n");
+		return -EINVAL;
+	}
+
+	dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dev_set_drvdata(dev, dp);
+
+	dp->dev = &pdev->dev;
+	dp->dpms_mode = DRM_MODE_DPMS_OFF;
+
+	/*
+	 * platform dp driver need containor_of the plat_data to get
+	 * the driver private data, so we need to store the point of
+	 * plat_data, not the context of plat_data.
+	 */
+	dp->plat_data = plat_data;
+
+	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
+	if (IS_ERR(dp->video_info))
+		return PTR_ERR(dp->video_info);
+
+	dp->phy = devm_phy_get(dp->dev, "dp");
+	if (IS_ERR(dp->phy)) {
+		dev_err(dp->dev, "no DP phy configured\n");
+		ret = PTR_ERR(dp->phy);
+		if (ret) {
+			/*
+			 * phy itself is not enabled, so we can move forward
+			 * assigning NULL to phy pointer.
+			 */
+			if (ret == -ENOSYS || ret == -ENODEV)
+				dp->phy = NULL;
+			else
+				return ret;
+		}
+	}
+
+	dp->clock = devm_clk_get(&pdev->dev, "dp");
+	if (IS_ERR(dp->clock)) {
+		dev_err(&pdev->dev, "failed to get clock\n");
+		return PTR_ERR(dp->clock);
+	}
+
+	clk_prepare_enable(dp->clock);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
+	if (IS_ERR(dp->reg_base))
+		return PTR_ERR(dp->reg_base);
+
+	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
+	if (!gpio_is_valid(dp->hpd_gpio))
+		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
+						 "samsung,hpd-gpio", 0);
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		/*
+		 * Set up the hotplug GPIO from the device tree as an interrupt.
+		 * Simply specifying a different interrupt in the device tree
+		 * doesn't work since we handle hotplug rather differently when
+		 * using a GPIO.  We also need the actual GPIO specifier so
+		 * that we can get the current state of the GPIO.
+		 */
+		ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
+					    "hpd_gpio");
+		if (ret) {
+			dev_err(&pdev->dev, "failed to get hpd gpio\n");
+			return ret;
+		}
+		dp->irq = gpio_to_irq(dp->hpd_gpio);
+		irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
+	} else {
+		dp->hpd_gpio = -ENODEV;
+		dp->irq = platform_get_irq(pdev, 0);
+		irq_flags = 0;
+	}
+
+	if (dp->irq == -ENXIO) {
+		dev_err(&pdev->dev, "failed to get irq\n");
+		return -ENODEV;
+	}
+
+	INIT_WORK(&dp->hotplug_work, analogix_dp_hotplug);
+
+	pm_runtime_enable(dev);
+
+	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
+			irq_flags, "analogix-dp", dp);
+	if (ret) {
+		dev_err(&pdev->dev, "failed to request irq\n");
+		goto err_disable_pm_runtime;
+	}
+	disable_irq(dp->irq);
+
+	dp->drm_dev = drm_dev;
+	dp->encoder = dp->plat_data->encoder;
+
+	ret = analogix_dp_create_bridge(drm_dev, dp);
+	if (ret) {
+		DRM_ERROR("failed to create bridge (%d)\n", ret);
+		drm_encoder_cleanup(dp->encoder);
+		goto err_disable_pm_runtime;
+	}
+
+	return 0;
+
+err_disable_pm_runtime:
+	pm_runtime_disable(dev);
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(analogix_dp_bind);
+
+void analogix_dp_unbind(struct device *dev, struct device *master,
+			void *data)
+{
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+
+	analogix_dp_bridge_disable(dp->bridge);
+	pm_runtime_disable(dev);
+}
+EXPORT_SYMBOL_GPL(analogix_dp_unbind);
+
+#ifdef CONFIG_PM
+int analogix_dp_suspend(struct device *dev)
+{
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(dp->clock);
+	return 0;
+}
+EXPORT_SYMBOL_GPL(analogix_dp_suspend);
+
+int analogix_dp_resume(struct device *dev)
+{
+	struct analogix_dp_device *dp = dev_get_drvdata(dev);
+	int ret;
+
+	ret = clk_prepare_enable(dp->clock);
+	if (ret < 0) {
+		DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(analogix_dp_resume);
+#endif
+
+MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
+MODULE_DESCRIPTION("Analogix DP Core Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
new file mode 100644
index 0000000..0fff745
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -0,0 +1,277 @@
+/*
+ * Header file for Analogix DP (Display Port) core interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef _ANALOGIX_DP_CORE_H
+#define _ANALOGIX_DP_CORE_H
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_dp_helper.h>
+
+#define DP_TIMEOUT_LOOP_COUNT 100
+#define MAX_CR_LOOP 5
+#define MAX_EQ_LOOP 5
+
+enum link_rate_type {
+	LINK_RATE_1_62GBPS = 0x06,
+	LINK_RATE_2_70GBPS = 0x0a
+};
+
+enum link_lane_count_type {
+	LANE_COUNT1 = 1,
+	LANE_COUNT2 = 2,
+	LANE_COUNT4 = 4
+};
+
+enum link_training_state {
+	START,
+	CLOCK_RECOVERY,
+	EQUALIZER_TRAINING,
+	FINISHED,
+	FAILED
+};
+
+enum voltage_swing_level {
+	VOLTAGE_LEVEL_0,
+	VOLTAGE_LEVEL_1,
+	VOLTAGE_LEVEL_2,
+	VOLTAGE_LEVEL_3,
+};
+
+enum pre_emphasis_level {
+	PRE_EMPHASIS_LEVEL_0,
+	PRE_EMPHASIS_LEVEL_1,
+	PRE_EMPHASIS_LEVEL_2,
+	PRE_EMPHASIS_LEVEL_3,
+};
+
+enum pattern_set {
+	PRBS7,
+	D10_2,
+	TRAINING_PTN1,
+	TRAINING_PTN2,
+	DP_NONE
+};
+
+enum color_space {
+	COLOR_RGB,
+	COLOR_YCBCR422,
+	COLOR_YCBCR444
+};
+
+enum color_depth {
+	COLOR_6,
+	COLOR_8,
+	COLOR_10,
+	COLOR_12
+};
+
+enum color_coefficient {
+	COLOR_YCBCR601,
+	COLOR_YCBCR709
+};
+
+enum dynamic_range {
+	VESA,
+	CEA
+};
+
+enum pll_status {
+	PLL_UNLOCKED,
+	PLL_LOCKED
+};
+
+enum clock_recovery_m_value_type {
+	CALCULATED_M,
+	REGISTER_M
+};
+
+enum video_timing_recognition_type {
+	VIDEO_TIMING_FROM_CAPTURE,
+	VIDEO_TIMING_FROM_REGISTER
+};
+
+enum analog_power_block {
+	AUX_BLOCK,
+	CH0_BLOCK,
+	CH1_BLOCK,
+	CH2_BLOCK,
+	CH3_BLOCK,
+	ANALOG_TOTAL,
+	POWER_ALL
+};
+
+enum dp_irq_type {
+	DP_IRQ_TYPE_HP_CABLE_IN,
+	DP_IRQ_TYPE_HP_CABLE_OUT,
+	DP_IRQ_TYPE_HP_CHANGE,
+	DP_IRQ_TYPE_UNKNOWN,
+};
+
+struct video_info {
+	char *name;
+
+	bool h_sync_polarity;
+	bool v_sync_polarity;
+	bool interlaced;
+
+	enum color_space color_space;
+	enum dynamic_range dynamic_range;
+	enum color_coefficient ycbcr_coeff;
+	enum color_depth color_depth;
+
+	enum link_rate_type link_rate;
+	enum link_lane_count_type lane_count;
+};
+
+struct link_train {
+	int eq_loop;
+	int cr_loop[4];
+
+	u8 link_rate;
+	u8 lane_count;
+	u8 training_lane[4];
+
+	enum link_training_state lt_state;
+};
+
+struct analogix_dp_device {
+	struct drm_encoder	*encoder;
+	struct device		*dev;
+	struct drm_device	*drm_dev;
+	struct drm_connector	connector;
+	struct drm_bridge	*bridge;
+	struct clk		*clock;
+	unsigned int		irq;
+	void __iomem		*reg_base;
+
+	struct video_info	*video_info;
+	struct link_train	link_train;
+	struct work_struct	hotplug_work;
+	struct phy		*phy;
+	int			dpms_mode;
+	int			hpd_gpio;
+
+	struct analogix_dp_plat_data *plat_data;
+};
+
+/* analogix_dp_reg.c */
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_stop_video(struct analogix_dp_device *dp);
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
+void analogix_dp_reset(struct analogix_dp_device *dp);
+void analogix_dp_swreset(struct analogix_dp_device *dp);
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				       enum analog_power_block block,
+				       bool enable);
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
+void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
+void analogix_dp_reset_aux(struct analogix_dp_device *dp);
+void analogix_dp_init_aux(struct analogix_dp_device *dp);
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char data);
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char *data);
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[]);
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[]);
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr);
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int *data);
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char edid[]);
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+				u32 training_lane);
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
+void analogix_dp_reset_macro(struct analogix_dp_device *dp);
+void analogix_dp_init_video(struct analogix_dp_device *dp);
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+			enum clock_recovery_m_value_type type,
+			u32 m_value,
+			u32 n_value);
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_start_video(struct analogix_dp_device *dp);
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
+
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR			0x50
+#define I2C_E_EDID_DEVICE_ADDR			0x30
+
+#define EDID_BLOCK_LENGTH			0x80
+#define EDID_HEADER_PATTERN			0x00
+#define EDID_EXTENSION_FLAG			0x7e
+#define EDID_CHECKSUM				0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
+
+#endif /* _ANALOGIX_DP_CORE_H */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
new file mode 100644
index 0000000..0b926ea
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -0,0 +1,1263 @@
+/*
+ * Analogix DP (Display port) core register interface driver.
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+
+#include "analogix_dp_core.h"
+#include "analogix_dp_reg.h"
+
+#define COMMON_INT_MASK_1	0
+#define COMMON_INT_MASK_2	0
+#define COMMON_INT_MASK_3	0
+#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
+#define INT_STA_MASK		INT_HPD
+
+void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+		reg |= HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+	} else {
+		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+		reg &= ~HDCP_VIDEO_MUTE;
+		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+	}
+}
+
+void analogix_dp_stop_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+	reg &= ~VIDEO_EN;
+	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+}
+
+void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable)
+		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
+			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+	else
+		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
+			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+
+	writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
+}
+
+void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = TX_TERMINAL_CTRL_50_OHM;
+	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
+
+	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
+	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
+
+	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
+	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
+
+	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
+		TX_CUR1_2X | TX_CUR_16_MA;
+	writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
+
+	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
+		CH1_AMP_400_MV | CH0_AMP_400_MV;
+	writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
+}
+
+void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
+{
+	/* Set interrupt pin assertion polarity as high */
+	writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
+
+	/* Clear pending regisers */
+	writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
+	writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
+	writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
+	writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
+	writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
+
+	/* 0:mask,1: unmask */
+	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
+	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
+	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
+	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
+	writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
+}
+
+void analogix_dp_reset(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	analogix_dp_stop_video(dp);
+	analogix_dp_enable_video_mute(dp, 0);
+
+	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
+		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
+		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
+
+	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
+		SERDES_FIFO_FUNC_EN_N |
+		LS_CLK_DOMAIN_FUNC_EN_N;
+	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+
+	usleep_range(20, 30);
+
+	analogix_dp_lane_swap(dp, 0);
+
+	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
+	writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
+	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+
+	writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
+	writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
+
+	writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
+	writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
+
+	writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
+
+	writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
+
+	writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
+	writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
+
+	writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
+	writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
+
+	writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_swreset(struct analogix_dp_device *dp)
+{
+	writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
+}
+
+void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* 0: mask, 1: unmask */
+	reg = COMMON_INT_MASK_1;
+	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
+
+	reg = COMMON_INT_MASK_2;
+	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
+
+	reg = COMMON_INT_MASK_3;
+	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
+
+	reg = COMMON_INT_MASK_4;
+	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
+
+	reg = INT_STA_MASK;
+	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
+}
+
+enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
+	if (reg & PLL_LOCK)
+		return PLL_LOCKED;
+	else
+		return PLL_UNLOCKED;
+}
+
+void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
+		reg |= DP_PLL_PD;
+		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
+	} else {
+		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
+		reg &= ~DP_PLL_PD;
+		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
+	}
+}
+
+void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
+				enum analog_power_block block,
+				bool enable)
+{
+	u32 reg;
+
+	switch (block) {
+	case AUX_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg |= AUX_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg &= ~AUX_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		}
+		break;
+	case CH0_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg |= CH0_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg &= ~CH0_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		}
+		break;
+	case CH1_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg |= CH1_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg &= ~CH1_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		}
+		break;
+	case CH2_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg |= CH2_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg &= ~CH2_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		}
+		break;
+	case CH3_BLOCK:
+		if (enable) {
+			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg |= CH3_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg &= ~CH3_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		}
+		break;
+	case ANALOG_TOTAL:
+		if (enable) {
+			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg |= DP_PHY_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		} else {
+			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
+			reg &= ~DP_PHY_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		}
+		break;
+	case POWER_ALL:
+		if (enable) {
+			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
+				CH1_PD | CH0_PD;
+			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
+		} else {
+			writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
+{
+	u32 reg;
+	int timeout_loop = 0;
+
+	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
+
+	reg = PLL_LOCK_CHG;
+	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
+
+	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
+	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
+	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
+
+	/* Power up PLL */
+	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+		analogix_dp_set_pll_power_down(dp, 0);
+
+		while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
+			timeout_loop++;
+			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+				dev_err(dp->dev, "failed to get pll lock status\n");
+				return;
+			}
+			usleep_range(10, 20);
+		}
+	}
+
+	/* Enable Serdes FIFO function and Link symbol clock domain module */
+	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
+		| AUX_FUNC_EN_N);
+	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+}
+
+void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
+	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
+
+	reg = INT_HPD;
+	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
+}
+
+void analogix_dp_init_hpd(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio))
+		return;
+
+	analogix_dp_clear_hotplug_interrupts(dp);
+
+	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+	reg &= ~(F_HPD | HPD_CTRL);
+	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+}
+
+enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		reg = gpio_get_value(dp->hpd_gpio);
+		if (reg)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+		else
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+	} else {
+		/* Parse hotplug interrupt status register */
+		reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
+
+		if (reg & PLUG)
+			return DP_IRQ_TYPE_HP_CABLE_IN;
+
+		if (reg & HPD_LOST)
+			return DP_IRQ_TYPE_HP_CABLE_OUT;
+
+		if (reg & HOTPLUG_CHG)
+			return DP_IRQ_TYPE_HP_CHANGE;
+
+		return DP_IRQ_TYPE_UNKNOWN;
+	}
+}
+
+void analogix_dp_reset_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Disable AUX channel module */
+	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+	reg |= AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+}
+
+void analogix_dp_init_aux(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Clear inerrupts related to AUX channel */
+	reg = RPLY_RECEIV | AUX_ERR;
+	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
+
+	analogix_dp_reset_aux(dp);
+
+	/* Disable AUX transaction H/W retry */
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
+		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
+
+	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
+	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
+	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
+
+	/* Enable AUX channel module */
+	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+	reg &= ~AUX_FUNC_EN_N;
+	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
+}
+
+int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	if (gpio_is_valid(dp->hpd_gpio)) {
+		if (gpio_get_value(dp->hpd_gpio))
+			return 0;
+	} else {
+		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+		if (reg & HPD_STATUS)
+			return 0;
+	}
+
+	return -EINVAL;
+}
+
+void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
+	reg &= ~SW_FUNC_EN_N;
+	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
+}
+
+int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
+{
+	int reg;
+	int retval = 0;
+	int timeout_loop = 0;
+
+	/* Enable AUX CH operation */
+	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
+	reg |= AUX_EN;
+	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
+
+	/* Is AUX CH command reply received? */
+	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
+	while (!(reg & RPLY_RECEIV)) {
+		timeout_loop++;
+		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+			dev_err(dp->dev, "AUX CH command reply failed!\n");
+			return -ETIMEDOUT;
+		}
+		reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
+		usleep_range(10, 11);
+	}
+
+	/* Clear interrupt source for AUX CH command reply */
+	writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
+
+	/* Clear interrupt source for AUX CH access error */
+	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
+	if (reg & AUX_ERR) {
+		writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
+		return -EREMOTEIO;
+	}
+
+	/* Check AUX CH error access status */
+	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
+	if ((reg & AUX_STATUS_MASK) != 0) {
+		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
+			reg & AUX_STATUS_MASK);
+		return -EREMOTEIO;
+	}
+
+	return retval;
+}
+
+int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
+
+		/* Write data buffer */
+		reg = (unsigned int)data;
+		writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
+
+		/*
+		 * Set DisplayPort transaction and write 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned char *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
+
+		/* Select DPCD device address */
+		reg = AUX_ADDR_7_0(reg_addr);
+		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
+		reg = AUX_ADDR_15_8(reg_addr);
+		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
+		reg = AUX_ADDR_19_16(reg_addr);
+		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
+
+		/*
+		 * Set DisplayPort transaction and read 1 byte
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	/* Read data buffer */
+	reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
+	*data = (unsigned char)(reg & 0xff);
+
+	return retval;
+}
+
+int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
+
+			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+			     cur_data_idx++) {
+				reg = data[start_offset + cur_data_idx];
+				writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
+							  + 4 * cur_data_idx);
+			}
+
+			/*
+			 * Set DisplayPort transaction and write
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
+			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+			else
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char data[])
+{
+	u32 reg;
+	unsigned int start_offset;
+	unsigned int cur_data_count;
+	unsigned int cur_data_idx;
+	int i;
+	int retval = 0;
+
+	/* Clear AUX CH data buffer */
+	reg = BUF_CLR;
+	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
+
+	start_offset = 0;
+	while (start_offset < count) {
+		/* Buffer size of AUX CH is 16 * 4bytes */
+		if ((count - start_offset) > 16)
+			cur_data_count = 16;
+		else
+			cur_data_count = count - start_offset;
+
+		/* AUX CH Request Transaction process */
+		for (i = 0; i < 3; i++) {
+			/* Select DPCD device address */
+			reg = AUX_ADDR_7_0(reg_addr + start_offset);
+			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
+			reg = AUX_ADDR_15_8(reg_addr + start_offset);
+			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
+			reg = AUX_ADDR_19_16(reg_addr + start_offset);
+			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
+
+			/*
+			 * Set DisplayPort transaction and read
+			 * If bit 3 is 1, DisplayPort transaction.
+			 * If Bit 3 is 0, I2C transaction.
+			 */
+			reg = AUX_LENGTH(cur_data_count) |
+				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
+			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
+
+			/* Start AUX transaction */
+			retval = analogix_dp_start_aux_transaction(dp);
+			if (retval == 0)
+				break;
+			else
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
+		    cur_data_idx++) {
+			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			data[start_offset + cur_data_idx] =
+				(unsigned char)reg;
+		}
+
+		start_offset += cur_data_count;
+	}
+
+	return retval;
+}
+
+int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr)
+{
+	u32 reg;
+	int retval;
+
+	/* Set EDID device address */
+	reg = device_addr;
+	writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
+	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
+	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
+
+	/* Set offset from base address of EDID device */
+	writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
+
+	/*
+	 * Set I2C transaction and write address
+	 * If bit 3 is 1, DisplayPort transaction.
+	 * If Bit 3 is 0, I2C transaction.
+	 */
+	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
+		AUX_TX_COMM_WRITE;
+	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
+
+	/* Start AUX transaction */
+	retval = analogix_dp_start_aux_transaction(dp);
+	if (retval != 0)
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
+
+	return retval;
+}
+
+int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int *data)
+{
+	u32 reg;
+	int i;
+	int retval;
+
+	for (i = 0; i < 3; i++) {
+		/* Clear AUX CH data buffer */
+		reg = BUF_CLR;
+		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
+
+		/* Select EDID device */
+		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+		if (retval != 0)
+			continue;
+
+		/*
+		 * Set I2C transaction and read data
+		 * If bit 3 is 1, DisplayPort transaction.
+		 * If Bit 3 is 0, I2C transaction.
+		 */
+		reg = AUX_TX_COMM_I2C_TRANSACTION |
+			AUX_TX_COMM_READ;
+		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
+
+		/* Start AUX transaction */
+		retval = analogix_dp_start_aux_transaction(dp);
+		if (retval == 0)
+			break;
+		else
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
+	}
+
+	/* Read data */
+	if (retval == 0)
+		*data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
+
+	return retval;
+}
+
+int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
+				unsigned int device_addr,
+				unsigned int reg_addr,
+				unsigned int count,
+				unsigned char edid[])
+{
+	u32 reg;
+	unsigned int i, j;
+	unsigned int cur_data_idx;
+	unsigned int defer = 0;
+	int retval = 0;
+
+	for (i = 0; i < count; i += 16) {
+		for (j = 0; j < 3; j++) {
+			/* Clear AUX CH data buffer */
+			reg = BUF_CLR;
+			writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
+
+			/* Set normal AUX CH command */
+			reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
+			reg &= ~ADDR_ONLY;
+			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
+
+			/*
+			 * If Rx sends defer, Tx sends only reads
+			 * request without sending address
+			 */
+			if (!defer)
+				retval = analogix_dp_select_i2c_device(dp,
+						device_addr, reg_addr + i);
+			else
+				defer = 0;
+
+			if (retval == 0) {
+				/*
+				 * Set I2C transaction and write data
+				 * If bit 3 is 1, DisplayPort transaction.
+				 * If Bit 3 is 0, I2C transaction.
+				 */
+				reg = AUX_LENGTH(16) |
+					AUX_TX_COMM_I2C_TRANSACTION |
+					AUX_TX_COMM_READ;
+				writel(reg, dp->reg_base +
+					EXYNOS_DP_AUX_CH_CTL_1);
+
+				/* Start AUX transaction */
+				retval = analogix_dp_start_aux_transaction(dp);
+				if (retval == 0)
+					break;
+				else
+					dev_dbg(dp->dev,
+						"%s: Aux Transaction fail!\n",
+						__func__);
+			}
+			/* Check if Rx sends defer */
+			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
+			if (reg == AUX_RX_COMM_AUX_DEFER ||
+				reg == AUX_RX_COMM_I2C_DEFER) {
+				dev_err(dp->dev, "Defer: %d\n\n", reg);
+				defer = 1;
+			}
+		}
+
+		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
+			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
+						 + 4 * cur_data_idx);
+			edid[i + cur_data_idx] = (unsigned char)reg;
+		}
+	}
+
+	return retval;
+}
+
+void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
+{
+	u32 reg;
+
+	reg = bwtype;
+	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
+		writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
+}
+
+void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
+	*bwtype = reg;
+}
+
+void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
+{
+	u32 reg;
+
+	reg = count;
+	writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
+}
+
+void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
+	*count = reg;
+}
+
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		reg |= ENHANCED;
+		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+	} else {
+		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		reg &= ~ENHANCED;
+		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+	}
+}
+
+void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
+				enum pattern_set pattern)
+{
+	u32 reg;
+
+	switch (pattern) {
+	case PRBS7:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
+		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+		break;
+	case D10_2:
+		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
+		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN1:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
+		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+		break;
+	case TRAINING_PTN2:
+		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
+		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+		break;
+	case DP_NONE:
+		reg = SCRAMBLING_ENABLE |
+			LINK_QUAL_PATTERN_SET_DISABLE |
+			SW_TRAINING_PATTERN_SET_NORMAL;
+		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+		break;
+	default:
+		break;
+	}
+}
+
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
+	reg &= ~PRE_EMPHASIS_SET_MASK;
+	reg |= level << PRE_EMPHASIS_SET_SHIFT;
+	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
+					 u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
+}
+
+void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
+					u32 training_lane)
+{
+	u32 reg;
+
+	reg = training_lane;
+	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
+}
+
+u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
+	return reg;
+}
+
+u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
+	return reg;
+}
+
+void analogix_dp_reset_macro(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
+	reg |= MACRO_RST;
+	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
+
+	/* 10 us is the minimum reset time. */
+	usleep_range(10, 20);
+
+	reg &= ~MACRO_RST;
+	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
+}
+
+void analogix_dp_init_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
+	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
+
+	reg = CHA_CRI(4) | CHA_CTRL;
+	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
+
+	reg = 0x0;
+	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+
+	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
+	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
+}
+
+void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	/* Configure the input color depth, color space, dynamic range */
+	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
+		(dp->video_info->color_depth << IN_BPC_SHIFT) |
+		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
+	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
+
+	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
+	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
+	reg &= ~IN_YC_COEFFI_MASK;
+	if (dp->video_info->ycbcr_coeff)
+		reg |= IN_YC_COEFFI_ITU709;
+	else
+		reg |= IN_YC_COEFFI_ITU601;
+	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
+}
+
+int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
+	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
+
+	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
+
+	if (!(reg & DET_STA)) {
+		dev_dbg(dp->dev, "Input stream clock not detected.\n");
+		return -EINVAL;
+	}
+
+	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
+	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
+
+	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
+	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
+
+	if (reg & CHA_STA) {
+		dev_dbg(dp->dev, "Input stream clk is changing\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
+		enum clock_recovery_m_value_type type,
+		u32 m_value,
+		u32 n_value)
+{
+	u32 reg;
+
+	if (type == REGISTER_M) {
+		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		reg |= FIX_M_VID;
+		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		reg = m_value & 0xff;
+		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
+		reg = (m_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
+		reg = (m_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
+
+		reg = n_value & 0xff;
+		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
+		reg = (n_value >> 8) & 0xff;
+		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
+		reg = (n_value >> 16) & 0xff;
+		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
+	} else  {
+		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+		reg &= ~FIX_M_VID;
+		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
+
+		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
+		writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
+		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
+	}
+}
+
+void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
+{
+	u32 reg;
+
+	if (type == VIDEO_TIMING_FROM_CAPTURE) {
+		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+		reg &= ~FORMAT_SEL;
+		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+	} else {
+		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+		reg |= FORMAT_SEL;
+		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+	}
+}
+
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
+{
+	u32 reg;
+
+	if (enable) {
+		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
+		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
+	} else {
+		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
+		reg &= ~VIDEO_MODE_MASK;
+		reg |= VIDEO_MODE_SLAVE_MODE;
+		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
+	}
+}
+
+void analogix_dp_start_video(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+	reg |= VIDEO_EN;
+	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
+}
+
+int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+
+	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
+	if (!(reg & STRM_VALID)) {
+		dev_dbg(dp->dev, "Input video stream is not detected.\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
+	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg |= MASTER_VID_FUNC_EN_N;
+	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
+
+	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+	reg &= ~INTERACE_SCAN_CFG;
+	reg |= (dp->video_info->interlaced << 2);
+	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+	reg &= ~VSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->v_sync_polarity << 1);
+	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+
+	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+	reg &= ~HSYNC_POLARITY_CFG;
+	reg |= (dp->video_info->h_sync_polarity << 0);
+	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
+
+	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
+	writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
+}
+
+void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+	reg &= ~SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+}
+
+void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
+{
+	u32 reg;
+
+	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+	reg |= SCRAMBLING_DISABLE;
+	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
+}
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
new file mode 100644
index 0000000..b9661c9
--- /dev/null
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -0,0 +1,366 @@
+/*
+ * Register definition file for Analogix DP core driver
+ *
+ * Copyright (C) 2012 Samsung Electronics Co., Ltd.
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef _ANALOGIX_DP_REG_H
+#define _ANALOGIX_DP_REG_H
+
+#define EXYNOS_DP_TX_SW_RESET			0x14
+#define EXYNOS_DP_FUNC_EN_1			0x18
+#define EXYNOS_DP_FUNC_EN_2			0x1C
+#define EXYNOS_DP_VIDEO_CTL_1			0x20
+#define EXYNOS_DP_VIDEO_CTL_2			0x24
+#define EXYNOS_DP_VIDEO_CTL_3			0x28
+
+#define EXYNOS_DP_VIDEO_CTL_8			0x3C
+#define EXYNOS_DP_VIDEO_CTL_10			0x44
+
+#define EXYNOS_DP_LANE_MAP			0x35C
+
+#define EXYNOS_DP_ANALOG_CTL_1			0x370
+#define EXYNOS_DP_ANALOG_CTL_2			0x374
+#define EXYNOS_DP_ANALOG_CTL_3			0x378
+#define EXYNOS_DP_PLL_FILTER_CTL_1		0x37C
+#define EXYNOS_DP_TX_AMP_TUNING_CTL		0x380
+
+#define EXYNOS_DP_AUX_HW_RETRY_CTL		0x390
+
+#define EXYNOS_DP_COMMON_INT_STA_1		0x3C4
+#define EXYNOS_DP_COMMON_INT_STA_2		0x3C8
+#define EXYNOS_DP_COMMON_INT_STA_3		0x3CC
+#define EXYNOS_DP_COMMON_INT_STA_4		0x3D0
+#define EXYNOS_DP_INT_STA			0x3DC
+#define EXYNOS_DP_COMMON_INT_MASK_1		0x3E0
+#define EXYNOS_DP_COMMON_INT_MASK_2		0x3E4
+#define EXYNOS_DP_COMMON_INT_MASK_3		0x3E8
+#define EXYNOS_DP_COMMON_INT_MASK_4		0x3EC
+#define EXYNOS_DP_INT_STA_MASK			0x3F8
+#define EXYNOS_DP_INT_CTL			0x3FC
+
+#define EXYNOS_DP_SYS_CTL_1			0x600
+#define EXYNOS_DP_SYS_CTL_2			0x604
+#define EXYNOS_DP_SYS_CTL_3			0x608
+#define EXYNOS_DP_SYS_CTL_4			0x60C
+
+#define EXYNOS_DP_PKT_SEND_CTL			0x640
+#define EXYNOS_DP_HDCP_CTL			0x648
+
+#define EXYNOS_DP_LINK_BW_SET			0x680
+#define EXYNOS_DP_LANE_COUNT_SET		0x684
+#define EXYNOS_DP_TRAINING_PTN_SET		0x688
+#define EXYNOS_DP_LN0_LINK_TRAINING_CTL		0x68C
+#define EXYNOS_DP_LN1_LINK_TRAINING_CTL		0x690
+#define EXYNOS_DP_LN2_LINK_TRAINING_CTL		0x694
+#define EXYNOS_DP_LN3_LINK_TRAINING_CTL		0x698
+
+#define EXYNOS_DP_DEBUG_CTL			0x6C0
+#define EXYNOS_DP_HPD_DEGLITCH_L		0x6C4
+#define EXYNOS_DP_HPD_DEGLITCH_H		0x6C8
+#define EXYNOS_DP_LINK_DEBUG_CTL		0x6E0
+
+#define EXYNOS_DP_M_VID_0			0x700
+#define EXYNOS_DP_M_VID_1			0x704
+#define EXYNOS_DP_M_VID_2			0x708
+#define EXYNOS_DP_N_VID_0			0x70C
+#define EXYNOS_DP_N_VID_1			0x710
+#define EXYNOS_DP_N_VID_2			0x714
+
+#define EXYNOS_DP_PLL_CTL			0x71C
+#define EXYNOS_DP_PHY_PD			0x720
+#define EXYNOS_DP_PHY_TEST			0x724
+
+#define EXYNOS_DP_VIDEO_FIFO_THRD		0x730
+#define EXYNOS_DP_AUDIO_MARGIN			0x73C
+
+#define EXYNOS_DP_M_VID_GEN_FILTER_TH		0x764
+#define EXYNOS_DP_M_AUD_GEN_FILTER_TH		0x778
+#define EXYNOS_DP_AUX_CH_STA			0x780
+#define EXYNOS_DP_AUX_CH_DEFER_CTL		0x788
+#define EXYNOS_DP_AUX_RX_COMM			0x78C
+#define EXYNOS_DP_BUFFER_DATA_CTL		0x790
+#define EXYNOS_DP_AUX_CH_CTL_1			0x794
+#define EXYNOS_DP_AUX_ADDR_7_0			0x798
+#define EXYNOS_DP_AUX_ADDR_15_8			0x79C
+#define EXYNOS_DP_AUX_ADDR_19_16		0x7A0
+#define EXYNOS_DP_AUX_CH_CTL_2			0x7A4
+
+#define EXYNOS_DP_BUF_DATA_0			0x7C0
+
+#define EXYNOS_DP_SOC_GENERAL_CTL		0x800
+
+/* EXYNOS_DP_TX_SW_RESET */
+#define RESET_DP_TX				(0x1 << 0)
+
+/* EXYNOS_DP_FUNC_EN_1 */
+#define MASTER_VID_FUNC_EN_N			(0x1 << 7)
+#define SLAVE_VID_FUNC_EN_N			(0x1 << 5)
+#define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
+#define AUD_FUNC_EN_N				(0x1 << 3)
+#define HDCP_FUNC_EN_N				(0x1 << 2)
+#define CRC_FUNC_EN_N				(0x1 << 1)
+#define SW_FUNC_EN_N				(0x1 << 0)
+
+/* EXYNOS_DP_FUNC_EN_2 */
+#define SSC_FUNC_EN_N				(0x1 << 7)
+#define AUX_FUNC_EN_N				(0x1 << 2)
+#define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
+#define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_1 */
+#define VIDEO_EN				(0x1 << 7)
+#define HDCP_VIDEO_MUTE				(0x1 << 6)
+
+/* EXYNOS_DP_VIDEO_CTL_1 */
+#define IN_D_RANGE_MASK				(0x1 << 7)
+#define IN_D_RANGE_SHIFT			(7)
+#define IN_D_RANGE_CEA				(0x1 << 7)
+#define IN_D_RANGE_VESA				(0x0 << 7)
+#define IN_BPC_MASK				(0x7 << 4)
+#define IN_BPC_SHIFT				(4)
+#define IN_BPC_12_BITS				(0x3 << 4)
+#define IN_BPC_10_BITS				(0x2 << 4)
+#define IN_BPC_8_BITS				(0x1 << 4)
+#define IN_BPC_6_BITS				(0x0 << 4)
+#define IN_COLOR_F_MASK				(0x3 << 0)
+#define IN_COLOR_F_SHIFT			(0)
+#define IN_COLOR_F_YCBCR444			(0x2 << 0)
+#define IN_COLOR_F_YCBCR422			(0x1 << 0)
+#define IN_COLOR_F_RGB				(0x0 << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_3 */
+#define IN_YC_COEFFI_MASK			(0x1 << 7)
+#define IN_YC_COEFFI_SHIFT			(7)
+#define IN_YC_COEFFI_ITU709			(0x1 << 7)
+#define IN_YC_COEFFI_ITU601			(0x0 << 7)
+#define VID_CHK_UPDATE_TYPE_MASK		(0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_SHIFT		(4)
+#define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
+#define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
+
+/* EXYNOS_DP_VIDEO_CTL_8 */
+#define VID_HRES_TH(x)				(((x) & 0xf) << 4)
+#define VID_VRES_TH(x)				(((x) & 0xf) << 0)
+
+/* EXYNOS_DP_VIDEO_CTL_10 */
+#define FORMAT_SEL				(0x1 << 4)
+#define INTERACE_SCAN_CFG			(0x1 << 2)
+#define VSYNC_POLARITY_CFG			(0x1 << 1)
+#define HSYNC_POLARITY_CFG			(0x1 << 0)
+
+/* EXYNOS_DP_LANE_MAP */
+#define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
+#define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
+#define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
+#define LANE3_MAP_LOGIC_LANE_3			(0x3 << 6)
+#define LANE2_MAP_LOGIC_LANE_0			(0x0 << 4)
+#define LANE2_MAP_LOGIC_LANE_1			(0x1 << 4)
+#define LANE2_MAP_LOGIC_LANE_2			(0x2 << 4)
+#define LANE2_MAP_LOGIC_LANE_3			(0x3 << 4)
+#define LANE1_MAP_LOGIC_LANE_0			(0x0 << 2)
+#define LANE1_MAP_LOGIC_LANE_1			(0x1 << 2)
+#define LANE1_MAP_LOGIC_LANE_2			(0x2 << 2)
+#define LANE1_MAP_LOGIC_LANE_3			(0x3 << 2)
+#define LANE0_MAP_LOGIC_LANE_0			(0x0 << 0)
+#define LANE0_MAP_LOGIC_LANE_1			(0x1 << 0)
+#define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
+#define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
+
+/* EXYNOS_DP_ANALOG_CTL_1 */
+#define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
+
+/* EXYNOS_DP_ANALOG_CTL_2 */
+#define SEL_24M					(0x1 << 3)
+#define TX_DVDD_BIT_1_0625V			(0x4 << 0)
+
+/* EXYNOS_DP_ANALOG_CTL_3 */
+#define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
+#define VCO_BIT_600_MICRO			(0x5 << 0)
+
+/* EXYNOS_DP_PLL_FILTER_CTL_1 */
+#define PD_RING_OSC				(0x1 << 6)
+#define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
+#define TX_CUR1_2X				(0x1 << 2)
+#define TX_CUR_16_MA				(0x3 << 0)
+
+/* EXYNOS_DP_TX_AMP_TUNING_CTL */
+#define CH3_AMP_400_MV				(0x0 << 24)
+#define CH2_AMP_400_MV				(0x0 << 16)
+#define CH1_AMP_400_MV				(0x0 << 8)
+#define CH0_AMP_400_MV				(0x0 << 0)
+
+/* EXYNOS_DP_AUX_HW_RETRY_CTL */
+#define AUX_BIT_PERIOD_EXPECTED_DELAY(x)	(((x) & 0x7) << 8)
+#define AUX_HW_RETRY_INTERVAL_MASK		(0x3 << 3)
+#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS	(0x0 << 3)
+#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS	(0x1 << 3)
+#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS	(0x2 << 3)
+#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS	(0x3 << 3)
+#define AUX_HW_RETRY_COUNT_SEL(x)		(((x) & 0x7) << 0)
+
+/* EXYNOS_DP_COMMON_INT_STA_1 */
+#define VSYNC_DET				(0x1 << 7)
+#define PLL_LOCK_CHG				(0x1 << 6)
+#define SPDIF_ERR				(0x1 << 5)
+#define SPDIF_UNSTBL				(0x1 << 4)
+#define VID_FORMAT_CHG				(0x1 << 3)
+#define AUD_CLK_CHG				(0x1 << 2)
+#define VID_CLK_CHG				(0x1 << 1)
+#define SW_INT					(0x1 << 0)
+
+/* EXYNOS_DP_COMMON_INT_STA_2 */
+#define ENC_EN_CHG				(0x1 << 6)
+#define HW_BKSV_RDY				(0x1 << 3)
+#define HW_SHA_DONE				(0x1 << 2)
+#define HW_AUTH_STATE_CHG			(0x1 << 1)
+#define HW_AUTH_DONE				(0x1 << 0)
+
+/* EXYNOS_DP_COMMON_INT_STA_3 */
+#define AFIFO_UNDER				(0x1 << 7)
+#define AFIFO_OVER				(0x1 << 6)
+#define R0_CHK_FLAG				(0x1 << 5)
+
+/* EXYNOS_DP_COMMON_INT_STA_4 */
+#define PSR_ACTIVE				(0x1 << 7)
+#define PSR_INACTIVE				(0x1 << 6)
+#define SPDIF_BI_PHASE_ERR			(0x1 << 5)
+#define HOTPLUG_CHG				(0x1 << 2)
+#define HPD_LOST				(0x1 << 1)
+#define PLUG					(0x1 << 0)
+
+/* EXYNOS_DP_INT_STA */
+#define INT_HPD					(0x1 << 6)
+#define HW_TRAINING_FINISH			(0x1 << 5)
+#define RPLY_RECEIV				(0x1 << 1)
+#define AUX_ERR					(0x1 << 0)
+
+/* EXYNOS_DP_INT_CTL */
+#define SOFT_INT_CTRL				(0x1 << 2)
+#define INT_POL1				(0x1 << 1)
+#define INT_POL0				(0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_1 */
+#define DET_STA					(0x1 << 2)
+#define FORCE_DET				(0x1 << 1)
+#define DET_CTRL				(0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_2 */
+#define CHA_CRI(x)				(((x) & 0xf) << 4)
+#define CHA_STA					(0x1 << 2)
+#define FORCE_CHA				(0x1 << 1)
+#define CHA_CTRL				(0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_3 */
+#define HPD_STATUS				(0x1 << 6)
+#define F_HPD					(0x1 << 5)
+#define HPD_CTRL				(0x1 << 4)
+#define HDCP_RDY				(0x1 << 3)
+#define STRM_VALID				(0x1 << 2)
+#define F_VALID					(0x1 << 1)
+#define VALID_CTRL				(0x1 << 0)
+
+/* EXYNOS_DP_SYS_CTL_4 */
+#define FIX_M_AUD				(0x1 << 4)
+#define ENHANCED				(0x1 << 3)
+#define FIX_M_VID				(0x1 << 2)
+#define M_VID_UPDATE_CTRL			(0x3 << 0)
+
+/* EXYNOS_DP_TRAINING_PTN_SET */
+#define SCRAMBLER_TYPE				(0x1 << 9)
+#define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
+#define SCRAMBLING_DISABLE			(0x1 << 5)
+#define SCRAMBLING_ENABLE			(0x0 << 5)
+#define LINK_QUAL_PATTERN_SET_MASK		(0x3 << 2)
+#define LINK_QUAL_PATTERN_SET_PRBS7		(0x3 << 2)
+#define LINK_QUAL_PATTERN_SET_D10_2		(0x1 << 2)
+#define LINK_QUAL_PATTERN_SET_DISABLE		(0x0 << 2)
+#define SW_TRAINING_PATTERN_SET_MASK		(0x3 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN2		(0x2 << 0)
+#define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
+#define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
+
+/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
+#define PRE_EMPHASIS_SET_MASK			(0x3 << 3)
+#define PRE_EMPHASIS_SET_SHIFT			(3)
+
+/* EXYNOS_DP_DEBUG_CTL */
+#define PLL_LOCK				(0x1 << 4)
+#define F_PLL_LOCK				(0x1 << 3)
+#define PLL_LOCK_CTRL				(0x1 << 2)
+#define PN_INV					(0x1 << 0)
+
+/* EXYNOS_DP_PLL_CTL */
+#define DP_PLL_PD				(0x1 << 7)
+#define DP_PLL_RESET				(0x1 << 6)
+#define DP_PLL_LOOP_BIT_DEFAULT			(0x1 << 4)
+#define DP_PLL_REF_BIT_1_1250V			(0x5 << 0)
+#define DP_PLL_REF_BIT_1_2500V			(0x7 << 0)
+
+/* EXYNOS_DP_PHY_PD */
+#define DP_PHY_PD				(0x1 << 5)
+#define AUX_PD					(0x1 << 4)
+#define CH3_PD					(0x1 << 3)
+#define CH2_PD					(0x1 << 2)
+#define CH1_PD					(0x1 << 1)
+#define CH0_PD					(0x1 << 0)
+
+/* EXYNOS_DP_PHY_TEST */
+#define MACRO_RST				(0x1 << 5)
+#define CH1_TEST				(0x1 << 1)
+#define CH0_TEST				(0x1 << 0)
+
+/* EXYNOS_DP_AUX_CH_STA */
+#define AUX_BUSY				(0x1 << 4)
+#define AUX_STATUS_MASK				(0xf << 0)
+
+/* EXYNOS_DP_AUX_CH_DEFER_CTL */
+#define DEFER_CTRL_EN				(0x1 << 7)
+#define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
+
+/* EXYNOS_DP_AUX_RX_COMM */
+#define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
+#define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
+
+/* EXYNOS_DP_BUFFER_DATA_CTL */
+#define BUF_CLR					(0x1 << 7)
+#define BUF_DATA_COUNT(x)			(((x) & 0x1f) << 0)
+
+/* EXYNOS_DP_AUX_CH_CTL_1 */
+#define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
+#define AUX_TX_COMM_MASK			(0xf << 0)
+#define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
+#define AUX_TX_COMM_I2C_TRANSACTION		(0x0 << 3)
+#define AUX_TX_COMM_MOT				(0x1 << 2)
+#define AUX_TX_COMM_WRITE			(0x0 << 0)
+#define AUX_TX_COMM_READ			(0x1 << 0)
+
+/* EXYNOS_DP_AUX_ADDR_7_0 */
+#define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
+
+/* EXYNOS_DP_AUX_ADDR_15_8 */
+#define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
+
+/* EXYNOS_DP_AUX_ADDR_19_16 */
+#define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
+
+/* EXYNOS_DP_AUX_CH_CTL_2 */
+#define ADDR_ONLY				(0x1 << 1)
+#define AUX_EN					(0x1 << 0)
+
+/* EXYNOS_DP_SOC_GENERAL_CTL */
+#define AUDIO_MODE_SPDIF_MODE			(0x1 << 8)
+#define AUDIO_MODE_MASTER_MODE			(0x0 << 8)
+#define MASTER_VIDEO_INTERLACE_EN		(0x1 << 4)
+#define VIDEO_MASTER_CLK_SEL			(0x1 << 2)
+#define VIDEO_MASTER_MODE_EN			(0x1 << 1)
+#define VIDEO_MODE_MASK				(0x1 << 0)
+#define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
+#define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
+
+#endif /* _ANALOGIX_DP_REG_H */
diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
index f17d392..2fadd82 100644
--- a/drivers/gpu/drm/exynos/Kconfig
+++ b/drivers/gpu/drm/exynos/Kconfig
@@ -71,8 +71,9 @@ config DRM_EXYNOS_DSI
 	  This enables support for Exynos MIPI-DSI device.
 
 config DRM_EXYNOS_DP
-	bool "Display Port"
+	bool "EXYNOS specific extensions for Analogix DP driver"
 	depends on DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON
+	select DRM_ANALOGIX_DP
 	default DRM_EXYNOS
 	select DRM_PANEL
 	help
diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
index 968b31c..2bdd949 100644
--- a/drivers/gpu/drm/exynos/Makefile
+++ b/drivers/gpu/drm/exynos/Makefile
@@ -12,7 +12,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON)	+= exynos5433_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON)	+= exynos7_drm_decon.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DPI)	+= exynos_drm_dpi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_DSI)	+= exynos_drm_dsi.o
-exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o exynos_dp_reg.o
+exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_MIXER)	+= exynos_mixer.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)	+= exynos_hdmi.o
 exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI)	+= exynos_drm_vidi.o
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index cff8dc7..8456794 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -14,967 +14,76 @@
 #include <linux/platform_device.h>
 #include <linux/err.h>
 #include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/interrupt.h>
-#include <linux/of.h>
-#include <linux/of_gpio.h>
 #include <linux/of_graph.h>
-#include <linux/gpio.h>
 #include <linux/component.h>
-#include <linux/phy/phy.h>
 #include <video/of_display_timing.h>
 #include <video/of_videomode.h>
+#include <video/videomode.h>
 
 #include <drm/drmP.h>
 #include <drm/drm_crtc.h>
 #include <drm/drm_crtc_helper.h>
-#include <drm/drm_atomic_helper.h>
 #include <drm/drm_panel.h>
 
-#include "exynos_dp_core.h"
+#include <drm/bridge/analogix_dp.h>
+#include <drm/exynos_drm.h>
+
 #include "exynos_drm_crtc.h"
 
-#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
-					connector)
+#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
 
-static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
-{
-	return to_exynos_crtc(dp->encoder.crtc);
-}
+struct exynos_dp_device {
+	struct drm_encoder         encoder;
+	struct drm_connector       connector;
+	struct drm_bridge          *ptn_bridge;
+	struct drm_device          *drm_dev;
+	struct device              *dev;
 
-static inline struct exynos_dp_device *encoder_to_dp(
-						struct drm_encoder *e)
-{
-	return container_of(e, struct exynos_dp_device, encoder);
-}
-
-struct bridge_init {
-	struct i2c_client *client;
-	struct device_node *node;
+	struct videomode           vm;
+	struct analogix_dp_plat_data plat_data;
 };
 
-static void exynos_dp_init_dp(struct exynos_dp_device *dp)
-{
-	exynos_dp_reset(dp);
-
-	exynos_dp_swreset(dp);
-
-	exynos_dp_init_analog_param(dp);
-	exynos_dp_init_interrupt(dp);
-
-	/* SW defined function Normal operation */
-	exynos_dp_enable_sw_function(dp);
-
-	exynos_dp_config_interrupt(dp);
-	exynos_dp_init_analog_func(dp);
-
-	exynos_dp_init_hpd(dp);
-	exynos_dp_init_aux(dp);
-}
-
-static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
-{
-	int timeout_loop = 0;
-
-	while (exynos_dp_get_plug_in_status(dp) != 0) {
-		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "failed to get hpd plug status\n");
-			return -ETIMEDOUT;
-		}
-		usleep_range(10, 11);
-	}
-
-	return 0;
-}
-
-static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
-{
-	int i;
-	unsigned char sum = 0;
-
-	for (i = 0; i < EDID_BLOCK_LENGTH; i++)
-		sum = sum + edid_data[i];
-
-	return sum;
-}
-
-static int exynos_dp_read_edid(struct exynos_dp_device *dp)
-{
-	unsigned char edid[EDID_BLOCK_LENGTH * 2];
-	unsigned int extend_block = 0;
-	unsigned char sum;
-	unsigned char test_vector;
-	int retval;
-
-	/*
-	 * EDID device address is 0x50.
-	 * However, if necessary, you must have set upper address
-	 * into E-EDID in I2C device, 0x30.
-	 */
-
-	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
-	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-				EDID_EXTENSION_FLAG,
-				&extend_block);
-	if (retval)
-		return retval;
-
-	if (extend_block > 0) {
-		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
-
-		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-						EDID_HEADER_PATTERN,
-						EDID_BLOCK_LENGTH,
-						&edid[EDID_HEADER_PATTERN]);
-		if (retval != 0) {
-			dev_err(dp->dev, "EDID Read failed!\n");
-			return -EIO;
-		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
-		if (sum != 0) {
-			dev_err(dp->dev, "EDID bad checksum!\n");
-			return -EIO;
-		}
-
-		/* Read additional EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_BLOCK_LENGTH,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_BLOCK_LENGTH]);
-		if (retval != 0) {
-			dev_err(dp->dev, "EDID Read failed!\n");
-			return -EIO;
-		}
-		sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
-		if (sum != 0) {
-			dev_err(dp->dev, "EDID bad checksum!\n");
-			return -EIO;
-		}
-
-		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					&test_vector);
-		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
-		}
-	} else {
-		dev_info(dp->dev, "EDID data does not include any extensions.\n");
-
-		/* Read EDID data */
-		retval = exynos_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_HEADER_PATTERN,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_HEADER_PATTERN]);
-		if (retval != 0) {
-			dev_err(dp->dev, "EDID Read failed!\n");
-			return -EIO;
-		}
-		sum = exynos_dp_calc_edid_check_sum(edid);
-		if (sum != 0) {
-			dev_err(dp->dev, "EDID bad checksum!\n");
-			return -EIO;
-		}
-
-		exynos_dp_read_byte_from_dpcd(dp,
-			DP_TEST_REQUEST,
-			&test_vector);
-		if (test_vector & DP_TEST_LINK_EDID_READ) {
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
-			exynos_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
-		}
-	}
-
-	dev_dbg(dp->dev, "EDID Read success!\n");
-	return 0;
-}
-
-static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
-{
-	u8 buf[12];
-	int i;
-	int retval;
-
-	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
-				12, buf);
-	if (retval)
-		return retval;
-
-	/* Read EDID */
-	for (i = 0; i < 3; i++) {
-		retval = exynos_dp_read_edid(dp);
-		if (!retval)
-			break;
-	}
-
-	return retval;
-}
-
-static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
-						bool enable)
-{
-	u8 data;
-
-	exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
-
-	if (enable)
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DP_LANE_COUNT_ENHANCED_FRAME_EN |
-			DPCD_LANE_COUNT_SET(data));
-	else
-		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DPCD_LANE_COUNT_SET(data));
-}
-
-static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
-{
-	u8 data;
-	int retval;
-
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
-	retval = DPCD_ENHANCED_FRAME_CAP(data);
-
-	return retval;
-}
-
-static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
-{
-	u8 data;
-
-	data = exynos_dp_is_enhanced_mode_available(dp);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, data);
-	exynos_dp_enable_enhanced_mode(dp, data);
-}
-
-static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
-{
-	exynos_dp_set_training_pattern(dp, DP_NONE);
-
-	exynos_dp_write_byte_to_dpcd(dp,
-		DP_TRAINING_PATTERN_SET,
-		DP_TRAINING_PATTERN_DISABLE);
-}
-
-static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
-					int pre_emphasis, int lane)
-{
-	switch (lane) {
-	case 0:
-		exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
-		break;
-	case 1:
-		exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
-		break;
-
-	case 2:
-		exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
-		break;
-
-	case 3:
-		exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
-		break;
-	}
-}
-
-static int exynos_dp_link_start(struct exynos_dp_device *dp)
-{
-	u8 buf[4];
-	int lane, lane_count, pll_tries, retval;
-
-	lane_count = dp->link_train.lane_count;
-
-	dp->link_train.lt_state = CLOCK_RECOVERY;
-	dp->link_train.eq_loop = 0;
-
-	for (lane = 0; lane < lane_count; lane++)
-		dp->link_train.cr_loop[lane] = 0;
-
-	/* Set link rate and count as you want to establish*/
-	exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
-	exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
-
-	/* Setup RX configuration */
-	buf[0] = dp->link_train.link_rate;
-	buf[1] = dp->link_train.lane_count;
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
-				2, buf);
-	if (retval)
-		return retval;
-
-	/* Set TX pre-emphasis to minimum */
-	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_lane_pre_emphasis(dp,
-			PRE_EMPHASIS_LEVEL_0, lane);
-
-	/* Wait for PLL lock */
-	pll_tries = 0;
-	while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-		if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
-			dev_err(dp->dev, "Wait for PLL lock timed out\n");
-			return -ETIMEDOUT;
-		}
-
-		pll_tries++;
-		usleep_range(90, 120);
-	}
-
-	/* Set training pattern 1 */
-	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
-
-	/* Set RX training pattern */
-	retval = exynos_dp_write_byte_to_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
-	if (retval)
-		return retval;
-
-	for (lane = 0; lane < lane_count; lane++)
-		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
-			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
-
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, buf);
-
-	return retval;
-}
-
-static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
-{
-	int shift = (lane & 1) * 4;
-	u8 link_value = link_status[lane>>1];
-
-	return (link_value >> shift) & 0xf;
-}
-
-static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
-{
-	int lane;
-	u8 lane_status;
-
-	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
-		if ((lane_status & DP_LANE_CR_DONE) == 0)
-			return -EINVAL;
-	}
-	return 0;
-}
-
-static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				int lane_count)
+int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
+				bool enable)
 {
-	int lane;
-	u8 lane_status;
+	struct exynos_dp_device *dp = to_dp(plat_data);
+	struct drm_encoder *encoder = &dp->encoder;
+	struct exynos_drm_crtc *crtc;
 
-	if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
-		return -EINVAL;
+	if (!encoder)
+		return -1;
 
-	for (lane = 0; lane < lane_count; lane++) {
-		lane_status = exynos_dp_get_lane_status(link_status, lane);
-		lane_status &= DP_CHANNEL_EQ_BITS;
-		if (lane_status != DP_CHANNEL_EQ_BITS)
-			return -EINVAL;
-	}
+	crtc = to_exynos_crtc(encoder->crtc);
+	if (crtc && crtc->ops && crtc->ops->clock_enable)
+		crtc->ops->clock_enable(crtc, enable);
 
 	return 0;
 }
 
-static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							int lane)
-{
-	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
-
-	return (link_value >> shift) & 0x3;
-}
-
-static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
-					u8 adjust_request[2],
-					int lane)
-{
-	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
-
-	return ((link_value >> shift) & 0xc) >> 2;
-}
-
-static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
-					u8 training_lane_set, int lane)
-{
-	switch (lane) {
-	case 0:
-		exynos_dp_set_lane0_link_training(dp, training_lane_set);
-		break;
-	case 1:
-		exynos_dp_set_lane1_link_training(dp, training_lane_set);
-		break;
-
-	case 2:
-		exynos_dp_set_lane2_link_training(dp, training_lane_set);
-		break;
-
-	case 3:
-		exynos_dp_set_lane3_link_training(dp, training_lane_set);
-		break;
-	}
-}
-
-static unsigned int exynos_dp_get_lane_link_training(
-				struct exynos_dp_device *dp,
-				int lane)
-{
-	u32 reg;
-
-	switch (lane) {
-	case 0:
-		reg = exynos_dp_get_lane0_link_training(dp);
-		break;
-	case 1:
-		reg = exynos_dp_get_lane1_link_training(dp);
-		break;
-	case 2:
-		reg = exynos_dp_get_lane2_link_training(dp);
-		break;
-	case 3:
-		reg = exynos_dp_get_lane3_link_training(dp);
-		break;
-	default:
-		WARN_ON(1);
-		return 0;
-	}
-
-	return reg;
-}
-
-static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
-{
-	exynos_dp_training_pattern_dis(dp);
-	exynos_dp_set_enhanced_mode(dp);
-
-	dp->link_train.lt_state = FAILED;
-}
-
-static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
-					u8 adjust_request[2])
-{
-	int lane, lane_count;
-	u8 voltage_swing, pre_emphasis, training_lane;
-
-	lane_count = dp->link_train.lane_count;
-	for (lane = 0; lane < lane_count; lane++) {
-		voltage_swing = exynos_dp_get_adjust_request_voltage(
-						adjust_request, lane);
-		pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
-						adjust_request, lane);
-		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
-				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
-
-		if (voltage_swing == VOLTAGE_LEVEL_3)
-			training_lane |= DP_TRAIN_MAX_SWING_REACHED;
-		if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
-			training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
-
-		dp->link_train.training_lane[lane] = training_lane;
-	}
-}
-
-static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
-{
-	int lane, lane_count, retval;
-	u8 voltage_swing, pre_emphasis, training_lane;
-	u8 link_status[2], adjust_request[2];
-
-	usleep_range(100, 101);
-
-	lane_count = dp->link_train.lane_count;
-
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
-			DP_LANE0_1_STATUS, 2, link_status);
-	if (retval)
-		return retval;
-
-	retval =  exynos_dp_read_bytes_from_dpcd(dp,
-			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
-	if (retval)
-		return retval;
-
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
-		/* set training pattern 2 for EQ */
-		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
-
-		retval = exynos_dp_write_byte_to_dpcd(dp,
-				DP_TRAINING_PATTERN_SET,
-				DP_LINK_SCRAMBLING_DISABLE |
-				DP_TRAINING_PATTERN_2);
-		if (retval)
-			return retval;
-
-		dev_info(dp->dev, "Link Training Clock Recovery success\n");
-		dp->link_train.lt_state = EQUALIZER_TRAINING;
-	} else {
-		for (lane = 0; lane < lane_count; lane++) {
-			training_lane = exynos_dp_get_lane_link_training(
-							dp, lane);
-			voltage_swing = exynos_dp_get_adjust_request_voltage(
-							adjust_request, lane);
-			pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
-							adjust_request, lane);
-
-			if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
-					voltage_swing &&
-			    DPCD_PRE_EMPHASIS_GET(training_lane) ==
-					pre_emphasis)
-				dp->link_train.cr_loop[lane]++;
-
-			if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
-			    voltage_swing == VOLTAGE_LEVEL_3 ||
-			    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
-				dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
-					dp->link_train.cr_loop[lane],
-					voltage_swing, pre_emphasis);
-				exynos_dp_reduce_link_rate(dp);
-				return -EIO;
-			}
-		}
-	}
-
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
-
-	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
-			dp->link_train.training_lane[lane], lane);
-
-	retval = exynos_dp_write_bytes_to_dpcd(dp,
-			DP_TRAINING_LANE0_SET, lane_count,
-			dp->link_train.training_lane);
-	if (retval)
-		return retval;
-
-	return retval;
-}
-
-static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
-{
-	int lane, lane_count, retval;
-	u32 reg;
-	u8 link_align, link_status[2], adjust_request[2];
-
-	usleep_range(400, 401);
-
-	lane_count = dp->link_train.lane_count;
-
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
-			DP_LANE0_1_STATUS, 2, link_status);
-	if (retval)
-		return retval;
-
-	if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
-		exynos_dp_reduce_link_rate(dp);
-		return -EIO;
-	}
-
-	retval = exynos_dp_read_bytes_from_dpcd(dp,
-			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
-	if (retval)
-		return retval;
-
-	retval = exynos_dp_read_byte_from_dpcd(dp,
-			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
-	if (retval)
-		return retval;
-
-	exynos_dp_get_adjust_training_lane(dp, adjust_request);
-
-	if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
-		/* traing pattern Set to Normal */
-		exynos_dp_training_pattern_dis(dp);
-
-		dev_info(dp->dev, "Link Training success!\n");
-
-		exynos_dp_get_link_bandwidth(dp, &reg);
-		dp->link_train.link_rate = reg;
-		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
-			dp->link_train.link_rate);
-
-		exynos_dp_get_lane_count(dp, &reg);
-		dp->link_train.lane_count = reg;
-		dev_dbg(dp->dev, "final lane count = %.2x\n",
-			dp->link_train.lane_count);
-
-		/* set enhanced mode if available */
-		exynos_dp_set_enhanced_mode(dp);
-		dp->link_train.lt_state = FINISHED;
-
-		return 0;
-	}
-
-	/* not all locked */
-	dp->link_train.eq_loop++;
-
-	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
-		dev_err(dp->dev, "EQ Max loop\n");
-		exynos_dp_reduce_link_rate(dp);
-		return -EIO;
-	}
-
-	for (lane = 0; lane < lane_count; lane++)
-		exynos_dp_set_lane_link_training(dp,
-			dp->link_train.training_lane[lane], lane);
-
-	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, dp->link_train.training_lane);
-
-	return retval;
-}
-
-static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
-					u8 *bandwidth)
-{
-	u8 data;
-
-	/*
-	 * For DP rev.1.1, Maximum link rate of Main Link lanes
-	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
-	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
-	*bandwidth = data;
-}
-
-static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
-					u8 *lane_count)
-{
-	u8 data;
-
-	/*
-	 * For DP rev.1.1, Maximum number of Main Link lanes
-	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
-	 */
-	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
-	*lane_count = DPCD_MAX_LANE_COUNT(data);
-}
-
-static void exynos_dp_init_training(struct exynos_dp_device *dp,
-			enum link_lane_count_type max_lane,
-			enum link_rate_type max_rate)
-{
-	/*
-	 * MACRO_RST must be applied after the PLL_LOCK to avoid
-	 * the DP inter pair skew issue for at least 10 us
-	 */
-	exynos_dp_reset_macro(dp);
-
-	/* Initialize by reading RX's DPCD */
-	exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
-	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
-
-	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
-		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
-			dp->link_train.link_rate);
-		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
-	}
-
-	if (dp->link_train.lane_count == 0) {
-		dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
-			dp->link_train.lane_count);
-		dp->link_train.lane_count = (u8)LANE_COUNT1;
-	}
-
-	/* Setup TX lane count & rate */
-	if (dp->link_train.lane_count > max_lane)
-		dp->link_train.lane_count = max_lane;
-	if (dp->link_train.link_rate > max_rate)
-		dp->link_train.link_rate = max_rate;
-
-	/* All DP analog module power up */
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
-}
-
-static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
+static int exynos_dp_poweron(struct analogix_dp_plat_data *plat_data)
 {
-	int retval = 0, training_finished = 0;
-
-	dp->link_train.lt_state = START;
-
-	/* Process here */
-	while (!retval && !training_finished) {
-		switch (dp->link_train.lt_state) {
-		case START:
-			retval = exynos_dp_link_start(dp);
-			if (retval)
-				dev_err(dp->dev, "LT link start failed!\n");
-			break;
-		case CLOCK_RECOVERY:
-			retval = exynos_dp_process_clock_recovery(dp);
-			if (retval)
-				dev_err(dp->dev, "LT CR failed!\n");
-			break;
-		case EQUALIZER_TRAINING:
-			retval = exynos_dp_process_equalizer_training(dp);
-			if (retval)
-				dev_err(dp->dev, "LT EQ failed!\n");
-			break;
-		case FINISHED:
-			training_finished = 1;
-			break;
-		case FAILED:
-			return -EREMOTEIO;
-		}
-	}
-	if (retval)
-		dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
-
-	return retval;
+	return exynos_dp_crtc_clock_enable(plat_data, true);
 }
 
-static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
-				u32 count,
-				u32 bwtype)
+static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
 {
-	int i;
-	int retval;
-
-	for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
-		exynos_dp_init_training(dp, count, bwtype);
-		retval = exynos_dp_sw_link_training(dp);
-		if (retval == 0)
-			break;
-
-		usleep_range(100, 110);
-	}
-
-	return retval;
+	return exynos_dp_crtc_clock_enable(plat_data, false);
 }
 
-static int exynos_dp_config_video(struct exynos_dp_device *dp)
+static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data)
 {
-	int retval = 0;
-	int timeout_loop = 0;
-	int done_count = 0;
-
-	exynos_dp_config_video_slave_mode(dp);
-
-	exynos_dp_set_video_color_format(dp);
-
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-		dev_err(dp->dev, "PLL is not locked yet.\n");
-		return -EINVAL;
-	}
-
-	for (;;) {
-		timeout_loop++;
-		if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
-			break;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "Timeout of video streamclk ok\n");
-			return -ETIMEDOUT;
-		}
-
-		usleep_range(1, 2);
-	}
-
-	/* Set to use the register calculated M/N video */
-	exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
-
-	/* For video bist, Video timing must be generated by register */
-	exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
-
-	/* Disable video mute */
-	exynos_dp_enable_video_mute(dp, 0);
-
-	/* Configure video slave mode */
-	exynos_dp_enable_video_master(dp, 0);
-
-	timeout_loop = 0;
-
-	for (;;) {
-		timeout_loop++;
-		if (exynos_dp_is_video_stream_on(dp) == 0) {
-			done_count++;
-			if (done_count > 10)
-				break;
-		} else if (done_count) {
-			done_count = 0;
-		}
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "Timeout of video streamclk ok\n");
-			return -ETIMEDOUT;
-		}
-
-		usleep_range(1000, 1001);
-	}
-
-	if (retval != 0)
-		dev_err(dp->dev, "Video stream is not detected!\n");
-
-	return retval;
-}
-
-static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
-{
-	u8 data;
-
-	if (enable) {
-		exynos_dp_enable_scrambling(dp);
-
-		exynos_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
-	} else {
-		exynos_dp_disable_scrambling(dp);
-
-		exynos_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
-		exynos_dp_write_byte_to_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
-	}
-}
-
-static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
-{
-	struct exynos_dp_device *dp = arg;
-
-	enum dp_irq_type irq_type;
-
-	irq_type = exynos_dp_get_irq_type(dp);
-	switch (irq_type) {
-	case DP_IRQ_TYPE_HP_CABLE_IN:
-		dev_dbg(dp->dev, "Received irq - cable in\n");
-		schedule_work(&dp->hotplug_work);
-		exynos_dp_clear_hotplug_interrupts(dp);
-		break;
-	case DP_IRQ_TYPE_HP_CABLE_OUT:
-		dev_dbg(dp->dev, "Received irq - cable out\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
-		break;
-	case DP_IRQ_TYPE_HP_CHANGE:
-		/*
-		 * We get these change notifications once in a while, but there
-		 * is nothing we can do with them. Just ignore it for now and
-		 * only handle cable changes.
-		 */
-		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
-		exynos_dp_clear_hotplug_interrupts(dp);
-		break;
-	default:
-		dev_err(dp->dev, "Received irq - unknown type!\n");
-		break;
-	}
-	return IRQ_HANDLED;
-}
-
-static void exynos_dp_hotplug(struct work_struct *work)
-{
-	struct exynos_dp_device *dp;
-
-	dp = container_of(work, struct exynos_dp_device, hotplug_work);
-
-	if (dp->drm_dev)
-		drm_helper_hpd_irq_event(dp->drm_dev);
-}
-
-static void exynos_dp_commit(struct drm_encoder *encoder)
-{
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
-	int ret;
-
-	/* Keep the panel disabled while we configure video */
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel))
-			DRM_ERROR("failed to disable the panel\n");
-	}
-
-	ret = exynos_dp_detect_hpd(dp);
-	if (ret) {
-		/* Cable has been disconnected, we're done */
-		return;
-	}
-
-	ret = exynos_dp_handle_edid(dp);
-	if (ret) {
-		dev_err(dp->dev, "unable to handle edid\n");
-		return;
-	}
-
-	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
-					dp->video_info->link_rate);
-	if (ret) {
-		dev_err(dp->dev, "unable to do link train\n");
-		return;
-	}
-
-	exynos_dp_enable_scramble(dp, 1);
-	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
-	exynos_dp_enable_enhanced_mode(dp, 1);
-
-	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
-	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
-	exynos_dp_init_video(dp);
-	ret = exynos_dp_config_video(dp);
-	if (ret)
-		dev_err(dp->dev, "unable to config video\n");
-
-	/* Safe to enable the panel now */
-	if (dp->panel) {
-		if (drm_panel_enable(dp->panel))
-			DRM_ERROR("failed to enable the panel\n");
-	}
-
-	/* Enable video */
-	exynos_dp_start_video(dp);
-}
-
-static enum drm_connector_status exynos_dp_detect(
-				struct drm_connector *connector, bool force)
-{
-	return connector_status_connected;
-}
-
-static void exynos_dp_connector_destroy(struct drm_connector *connector)
-{
-	drm_connector_unregister(connector);
-	drm_connector_cleanup(connector);
-}
-
-static const struct drm_connector_funcs exynos_dp_connector_funcs = {
-	.dpms = drm_atomic_helper_connector_dpms,
-	.fill_modes = drm_helper_probe_single_connector_modes,
-	.detect = exynos_dp_detect,
-	.destroy = exynos_dp_connector_destroy,
-	.reset = drm_atomic_helper_connector_reset,
-	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
-	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
-};
-
-static int exynos_dp_get_modes(struct drm_connector *connector)
-{
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
+	struct exynos_dp_device *dp = to_dp(plat_data);
+	struct drm_connector *connector = &dp->connector;
 	struct drm_display_mode *mode;
+	int num_modes = 0;
 
-	if (dp->panel)
-		return drm_panel_get_modes(dp->panel);
+	if (dp->plat_data.panel)
+		return num_modes;
 
 	mode = drm_mode_create(connector->dev);
 	if (!mode) {
 		DRM_ERROR("failed to create a new display mode.\n");
-		return 0;
+		return num_modes;
 	}
 
 	drm_display_mode_from_videomode(&dp->vm, mode);
@@ -985,171 +94,31 @@ static int exynos_dp_get_modes(struct drm_connector *connector)
 	drm_mode_set_name(mode);
 	drm_mode_probed_add(connector, mode);
 
-	return 1;
-}
-
-static struct drm_encoder *exynos_dp_best_encoder(
-			struct drm_connector *connector)
-{
-	struct exynos_dp_device *dp = ctx_from_connector(connector);
-
-	return &dp->encoder;
-}
-
-static const struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
-	.get_modes = exynos_dp_get_modes,
-	.best_encoder = exynos_dp_best_encoder,
-};
-
-/* returns the number of bridges attached */
-static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
-		struct drm_encoder *encoder)
-{
-	int ret;
-
-	encoder->bridge->next = dp->ptn_bridge;
-	dp->ptn_bridge->encoder = encoder;
-	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
-	if (ret) {
-		DRM_ERROR("Failed to attach bridge to drm\n");
-		return ret;
-	}
-
-	return 0;
+	return num_modes + 1;
 }
 
-static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
+static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+				   struct drm_bridge *bridge,
+				   struct drm_connector *connector)
 {
-	struct exynos_dp_device *dp = bridge->driver_private;
+	struct exynos_dp_device *dp = to_dp(plat_data);
 	struct drm_encoder *encoder = &dp->encoder;
-	struct drm_connector *connector = &dp->connector;
 	int ret;
 
-	/* Pre-empt DP connector creation if there's a bridge */
-	if (dp->ptn_bridge) {
-		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
-		if (!ret)
-			return 0;
-	}
-
-	connector->polled = DRM_CONNECTOR_POLL_HPD;
-
-	ret = drm_connector_init(dp->drm_dev, connector,
-			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
-	if (ret) {
-		DRM_ERROR("Failed to initialize connector with drm\n");
-		return ret;
-	}
-
-	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
 	drm_connector_register(connector);
-	drm_mode_connector_attach_encoder(connector, encoder);
-
-	if (dp->panel)
-		ret = drm_panel_attach(dp->panel, &dp->connector);
-
-	return ret;
-}
-
-static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
-{
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
-
-	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
-		return;
-
-	pm_runtime_get_sync(dp->dev);
-
-	if (dp->panel) {
-		if (drm_panel_prepare(dp->panel)) {
-			DRM_ERROR("failed to setup the panel\n");
-			return;
-		}
-	}
-
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), true);
-
-	phy_power_on(dp->phy);
-	exynos_dp_init_dp(dp);
-	enable_irq(dp->irq);
-	exynos_dp_commit(&dp->encoder);
 
-	dp->dpms_mode = DRM_MODE_DPMS_ON;
-}
-
-static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
-{
-	struct exynos_dp_device *dp = bridge->driver_private;
-	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
-
-	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
-		return;
-
-	if (dp->panel) {
-		if (drm_panel_disable(dp->panel)) {
-			DRM_ERROR("failed to disable the panel\n");
-			return;
+	/* Pre-empt DP connector creation if there's a bridge */
+	if (dp->ptn_bridge) {
+		bridge->next = dp->ptn_bridge;
+		dp->ptn_bridge->encoder = encoder;
+		ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
+		if (ret) {
+			DRM_ERROR("Failed to attach bridge to drm\n");
+			bridge->next = NULL;
+			return ret;
 		}
 	}
 
-	disable_irq(dp->irq);
-	flush_work(&dp->hotplug_work);
-	phy_power_off(dp->phy);
-
-	if (crtc->ops->clock_enable)
-		crtc->ops->clock_enable(dp_to_crtc(dp), false);
-
-	if (dp->panel) {
-		if (drm_panel_unprepare(dp->panel))
-			DRM_ERROR("failed to turnoff the panel\n");
-	}
-
-	pm_runtime_put_sync(dp->dev);
-
-	dp->dpms_mode = DRM_MODE_DPMS_OFF;
-}
-
-static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
-{
-	/* do nothing */
-}
-
-static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
-	.enable = exynos_dp_bridge_enable,
-	.disable = exynos_dp_bridge_disable,
-	.pre_enable = exynos_dp_bridge_nop,
-	.post_disable = exynos_dp_bridge_nop,
-	.attach = exynos_dp_bridge_attach,
-};
-
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
-{
-	struct exynos_dp_device *dp = encoder_to_dp(encoder);
-	struct drm_device *drm_dev = dp->drm_dev;
-	struct drm_bridge *bridge;
-	int ret;
-
-	bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
-	if (!bridge) {
-		DRM_ERROR("failed to allocate for drm bridge\n");
-		return -ENOMEM;
-	}
-
-	dp->bridge = bridge;
-
-	encoder->bridge = bridge;
-	bridge->driver_private = dp;
-	bridge->encoder = encoder;
-	bridge->funcs = &exynos_dp_bridge_funcs;
-
-	ret = drm_bridge_attach(drm_dev, bridge);
-	if (ret) {
-		DRM_ERROR("failed to attach drm bridge\n");
-		return -EINVAL;
-	}
-
 	return 0;
 }
 
@@ -1159,82 +128,21 @@ static void exynos_dp_mode_set(struct drm_encoder *encoder,
 {
 }
 
-static void exynos_dp_enable(struct drm_encoder *encoder)
-{
-}
-
-static void exynos_dp_disable(struct drm_encoder *encoder)
+static void exynos_dp_nop(struct drm_encoder *encoder)
 {
+	/* do nothing */
 }
 
 static const struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
 	.mode_set = exynos_dp_mode_set,
-	.enable = exynos_dp_enable,
-	.disable = exynos_dp_disable,
+	.enable = exynos_dp_nop,
+	.disable = exynos_dp_nop,
 };
 
 static const struct drm_encoder_funcs exynos_dp_encoder_funcs = {
 	.destroy = drm_encoder_cleanup,
 };
 
-static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
-{
-	struct device_node *dp_node = dev->of_node;
-	struct video_info *dp_video_config;
-
-	dp_video_config = devm_kzalloc(dev,
-				sizeof(*dp_video_config), GFP_KERNEL);
-	if (!dp_video_config)
-		return ERR_PTR(-ENOMEM);
-
-	dp_video_config->h_sync_polarity =
-		of_property_read_bool(dp_node, "hsync-active-high");
-
-	dp_video_config->v_sync_polarity =
-		of_property_read_bool(dp_node, "vsync-active-high");
-
-	dp_video_config->interlaced =
-		of_property_read_bool(dp_node, "interlaced");
-
-	if (of_property_read_u32(dp_node, "samsung,color-space",
-				&dp_video_config->color_space)) {
-		dev_err(dev, "failed to get color-space\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				&dp_video_config->dynamic_range)) {
-		dev_err(dev, "failed to get dynamic-range\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				&dp_video_config->ycbcr_coeff)) {
-		dev_err(dev, "failed to get ycbcr-coeff\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				&dp_video_config->color_depth)) {
-		dev_err(dev, "failed to get color-depth\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				&dp_video_config->link_rate)) {
-		dev_err(dev, "failed to get link-rate\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				&dp_video_config->lane_count)) {
-		dev_err(dev, "failed to get lane-count\n");
-		return ERR_PTR(-EINVAL);
-	}
-
-	return dp_video_config;
-}
-
 static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
 {
 	int ret;
@@ -1250,97 +158,32 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
 static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 {
 	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-	struct platform_device *pdev = to_platform_device(dev);
-	struct drm_device *drm_dev = data;
 	struct drm_encoder *encoder = &dp->encoder;
-	struct resource *res;
-	unsigned int irq_flags;
-	int pipe, ret = 0;
+	struct drm_device *drm_dev = data;
+	int pipe, ret;
 
-	dp->dev = &pdev->dev;
-	dp->dpms_mode = DRM_MODE_DPMS_OFF;
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
 
-	dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
-	if (IS_ERR(dp->video_info))
-		return PTR_ERR(dp->video_info);
+	dp->dev = dev;
+	dp->drm_dev = drm_dev;
 
-	dp->phy = devm_phy_get(dp->dev, "dp");
-	if (IS_ERR(dp->phy)) {
-		dev_err(dp->dev, "no DP phy configured\n");
-		ret = PTR_ERR(dp->phy);
-		if (ret) {
-			/*
-			 * phy itself is not enabled, so we can move forward
-			 * assigning NULL to phy pointer.
-			 */
-			if (ret == -ENOSYS || ret == -ENODEV)
-				dp->phy = NULL;
-			else
-				return ret;
-		}
-	}
+	dp->plat_data.dev_type = EXYNOS_DP;
+	dp->plat_data.power_on = exynos_dp_poweron;
+	dp->plat_data.power_off = exynos_dp_poweroff;
+	dp->plat_data.attach = exynos_dp_bridge_attach;
+	dp->plat_data.get_modes = exynos_dp_get_modes;
 
-	if (!dp->panel && !dp->ptn_bridge) {
+	if (!dp->plat_data.panel && !dp->ptn_bridge) {
 		ret = exynos_dp_dt_parse_panel(dp);
 		if (ret)
 			return ret;
 	}
 
-	dp->clock = devm_clk_get(&pdev->dev, "dp");
-	if (IS_ERR(dp->clock)) {
-		dev_err(&pdev->dev, "failed to get clock\n");
-		return PTR_ERR(dp->clock);
-	}
-
-	clk_prepare_enable(dp->clock);
-
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-
-	dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
-	if (IS_ERR(dp->reg_base))
-		return PTR_ERR(dp->reg_base);
-
-	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		/*
-		 * Set up the hotplug GPIO from the device tree as an interrupt.
-		 * Simply specifying a different interrupt in the device tree
-		 * doesn't work since we handle hotplug rather differently when
-		 * using a GPIO.  We also need the actual GPIO specifier so
-		 * that we can get the current state of the GPIO.
-		 */
-		ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
-					    "hpd_gpio");
-		if (ret) {
-			dev_err(&pdev->dev, "failed to get hpd gpio\n");
-			return ret;
-		}
-		dp->irq = gpio_to_irq(dp->hpd_gpio);
-		irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
-	} else {
-		dp->hpd_gpio = -ENODEV;
-		dp->irq = platform_get_irq(pdev, 0);
-		irq_flags = 0;
-	}
-
-	if (dp->irq == -ENXIO) {
-		dev_err(&pdev->dev, "failed to get irq\n");
-		return -ENODEV;
-	}
-
-	INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
-
-	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
-			irq_flags, "exynos-dp", dp);
-	if (ret) {
-		dev_err(&pdev->dev, "failed to request irq\n");
-		return ret;
-	}
-	disable_irq(dp->irq);
-
-	dp->drm_dev = drm_dev;
-
 	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
 						  EXYNOS_DISPLAY_TYPE_LCD);
 	if (pipe < 0)
@@ -1355,22 +198,15 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 
 	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
 
-	ret = exynos_dp_create_connector(encoder);
-	if (ret) {
-		DRM_ERROR("failed to create connector ret = %d\n", ret);
-		drm_encoder_cleanup(encoder);
-		return ret;
-	}
+	dp->plat_data.encoder = encoder;
 
-	return 0;
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
 }
 
 static void exynos_dp_unbind(struct device *dev, struct device *master,
 				void *data)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-
-	exynos_dp_disable(&dp->encoder);
+	return analogix_dp_unbind(dev, master, data);
 }
 
 static const struct component_ops exynos_dp_ops = {
@@ -1383,21 +219,25 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct device_node *np = NULL, *endpoint = NULL;
 	struct exynos_dp_device *dp;
-	int ret;
 
 	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
 				GFP_KERNEL);
 	if (!dp)
 		return -ENOMEM;
 
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver would take charge of the drvdata.
+	 */
 	platform_set_drvdata(pdev, dp);
 
 	/* This is for the backward compatibility. */
 	np = of_parse_phandle(dev->of_node, "panel", 0);
 	if (np) {
-		dp->panel = of_drm_find_panel(np);
+		dp->plat_data.panel = of_drm_find_panel(np);
 		of_node_put(np);
-		if (!dp->panel)
+		if (!dp->plat_data.panel)
 			return -EPROBE_DEFER;
 		goto out;
 	}
@@ -1407,8 +247,8 @@ static int exynos_dp_probe(struct platform_device *pdev)
 		np = of_graph_get_remote_port_parent(endpoint);
 		if (np) {
 			/* The remote port can be either a panel or a bridge */
-			dp->panel = of_drm_find_panel(np);
-			if (!dp->panel) {
+			dp->plat_data.panel = of_drm_find_panel(np);
+			if (!dp->plat_data.panel) {
 				dp->ptn_bridge = of_drm_find_bridge(np);
 				if (!dp->ptn_bridge) {
 					of_node_put(np);
@@ -1426,23 +266,11 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	}
 
 out:
-	pm_runtime_enable(dev);
-
-	ret = component_add(&pdev->dev, &exynos_dp_ops);
-	if (ret)
-		goto err_disable_pm_runtime;
-
-	return ret;
-
-err_disable_pm_runtime:
-	pm_runtime_disable(dev);
-
-	return ret;
+	return component_add(&pdev->dev, &exynos_dp_ops);
 }
 
 static int exynos_dp_remove(struct platform_device *pdev)
 {
-	pm_runtime_disable(&pdev->dev);
 	component_del(&pdev->dev, &exynos_dp_ops);
 
 	return 0;
@@ -1451,25 +279,12 @@ static int exynos_dp_remove(struct platform_device *pdev)
 #ifdef CONFIG_PM
 static int exynos_dp_suspend(struct device *dev)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-
-	clk_disable_unprepare(dp->clock);
-
-	return 0;
+	return analogix_dp_suspend(dev);
 }
 
 static int exynos_dp_resume(struct device *dev)
 {
-	struct exynos_dp_device *dp = dev_get_drvdata(dev);
-	int ret;
-
-	ret = clk_prepare_enable(dp->clock);
-	if (ret < 0) {
-		DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
-		return ret;
-	}
-
-	return 0;
+	return analogix_dp_resume(dev);
 }
 #endif
 
@@ -1495,5 +310,5 @@ struct platform_driver dp_driver = {
 };
 
 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
-MODULE_DESCRIPTION("Samsung SoC DP Driver");
+MODULE_DESCRIPTION("Samsung Specific Analogix-DP Driver Extension");
 MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
deleted file mode 100644
index b5c2d8f..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * Header file for Samsung DP (Display Port) interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#ifndef _EXYNOS_DP_CORE_H
-#define _EXYNOS_DP_CORE_H
-
-#include <drm/drm_crtc.h>
-#include <drm/drm_dp_helper.h>
-#include <drm/exynos_drm.h>
-#include <video/videomode.h>
-
-#include "exynos_drm_drv.h"
-
-#define DP_TIMEOUT_LOOP_COUNT 100
-#define MAX_CR_LOOP 5
-#define MAX_EQ_LOOP 5
-
-enum link_rate_type {
-	LINK_RATE_1_62GBPS = 0x06,
-	LINK_RATE_2_70GBPS = 0x0a
-};
-
-enum link_lane_count_type {
-	LANE_COUNT1 = 1,
-	LANE_COUNT2 = 2,
-	LANE_COUNT4 = 4
-};
-
-enum link_training_state {
-	START,
-	CLOCK_RECOVERY,
-	EQUALIZER_TRAINING,
-	FINISHED,
-	FAILED
-};
-
-enum voltage_swing_level {
-	VOLTAGE_LEVEL_0,
-	VOLTAGE_LEVEL_1,
-	VOLTAGE_LEVEL_2,
-	VOLTAGE_LEVEL_3,
-};
-
-enum pre_emphasis_level {
-	PRE_EMPHASIS_LEVEL_0,
-	PRE_EMPHASIS_LEVEL_1,
-	PRE_EMPHASIS_LEVEL_2,
-	PRE_EMPHASIS_LEVEL_3,
-};
-
-enum pattern_set {
-	PRBS7,
-	D10_2,
-	TRAINING_PTN1,
-	TRAINING_PTN2,
-	DP_NONE
-};
-
-enum color_space {
-	COLOR_RGB,
-	COLOR_YCBCR422,
-	COLOR_YCBCR444
-};
-
-enum color_depth {
-	COLOR_6,
-	COLOR_8,
-	COLOR_10,
-	COLOR_12
-};
-
-enum color_coefficient {
-	COLOR_YCBCR601,
-	COLOR_YCBCR709
-};
-
-enum dynamic_range {
-	VESA,
-	CEA
-};
-
-enum pll_status {
-	PLL_UNLOCKED,
-	PLL_LOCKED
-};
-
-enum clock_recovery_m_value_type {
-	CALCULATED_M,
-	REGISTER_M
-};
-
-enum video_timing_recognition_type {
-	VIDEO_TIMING_FROM_CAPTURE,
-	VIDEO_TIMING_FROM_REGISTER
-};
-
-enum analog_power_block {
-	AUX_BLOCK,
-	CH0_BLOCK,
-	CH1_BLOCK,
-	CH2_BLOCK,
-	CH3_BLOCK,
-	ANALOG_TOTAL,
-	POWER_ALL
-};
-
-enum dp_irq_type {
-	DP_IRQ_TYPE_HP_CABLE_IN,
-	DP_IRQ_TYPE_HP_CABLE_OUT,
-	DP_IRQ_TYPE_HP_CHANGE,
-	DP_IRQ_TYPE_UNKNOWN,
-};
-
-struct video_info {
-	char *name;
-
-	bool h_sync_polarity;
-	bool v_sync_polarity;
-	bool interlaced;
-
-	enum color_space color_space;
-	enum dynamic_range dynamic_range;
-	enum color_coefficient ycbcr_coeff;
-	enum color_depth color_depth;
-
-	enum link_rate_type link_rate;
-	enum link_lane_count_type lane_count;
-};
-
-struct link_train {
-	int eq_loop;
-	int cr_loop[4];
-
-	u8 link_rate;
-	u8 lane_count;
-	u8 training_lane[4];
-
-	enum link_training_state lt_state;
-};
-
-struct exynos_dp_device {
-	struct drm_encoder	encoder;
-	struct device		*dev;
-	struct drm_device	*drm_dev;
-	struct drm_connector	connector;
-	struct drm_panel	*panel;
-	struct drm_bridge	*bridge;
-	struct drm_bridge	*ptn_bridge;
-	struct clk		*clock;
-	unsigned int		irq;
-	void __iomem		*reg_base;
-
-	struct video_info	*video_info;
-	struct link_train	link_train;
-	struct work_struct	hotplug_work;
-	struct phy		*phy;
-	int			dpms_mode;
-	int			hpd_gpio;
-	struct videomode	vm;
-};
-
-/* exynos_dp_reg.c */
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_stop_video(struct exynos_dp_device *dp);
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
-void exynos_dp_reset(struct exynos_dp_device *dp);
-void exynos_dp_swreset(struct exynos_dp_device *dp);
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable);
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
-void exynos_dp_init_hpd(struct exynos_dp_device *dp);
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
-void exynos_dp_reset_aux(struct exynos_dp_device *dp);
-void exynos_dp_init_aux(struct exynos_dp_device *dp);
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern);
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-				u32 training_lane);
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
-void exynos_dp_reset_macro(struct exynos_dp_device *dp);
-void exynos_dp_init_video(struct exynos_dp_device *dp);
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
-void exynos_dp_start_video(struct exynos_dp_device *dp);
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR			0x50
-#define I2C_E_EDID_DEVICE_ADDR			0x30
-
-#define EDID_BLOCK_LENGTH			0x80
-#define EDID_HEADER_PATTERN			0x00
-#define EDID_EXTENSION_FLAG			0x7e
-#define EDID_CHECKSUM				0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
-
-#endif /* _EXYNOS_DP_CORE_H */
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
deleted file mode 100644
index c1f87a2..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
+++ /dev/null
@@ -1,1263 +0,0 @@
-/*
- * Samsung DP (Display port) register interface driver.
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-
-#include <linux/device.h>
-#include <linux/io.h>
-#include <linux/delay.h>
-#include <linux/gpio.h>
-
-#include "exynos_dp_core.h"
-#include "exynos_dp_reg.h"
-
-#define COMMON_INT_MASK_1	0
-#define COMMON_INT_MASK_2	0
-#define COMMON_INT_MASK_3	0
-#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
-#define INT_STA_MASK		INT_HPD
-
-void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg |= HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-		reg &= ~HDCP_VIDEO_MUTE;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	}
-}
-
-void exynos_dp_stop_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg &= ~VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable)
-		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
-	else
-		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
-
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
-}
-
-void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = TX_TERMINAL_CTRL_50_OHM;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
-
-	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
-
-	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
-	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
-
-	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
-		TX_CUR1_2X | TX_CUR_16_MA;
-	writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
-
-	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
-		CH1_AMP_400_MV | CH0_AMP_400_MV;
-	writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
-}
-
-void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
-{
-	/* Set interrupt pin assertion polarity as high */
-	writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
-
-	/* Clear pending regisers */
-	writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-	writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
-	writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
-	writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-	writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* 0:mask,1: unmask */
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-	writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-void exynos_dp_reset(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	exynos_dp_stop_video(dp);
-	exynos_dp_enable_video_mute(dp, 0);
-
-	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
-		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
-		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
-		SERDES_FIFO_FUNC_EN_N |
-		LS_CLK_DOMAIN_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-
-	usleep_range(20, 30);
-
-	exynos_dp_lane_swap(dp, 0);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
-	writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
-
-	writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
-	writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
-
-	writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
-	writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
-
-	writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
-	writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
-
-	writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_swreset(struct exynos_dp_device *dp)
-{
-	writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
-}
-
-void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* 0: mask, 1: unmask */
-	reg = COMMON_INT_MASK_1;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
-
-	reg = COMMON_INT_MASK_2;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
-
-	reg = COMMON_INT_MASK_3;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
-
-	reg = COMMON_INT_MASK_4;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
-
-	reg = INT_STA_MASK;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
-}
-
-enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	if (reg & PLL_LOCK)
-		return PLL_LOCKED;
-	else
-		return PLL_UNLOCKED;
-}
-
-void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg |= DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
-		reg &= ~DP_PLL_PD;
-		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
-	}
-}
-
-void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
-{
-	u32 reg;
-
-	switch (block) {
-	case AUX_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~AUX_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH0_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH1_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH1_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH2_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH2_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case CH3_BLOCK:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~CH3_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case ANALOG_TOTAL:
-		if (enable) {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg |= DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
-			reg &= ~DP_PHY_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	case POWER_ALL:
-		if (enable) {
-			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
-				CH1_PD | CH0_PD;
-			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
-		} else {
-			writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
-{
-	u32 reg;
-	int timeout_loop = 0;
-
-	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
-
-	reg = PLL_LOCK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
-
-	/* Power up PLL */
-	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-		exynos_dp_set_pll_power_down(dp, 0);
-
-		while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
-			timeout_loop++;
-			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-				dev_err(dp->dev, "failed to get pll lock status\n");
-				return;
-			}
-			usleep_range(10, 20);
-		}
-	}
-
-	/* Enable Serdes FIFO function and Link symbol clock domain module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
-		| AUX_FUNC_EN_N);
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-	reg = INT_HPD;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-}
-
-void exynos_dp_init_hpd(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio))
-		return;
-
-	exynos_dp_clear_hotplug_interrupts(dp);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	reg &= ~(F_HPD | HPD_CTRL);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-}
-
-enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		reg = gpio_get_value(dp->hpd_gpio);
-		if (reg)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-		else
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-	} else {
-		/* Parse hotplug interrupt status register */
-		reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
-
-		if (reg & PLUG)
-			return DP_IRQ_TYPE_HP_CABLE_IN;
-
-		if (reg & HPD_LOST)
-			return DP_IRQ_TYPE_HP_CABLE_OUT;
-
-		if (reg & HOTPLUG_CHG)
-			return DP_IRQ_TYPE_HP_CHANGE;
-
-		return DP_IRQ_TYPE_UNKNOWN;
-	}
-}
-
-void exynos_dp_reset_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Disable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg |= AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-void exynos_dp_init_aux(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Clear inerrupts related to AUX channel */
-	reg = RPLY_RECEIV | AUX_ERR;
-	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	exynos_dp_reset_aux(dp);
-
-	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
-
-	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
-	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
-
-	/* Enable AUX channel module */
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-	reg &= ~AUX_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
-}
-
-int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	if (gpio_is_valid(dp->hpd_gpio)) {
-		if (gpio_get_value(dp->hpd_gpio))
-			return 0;
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-		if (reg & HPD_STATUS)
-			return 0;
-	}
-
-	return -EINVAL;
-}
-
-void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~SW_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-}
-
-int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
-{
-	int reg;
-	int retval = 0;
-	int timeout_loop = 0;
-
-	/* Enable AUX CH operation */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-	reg |= AUX_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-	/* Is AUX CH command reply received? */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	while (!(reg & RPLY_RECEIV)) {
-		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
-			dev_err(dp->dev, "AUX CH command reply failed!\n");
-			return -ETIMEDOUT;
-		}
-		reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-		usleep_range(10, 11);
-	}
-
-	/* Clear interrupt source for AUX CH command reply */
-	writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
-
-	/* Clear interrupt source for AUX CH access error */
-	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
-	if (reg & AUX_ERR) {
-		writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
-		return -EREMOTEIO;
-	}
-
-	/* Check AUX CH error access status */
-	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
-	if ((reg & AUX_STATUS_MASK) != 0) {
-		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
-			reg & AUX_STATUS_MASK);
-		return -EREMOTEIO;
-	}
-
-	return retval;
-}
-
-int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/* Write data buffer */
-		reg = (unsigned int)data;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-		/*
-		 * Set DisplayPort transaction and write 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select DPCD device address */
-		reg = AUX_ADDR_7_0(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-		reg = AUX_ADDR_15_8(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-		reg = AUX_ADDR_19_16(reg_addr);
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-		/*
-		 * Set DisplayPort transaction and read 1 byte
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	/* Read data buffer */
-	reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-	*data = (unsigned char)(reg & 0xff);
-
-	return retval;
-}
-
-int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-			     cur_data_idx++) {
-				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
-			}
-
-			/*
-			 * Set DisplayPort transaction and write
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
-{
-	u32 reg;
-	unsigned int start_offset;
-	unsigned int cur_data_count;
-	unsigned int cur_data_idx;
-	int i;
-	int retval = 0;
-
-	/* Clear AUX CH data buffer */
-	reg = BUF_CLR;
-	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-	start_offset = 0;
-	while (start_offset < count) {
-		/* Buffer size of AUX CH is 16 * 4bytes */
-		if ((count - start_offset) > 16)
-			cur_data_count = 16;
-		else
-			cur_data_count = count - start_offset;
-
-		/* AUX CH Request Transaction process */
-		for (i = 0; i < 3; i++) {
-			/* Select DPCD device address */
-			reg = AUX_ADDR_7_0(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-			reg = AUX_ADDR_15_8(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-			reg = AUX_ADDR_19_16(reg_addr + start_offset);
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-			/*
-			 * Set DisplayPort transaction and read
-			 * If bit 3 is 1, DisplayPort transaction.
-			 * If Bit 3 is 0, I2C transaction.
-			 */
-			reg = AUX_LENGTH(cur_data_count) |
-				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-			/* Start AUX transaction */
-			retval = exynos_dp_start_aux_transaction(dp);
-			if (retval == 0)
-				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
-		    cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			data[start_offset + cur_data_idx] =
-				(unsigned char)reg;
-		}
-
-		start_offset += cur_data_count;
-	}
-
-	return retval;
-}
-
-int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
-{
-	u32 reg;
-	int retval;
-
-	/* Set EDID device address */
-	reg = device_addr;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
-	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
-
-	/* Set offset from base address of EDID device */
-	writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	/*
-	 * Set I2C transaction and write address
-	 * If bit 3 is 1, DisplayPort transaction.
-	 * If Bit 3 is 0, I2C transaction.
-	 */
-	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
-		AUX_TX_COMM_WRITE;
-	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-	/* Start AUX transaction */
-	retval = exynos_dp_start_aux_transaction(dp);
-	if (retval != 0)
-		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
-
-	return retval;
-}
-
-int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
-{
-	u32 reg;
-	int i;
-	int retval;
-
-	for (i = 0; i < 3; i++) {
-		/* Clear AUX CH data buffer */
-		reg = BUF_CLR;
-		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-		/* Select EDID device */
-		retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
-		if (retval != 0)
-			continue;
-
-		/*
-		 * Set I2C transaction and read data
-		 * If bit 3 is 1, DisplayPort transaction.
-		 * If Bit 3 is 0, I2C transaction.
-		 */
-		reg = AUX_TX_COMM_I2C_TRANSACTION |
-			AUX_TX_COMM_READ;
-		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
-
-		/* Start AUX transaction */
-		retval = exynos_dp_start_aux_transaction(dp);
-		if (retval == 0)
-			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
-	}
-
-	/* Read data */
-	if (retval == 0)
-		*data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
-
-	return retval;
-}
-
-int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
-{
-	u32 reg;
-	unsigned int i, j;
-	unsigned int cur_data_idx;
-	unsigned int defer = 0;
-	int retval = 0;
-
-	for (i = 0; i < count; i += 16) {
-		for (j = 0; j < 3; j++) {
-			/* Clear AUX CH data buffer */
-			reg = BUF_CLR;
-			writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
-
-			/* Set normal AUX CH command */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-			reg &= ~ADDR_ONLY;
-			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
-
-			/*
-			 * If Rx sends defer, Tx sends only reads
-			 * request without sending address
-			 */
-			if (!defer)
-				retval = exynos_dp_select_i2c_device(dp,
-						device_addr, reg_addr + i);
-			else
-				defer = 0;
-
-			if (retval == 0) {
-				/*
-				 * Set I2C transaction and write data
-				 * If bit 3 is 1, DisplayPort transaction.
-				 * If Bit 3 is 0, I2C transaction.
-				 */
-				reg = AUX_LENGTH(16) |
-					AUX_TX_COMM_I2C_TRANSACTION |
-					AUX_TX_COMM_READ;
-				writel(reg, dp->reg_base +
-					EXYNOS_DP_AUX_CH_CTL_1);
-
-				/* Start AUX transaction */
-				retval = exynos_dp_start_aux_transaction(dp);
-				if (retval == 0)
-					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
-			}
-			/* Check if Rx sends defer */
-			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
-			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
-				dev_err(dp->dev, "Defer: %d\n\n", reg);
-				defer = 1;
-			}
-		}
-
-		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
-			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
-						 + 4 * cur_data_idx);
-			edid[i + cur_data_idx] = (unsigned char)reg;
-		}
-	}
-
-	return retval;
-}
-
-void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
-{
-	u32 reg;
-
-	reg = bwtype;
-	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
-		writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-}
-
-void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
-	*bwtype = reg;
-}
-
-void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
-{
-	u32 reg;
-
-	reg = count;
-	writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-}
-
-void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
-	*count = reg;
-}
-
-void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~ENHANCED;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-	}
-}
-
-void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
-				 enum pattern_set pattern)
-{
-	u32 reg;
-
-	switch (pattern) {
-	case PRBS7:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case D10_2:
-		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN1:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case TRAINING_PTN2:
-		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	case DP_NONE:
-		reg = SCRAMBLING_ENABLE |
-			LINK_QUAL_PATTERN_SET_DISABLE |
-			SW_TRAINING_PATTERN_SET_NORMAL;
-		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-		break;
-	default:
-		break;
-	}
-}
-
-void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	reg &= ~PRE_EMPHASIS_SET_MASK;
-	reg |= level << PRE_EMPHASIS_SET_SHIFT;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-}
-
-void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
-					u32 training_lane)
-{
-	u32 reg;
-
-	reg = training_lane;
-	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-}
-
-u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
-	return reg;
-}
-
-u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
-	return reg;
-}
-
-void exynos_dp_reset_macro(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
-	reg |= MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-
-	/* 10 us is the minimum reset time. */
-	usleep_range(10, 20);
-
-	reg &= ~MACRO_RST;
-	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
-}
-
-void exynos_dp_init_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
-	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = CHA_CRI(4) | CHA_CTRL;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = 0x0;
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
-}
-
-void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	/* Configure the input color depth, color space, dynamic range */
-	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
-		(dp->video_info->color_depth << IN_BPC_SHIFT) |
-		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
-
-	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-	reg &= ~IN_YC_COEFFI_MASK;
-	if (dp->video_info->ycbcr_coeff)
-		reg |= IN_YC_COEFFI_ITU709;
-	else
-		reg |= IN_YC_COEFFI_ITU601;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
-}
-
-int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
-
-	if (!(reg & DET_STA)) {
-		dev_dbg(dp->dev, "Input stream clock not detected.\n");
-		return -EINVAL;
-	}
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
-	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
-
-	if (reg & CHA_STA) {
-		dev_dbg(dp->dev, "Input stream clk is changing\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
-{
-	u32 reg;
-
-	if (type == REGISTER_M) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg |= FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg = m_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
-		reg = (m_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
-		reg = (m_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
-
-		reg = n_value & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
-		reg = (n_value >> 8) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
-		reg = (n_value >> 16) & 0xff;
-		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
-	} else  {
-		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-		reg &= ~FIX_M_VID;
-		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
-
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
-		writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
-		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
-	}
-}
-
-void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
-{
-	u32 reg;
-
-	if (type == VIDEO_TIMING_FROM_CAPTURE) {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg &= ~FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-		reg |= FORMAT_SEL;
-		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	}
-}
-
-void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
-{
-	u32 reg;
-
-	if (enable) {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	} else {
-		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-		reg &= ~VIDEO_MODE_MASK;
-		reg |= VIDEO_MODE_SLAVE_MODE;
-		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-	}
-}
-
-void exynos_dp_start_video(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-	reg |= VIDEO_EN;
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
-}
-
-int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
-	if (!(reg & STRM_VALID)) {
-		dev_dbg(dp->dev, "Input video stream is not detected.\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
-	reg |= MASTER_VID_FUNC_EN_N;
-	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~INTERACE_SCAN_CFG;
-	reg |= (dp->video_info->interlaced << 2);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~VSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->v_sync_polarity << 1);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-	reg &= ~HSYNC_POLARITY_CFG;
-	reg |= (dp->video_info->h_sync_polarity << 0);
-	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
-
-	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
-	writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
-}
-
-void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg &= ~SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
-
-void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
-{
-	u32 reg;
-
-	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-	reg |= SCRAMBLING_DISABLE;
-	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
-}
diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.h b/drivers/gpu/drm/exynos/exynos_dp_reg.h
deleted file mode 100644
index 2e9bd0e..0000000
--- a/drivers/gpu/drm/exynos/exynos_dp_reg.h
+++ /dev/null
@@ -1,366 +0,0 @@
-/*
- * Register definition file for Samsung DP driver
- *
- * Copyright (C) 2012 Samsung Electronics Co., Ltd.
- * Author: Jingoo Han <jg1.han@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _EXYNOS_DP_REG_H
-#define _EXYNOS_DP_REG_H
-
-#define EXYNOS_DP_TX_SW_RESET			0x14
-#define EXYNOS_DP_FUNC_EN_1			0x18
-#define EXYNOS_DP_FUNC_EN_2			0x1C
-#define EXYNOS_DP_VIDEO_CTL_1			0x20
-#define EXYNOS_DP_VIDEO_CTL_2			0x24
-#define EXYNOS_DP_VIDEO_CTL_3			0x28
-
-#define EXYNOS_DP_VIDEO_CTL_8			0x3C
-#define EXYNOS_DP_VIDEO_CTL_10			0x44
-
-#define EXYNOS_DP_LANE_MAP			0x35C
-
-#define EXYNOS_DP_ANALOG_CTL_1			0x370
-#define EXYNOS_DP_ANALOG_CTL_2			0x374
-#define EXYNOS_DP_ANALOG_CTL_3			0x378
-#define EXYNOS_DP_PLL_FILTER_CTL_1		0x37C
-#define EXYNOS_DP_TX_AMP_TUNING_CTL		0x380
-
-#define EXYNOS_DP_AUX_HW_RETRY_CTL		0x390
-
-#define EXYNOS_DP_COMMON_INT_STA_1		0x3C4
-#define EXYNOS_DP_COMMON_INT_STA_2		0x3C8
-#define EXYNOS_DP_COMMON_INT_STA_3		0x3CC
-#define EXYNOS_DP_COMMON_INT_STA_4		0x3D0
-#define EXYNOS_DP_INT_STA			0x3DC
-#define EXYNOS_DP_COMMON_INT_MASK_1		0x3E0
-#define EXYNOS_DP_COMMON_INT_MASK_2		0x3E4
-#define EXYNOS_DP_COMMON_INT_MASK_3		0x3E8
-#define EXYNOS_DP_COMMON_INT_MASK_4		0x3EC
-#define EXYNOS_DP_INT_STA_MASK			0x3F8
-#define EXYNOS_DP_INT_CTL			0x3FC
-
-#define EXYNOS_DP_SYS_CTL_1			0x600
-#define EXYNOS_DP_SYS_CTL_2			0x604
-#define EXYNOS_DP_SYS_CTL_3			0x608
-#define EXYNOS_DP_SYS_CTL_4			0x60C
-
-#define EXYNOS_DP_PKT_SEND_CTL			0x640
-#define EXYNOS_DP_HDCP_CTL			0x648
-
-#define EXYNOS_DP_LINK_BW_SET			0x680
-#define EXYNOS_DP_LANE_COUNT_SET		0x684
-#define EXYNOS_DP_TRAINING_PTN_SET		0x688
-#define EXYNOS_DP_LN0_LINK_TRAINING_CTL		0x68C
-#define EXYNOS_DP_LN1_LINK_TRAINING_CTL		0x690
-#define EXYNOS_DP_LN2_LINK_TRAINING_CTL		0x694
-#define EXYNOS_DP_LN3_LINK_TRAINING_CTL		0x698
-
-#define EXYNOS_DP_DEBUG_CTL			0x6C0
-#define EXYNOS_DP_HPD_DEGLITCH_L		0x6C4
-#define EXYNOS_DP_HPD_DEGLITCH_H		0x6C8
-#define EXYNOS_DP_LINK_DEBUG_CTL		0x6E0
-
-#define EXYNOS_DP_M_VID_0			0x700
-#define EXYNOS_DP_M_VID_1			0x704
-#define EXYNOS_DP_M_VID_2			0x708
-#define EXYNOS_DP_N_VID_0			0x70C
-#define EXYNOS_DP_N_VID_1			0x710
-#define EXYNOS_DP_N_VID_2			0x714
-
-#define EXYNOS_DP_PLL_CTL			0x71C
-#define EXYNOS_DP_PHY_PD			0x720
-#define EXYNOS_DP_PHY_TEST			0x724
-
-#define EXYNOS_DP_VIDEO_FIFO_THRD		0x730
-#define EXYNOS_DP_AUDIO_MARGIN			0x73C
-
-#define EXYNOS_DP_M_VID_GEN_FILTER_TH		0x764
-#define EXYNOS_DP_M_AUD_GEN_FILTER_TH		0x778
-#define EXYNOS_DP_AUX_CH_STA			0x780
-#define EXYNOS_DP_AUX_CH_DEFER_CTL		0x788
-#define EXYNOS_DP_AUX_RX_COMM			0x78C
-#define EXYNOS_DP_BUFFER_DATA_CTL		0x790
-#define EXYNOS_DP_AUX_CH_CTL_1			0x794
-#define EXYNOS_DP_AUX_ADDR_7_0			0x798
-#define EXYNOS_DP_AUX_ADDR_15_8			0x79C
-#define EXYNOS_DP_AUX_ADDR_19_16		0x7A0
-#define EXYNOS_DP_AUX_CH_CTL_2			0x7A4
-
-#define EXYNOS_DP_BUF_DATA_0			0x7C0
-
-#define EXYNOS_DP_SOC_GENERAL_CTL		0x800
-
-/* EXYNOS_DP_TX_SW_RESET */
-#define RESET_DP_TX				(0x1 << 0)
-
-/* EXYNOS_DP_FUNC_EN_1 */
-#define MASTER_VID_FUNC_EN_N			(0x1 << 7)
-#define SLAVE_VID_FUNC_EN_N			(0x1 << 5)
-#define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
-#define AUD_FUNC_EN_N				(0x1 << 3)
-#define HDCP_FUNC_EN_N				(0x1 << 2)
-#define CRC_FUNC_EN_N				(0x1 << 1)
-#define SW_FUNC_EN_N				(0x1 << 0)
-
-/* EXYNOS_DP_FUNC_EN_2 */
-#define SSC_FUNC_EN_N				(0x1 << 7)
-#define AUX_FUNC_EN_N				(0x1 << 2)
-#define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
-#define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
-
-/* EXYNOS_DP_VIDEO_CTL_1 */
-#define VIDEO_EN				(0x1 << 7)
-#define HDCP_VIDEO_MUTE				(0x1 << 6)
-
-/* EXYNOS_DP_VIDEO_CTL_1 */
-#define IN_D_RANGE_MASK				(0x1 << 7)
-#define IN_D_RANGE_SHIFT			(7)
-#define IN_D_RANGE_CEA				(0x1 << 7)
-#define IN_D_RANGE_VESA				(0x0 << 7)
-#define IN_BPC_MASK				(0x7 << 4)
-#define IN_BPC_SHIFT				(4)
-#define IN_BPC_12_BITS				(0x3 << 4)
-#define IN_BPC_10_BITS				(0x2 << 4)
-#define IN_BPC_8_BITS				(0x1 << 4)
-#define IN_BPC_6_BITS				(0x0 << 4)
-#define IN_COLOR_F_MASK				(0x3 << 0)
-#define IN_COLOR_F_SHIFT			(0)
-#define IN_COLOR_F_YCBCR444			(0x2 << 0)
-#define IN_COLOR_F_YCBCR422			(0x1 << 0)
-#define IN_COLOR_F_RGB				(0x0 << 0)
-
-/* EXYNOS_DP_VIDEO_CTL_3 */
-#define IN_YC_COEFFI_MASK			(0x1 << 7)
-#define IN_YC_COEFFI_SHIFT			(7)
-#define IN_YC_COEFFI_ITU709			(0x1 << 7)
-#define IN_YC_COEFFI_ITU601			(0x0 << 7)
-#define VID_CHK_UPDATE_TYPE_MASK		(0x1 << 4)
-#define VID_CHK_UPDATE_TYPE_SHIFT		(4)
-#define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
-#define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
-
-/* EXYNOS_DP_VIDEO_CTL_8 */
-#define VID_HRES_TH(x)				(((x) & 0xf) << 4)
-#define VID_VRES_TH(x)				(((x) & 0xf) << 0)
-
-/* EXYNOS_DP_VIDEO_CTL_10 */
-#define FORMAT_SEL				(0x1 << 4)
-#define INTERACE_SCAN_CFG			(0x1 << 2)
-#define VSYNC_POLARITY_CFG			(0x1 << 1)
-#define HSYNC_POLARITY_CFG			(0x1 << 0)
-
-/* EXYNOS_DP_LANE_MAP */
-#define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
-#define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
-#define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
-#define LANE3_MAP_LOGIC_LANE_3			(0x3 << 6)
-#define LANE2_MAP_LOGIC_LANE_0			(0x0 << 4)
-#define LANE2_MAP_LOGIC_LANE_1			(0x1 << 4)
-#define LANE2_MAP_LOGIC_LANE_2			(0x2 << 4)
-#define LANE2_MAP_LOGIC_LANE_3			(0x3 << 4)
-#define LANE1_MAP_LOGIC_LANE_0			(0x0 << 2)
-#define LANE1_MAP_LOGIC_LANE_1			(0x1 << 2)
-#define LANE1_MAP_LOGIC_LANE_2			(0x2 << 2)
-#define LANE1_MAP_LOGIC_LANE_3			(0x3 << 2)
-#define LANE0_MAP_LOGIC_LANE_0			(0x0 << 0)
-#define LANE0_MAP_LOGIC_LANE_1			(0x1 << 0)
-#define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
-#define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
-
-/* EXYNOS_DP_ANALOG_CTL_1 */
-#define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
-
-/* EXYNOS_DP_ANALOG_CTL_2 */
-#define SEL_24M					(0x1 << 3)
-#define TX_DVDD_BIT_1_0625V			(0x4 << 0)
-
-/* EXYNOS_DP_ANALOG_CTL_3 */
-#define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
-#define VCO_BIT_600_MICRO			(0x5 << 0)
-
-/* EXYNOS_DP_PLL_FILTER_CTL_1 */
-#define PD_RING_OSC				(0x1 << 6)
-#define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
-#define TX_CUR1_2X				(0x1 << 2)
-#define TX_CUR_16_MA				(0x3 << 0)
-
-/* EXYNOS_DP_TX_AMP_TUNING_CTL */
-#define CH3_AMP_400_MV				(0x0 << 24)
-#define CH2_AMP_400_MV				(0x0 << 16)
-#define CH1_AMP_400_MV				(0x0 << 8)
-#define CH0_AMP_400_MV				(0x0 << 0)
-
-/* EXYNOS_DP_AUX_HW_RETRY_CTL */
-#define AUX_BIT_PERIOD_EXPECTED_DELAY(x)	(((x) & 0x7) << 8)
-#define AUX_HW_RETRY_INTERVAL_MASK		(0x3 << 3)
-#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS	(0x0 << 3)
-#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS	(0x1 << 3)
-#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS	(0x2 << 3)
-#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS	(0x3 << 3)
-#define AUX_HW_RETRY_COUNT_SEL(x)		(((x) & 0x7) << 0)
-
-/* EXYNOS_DP_COMMON_INT_STA_1 */
-#define VSYNC_DET				(0x1 << 7)
-#define PLL_LOCK_CHG				(0x1 << 6)
-#define SPDIF_ERR				(0x1 << 5)
-#define SPDIF_UNSTBL				(0x1 << 4)
-#define VID_FORMAT_CHG				(0x1 << 3)
-#define AUD_CLK_CHG				(0x1 << 2)
-#define VID_CLK_CHG				(0x1 << 1)
-#define SW_INT					(0x1 << 0)
-
-/* EXYNOS_DP_COMMON_INT_STA_2 */
-#define ENC_EN_CHG				(0x1 << 6)
-#define HW_BKSV_RDY				(0x1 << 3)
-#define HW_SHA_DONE				(0x1 << 2)
-#define HW_AUTH_STATE_CHG			(0x1 << 1)
-#define HW_AUTH_DONE				(0x1 << 0)
-
-/* EXYNOS_DP_COMMON_INT_STA_3 */
-#define AFIFO_UNDER				(0x1 << 7)
-#define AFIFO_OVER				(0x1 << 6)
-#define R0_CHK_FLAG				(0x1 << 5)
-
-/* EXYNOS_DP_COMMON_INT_STA_4 */
-#define PSR_ACTIVE				(0x1 << 7)
-#define PSR_INACTIVE				(0x1 << 6)
-#define SPDIF_BI_PHASE_ERR			(0x1 << 5)
-#define HOTPLUG_CHG				(0x1 << 2)
-#define HPD_LOST				(0x1 << 1)
-#define PLUG					(0x1 << 0)
-
-/* EXYNOS_DP_INT_STA */
-#define INT_HPD					(0x1 << 6)
-#define HW_TRAINING_FINISH			(0x1 << 5)
-#define RPLY_RECEIV				(0x1 << 1)
-#define AUX_ERR					(0x1 << 0)
-
-/* EXYNOS_DP_INT_CTL */
-#define SOFT_INT_CTRL				(0x1 << 2)
-#define INT_POL1				(0x1 << 1)
-#define INT_POL0				(0x1 << 0)
-
-/* EXYNOS_DP_SYS_CTL_1 */
-#define DET_STA					(0x1 << 2)
-#define FORCE_DET				(0x1 << 1)
-#define DET_CTRL				(0x1 << 0)
-
-/* EXYNOS_DP_SYS_CTL_2 */
-#define CHA_CRI(x)				(((x) & 0xf) << 4)
-#define CHA_STA					(0x1 << 2)
-#define FORCE_CHA				(0x1 << 1)
-#define CHA_CTRL				(0x1 << 0)
-
-/* EXYNOS_DP_SYS_CTL_3 */
-#define HPD_STATUS				(0x1 << 6)
-#define F_HPD					(0x1 << 5)
-#define HPD_CTRL				(0x1 << 4)
-#define HDCP_RDY				(0x1 << 3)
-#define STRM_VALID				(0x1 << 2)
-#define F_VALID					(0x1 << 1)
-#define VALID_CTRL				(0x1 << 0)
-
-/* EXYNOS_DP_SYS_CTL_4 */
-#define FIX_M_AUD				(0x1 << 4)
-#define ENHANCED				(0x1 << 3)
-#define FIX_M_VID				(0x1 << 2)
-#define M_VID_UPDATE_CTRL			(0x3 << 0)
-
-/* EXYNOS_DP_TRAINING_PTN_SET */
-#define SCRAMBLER_TYPE				(0x1 << 9)
-#define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
-#define SCRAMBLING_DISABLE			(0x1 << 5)
-#define SCRAMBLING_ENABLE			(0x0 << 5)
-#define LINK_QUAL_PATTERN_SET_MASK		(0x3 << 2)
-#define LINK_QUAL_PATTERN_SET_PRBS7		(0x3 << 2)
-#define LINK_QUAL_PATTERN_SET_D10_2		(0x1 << 2)
-#define LINK_QUAL_PATTERN_SET_DISABLE		(0x0 << 2)
-#define SW_TRAINING_PATTERN_SET_MASK		(0x3 << 0)
-#define SW_TRAINING_PATTERN_SET_PTN2		(0x2 << 0)
-#define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
-#define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
-
-/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
-#define PRE_EMPHASIS_SET_MASK			(0x3 << 3)
-#define PRE_EMPHASIS_SET_SHIFT			(3)
-
-/* EXYNOS_DP_DEBUG_CTL */
-#define PLL_LOCK				(0x1 << 4)
-#define F_PLL_LOCK				(0x1 << 3)
-#define PLL_LOCK_CTRL				(0x1 << 2)
-#define PN_INV					(0x1 << 0)
-
-/* EXYNOS_DP_PLL_CTL */
-#define DP_PLL_PD				(0x1 << 7)
-#define DP_PLL_RESET				(0x1 << 6)
-#define DP_PLL_LOOP_BIT_DEFAULT			(0x1 << 4)
-#define DP_PLL_REF_BIT_1_1250V			(0x5 << 0)
-#define DP_PLL_REF_BIT_1_2500V			(0x7 << 0)
-
-/* EXYNOS_DP_PHY_PD */
-#define DP_PHY_PD				(0x1 << 5)
-#define AUX_PD					(0x1 << 4)
-#define CH3_PD					(0x1 << 3)
-#define CH2_PD					(0x1 << 2)
-#define CH1_PD					(0x1 << 1)
-#define CH0_PD					(0x1 << 0)
-
-/* EXYNOS_DP_PHY_TEST */
-#define MACRO_RST				(0x1 << 5)
-#define CH1_TEST				(0x1 << 1)
-#define CH0_TEST				(0x1 << 0)
-
-/* EXYNOS_DP_AUX_CH_STA */
-#define AUX_BUSY				(0x1 << 4)
-#define AUX_STATUS_MASK				(0xf << 0)
-
-/* EXYNOS_DP_AUX_CH_DEFER_CTL */
-#define DEFER_CTRL_EN				(0x1 << 7)
-#define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
-
-/* EXYNOS_DP_AUX_RX_COMM */
-#define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
-#define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
-
-/* EXYNOS_DP_BUFFER_DATA_CTL */
-#define BUF_CLR					(0x1 << 7)
-#define BUF_DATA_COUNT(x)			(((x) & 0x1f) << 0)
-
-/* EXYNOS_DP_AUX_CH_CTL_1 */
-#define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
-#define AUX_TX_COMM_MASK			(0xf << 0)
-#define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
-#define AUX_TX_COMM_I2C_TRANSACTION		(0x0 << 3)
-#define AUX_TX_COMM_MOT				(0x1 << 2)
-#define AUX_TX_COMM_WRITE			(0x0 << 0)
-#define AUX_TX_COMM_READ			(0x1 << 0)
-
-/* EXYNOS_DP_AUX_ADDR_7_0 */
-#define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
-
-/* EXYNOS_DP_AUX_ADDR_15_8 */
-#define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
-
-/* EXYNOS_DP_AUX_ADDR_19_16 */
-#define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
-
-/* EXYNOS_DP_AUX_CH_CTL_2 */
-#define ADDR_ONLY				(0x1 << 1)
-#define AUX_EN					(0x1 << 0)
-
-/* EXYNOS_DP_SOC_GENERAL_CTL */
-#define AUDIO_MODE_SPDIF_MODE			(0x1 << 8)
-#define AUDIO_MODE_MASTER_MODE			(0x0 << 8)
-#define MASTER_VIDEO_INTERLACE_EN		(0x1 << 4)
-#define VIDEO_MASTER_CLK_SEL			(0x1 << 2)
-#define VIDEO_MASTER_MODE_EN			(0x1 << 1)
-#define VIDEO_MODE_MASK				(0x1 << 0)
-#define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
-#define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
-
-#endif /* _EXYNOS_DP_REG_H */
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
new file mode 100644
index 0000000..d1188db
--- /dev/null
+++ b/include/drm/bridge/analogix_dp.h
@@ -0,0 +1,40 @@
+/*
+ * Analogix DP (Display Port) Core interface driver.
+ *
+ * Copyright (C) 2015 Rockchip Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#ifndef _ANALOGIX_DP_H_
+#define _ANALOGIX_DP_H_
+
+#include <drm/drm_crtc.h>
+
+enum analogix_dp_devtype {
+	EXYNOS_DP,
+};
+
+struct analogix_dp_plat_data {
+	enum analogix_dp_devtype dev_type;
+	struct drm_panel *panel;
+	struct drm_encoder *encoder;
+	struct drm_connector *connector;
+
+	int (*power_on)(struct analogix_dp_plat_data *);
+	int (*power_off)(struct analogix_dp_plat_data *);
+	int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *,
+		      struct drm_connector *);
+	int (*get_modes)(struct analogix_dp_plat_data *);
+};
+
+int analogix_dp_resume(struct device *dev);
+int analogix_dp_suspend(struct device *dev);
+
+int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
+		     struct analogix_dp_plat_data *plat_data);
+void analogix_dp_unbind(struct device *dev, struct device *master, void *data);
+
+#endif /* _ANALOGIX_DP_H_ */
-- 
2.6.4

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [PATCH v14 04/17] drm: bridge: analogix/dp: fix some obvious code style
  2016-02-15 11:09 ` [PATCH v14 04/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
@ 2016-03-17 21:48   ` Heiko Stübner
  2016-03-17 21:50   ` [PATCH v14.1 " Heiko Stübner
  1 sibling, 0 replies; 57+ messages in thread
From: Heiko Stübner @ 2016-03-17 21:48 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Mark Yao, Russell King, djkurtz, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, javier, Andy Yan, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v14.1:
- Rebase against drm-next from 2016-03-17

Changes in v14: None
Changes in v13: None
Changes in v12:
- Add the ack from Jingoo

Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
  from exynos_dp code, and rephrase reasonable commit message, and
  remove some controversial style (Krzysztof)
    -           analogix_dp_write_byte_to_dpcd(
    -                           dp, DP_TEST_RESPONSE,
    +           analogix_dp_write_byte_to_dpcd(dp,
    +                           DP_TEST_RESPONSE,
                                DP_TEST_EDID_CHECKSUM_WRITE);

Changes in v4: None
Changes in v3: None
Changes in v2:
- Improved commit message more readable, and avoid using some
  uncommon style like bellow: (Joe Preches)
    -  retval = exynos_dp_read_bytes_from_i2c(...
                                  ...);
    +  retval =
    +  exynos_dp_read_bytes_from_i2c(......);

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++++++++++-----------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  72 ++++++------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 124 ++++++++++----------
 drivers/gpu/drm/exynos/exynos_dp.c                 |   4 +-
 4 files changed, 165 insertions(+), 164 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 392c296..6901a6f 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -64,7 +64,7 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 
 	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
 			return -ETIMEDOUT;
 		}
@@ -101,8 +101,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
 	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-				EDID_EXTENSION_FLAG,
-				&extend_block);
+						EDID_EXTENSION_FLAG,
+						&extend_block);
 	if (retval)
 		return retval;
 
@@ -110,7 +110,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
+						I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -141,7 +142,7 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		}
 
 		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					&test_vector);
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
@@ -155,10 +156,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 		/* Read EDID data */
 		retval = analogix_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_HEADER_PATTERN,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_HEADER_PATTERN]);
+				I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
+				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -169,16 +168,13 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 			return -EIO;
 		}
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TEST_REQUEST,
-			&test_vector);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
+				DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
+				DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE);
 		}
 	}
 
@@ -193,8 +189,7 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
-				12, buf);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
 	if (retval)
 		return retval;
 
@@ -208,8 +203,9 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
-						bool enable)
+static void
+analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
+				       bool enable)
 {
 	u8 data;
 
@@ -217,11 +213,11 @@ static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp
 
 	if (enable)
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DP_LANE_COUNT_ENHANCED_FRAME_EN |
-			DPCD_LANE_COUNT_SET(data));
+					       DP_LANE_COUNT_ENHANCED_FRAME_EN |
+					       DPCD_LANE_COUNT_SET(data));
 	else
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DPCD_LANE_COUNT_SET(data));
+					       DPCD_LANE_COUNT_SET(data));
 }
 
 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
@@ -248,13 +244,13 @@ static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
 	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	analogix_dp_write_byte_to_dpcd(dp,
-		DP_TRAINING_PATTERN_SET,
-		DP_TRAINING_PATTERN_DISABLE);
+	analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+				       DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
-					int pre_emphasis, int lane)
+static void
+analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
+				       int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -294,8 +290,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
-				2, buf);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
 	if (retval)
 		return retval;
 
@@ -331,7 +326,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
 	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, buf);
+						 lane_count, buf);
 
 	return retval;
 }
@@ -339,7 +334,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = link_status[lane>>1];
+	u8 link_value = link_status[lane >> 1];
 
 	return (link_value >> shift) & 0xf;
 }
@@ -358,7 +353,7 @@ static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 }
 
 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				int lane_count)
+				     int lane_count)
 {
 	int lane;
 	u8 lane_status;
@@ -376,11 +371,11 @@ static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							int lane)
+static unsigned char
+analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return (link_value >> shift) & 0x3;
 }
@@ -390,13 +385,13 @@ static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
-					u8 training_lane_set, int lane)
+					       u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -416,9 +411,9 @@ static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 	}
 }
 
-static unsigned int analogix_dp_get_lane_link_training(
-				struct analogix_dp_device *dp,
-				int lane)
+static unsigned int
+analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
+				   int lane)
 {
 	u32 reg;
 
@@ -452,7 +447,7 @@ static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
-					u8 adjust_request[2])
+						 u8 adjust_request[2])
 {
 	int lane, lane_count;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -625,7 +620,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
-					u8 *bandwidth)
+					     u8 *bandwidth)
 {
 	u8 data;
 
@@ -638,7 +633,7 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
-					u8 *lane_count)
+					      u8 *lane_count)
 {
 	u8 data;
 
@@ -651,8 +646,8 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_init_training(struct analogix_dp_device *dp,
-			enum link_lane_count_type max_lane,
-			enum link_rate_type max_rate)
+				      enum link_lane_count_type max_lane,
+				      enum link_rate_type max_rate)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
@@ -665,7 +660,7 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -725,8 +720,7 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 }
 
 static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
-				u32 count,
-				u32 bwtype)
+				      u32 count, u32 bwtype)
 {
 	int i;
 	int retval;
@@ -762,7 +756,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		timeout_loop++;
 		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -793,7 +787,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		} else if (done_count) {
 			done_count = 0;
 		}
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -807,25 +801,24 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
+					bool enable)
 {
 	u8 data;
 
 	if (enable) {
 		analogix_dp_enable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
 		analogix_dp_disable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
@@ -898,7 +891,7 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	}
 
 	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					dp->video_info->link_rate);
+					 dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1130,8 +1123,8 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
 
-	dp_video_config = devm_kzalloc(dev,
-				sizeof(*dp_video_config), GFP_KERNEL);
+	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
+				       GFP_KERNEL);
 	if (!dp_video_config)
 		return ERR_PTR(-ENOMEM);
 
@@ -1145,37 +1138,37 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 		of_property_read_bool(dp_node, "interlaced");
 
 	if (of_property_read_u32(dp_node, "samsung,color-space",
-				&dp_video_config->color_space)) {
+				 &dp_video_config->color_space)) {
 		dev_err(dev, "failed to get color-space\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				&dp_video_config->dynamic_range)) {
+				 &dp_video_config->dynamic_range)) {
 		dev_err(dev, "failed to get dynamic-range\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				&dp_video_config->ycbcr_coeff)) {
+				 &dp_video_config->ycbcr_coeff)) {
 		dev_err(dev, "failed to get ycbcr-coeff\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				&dp_video_config->color_depth)) {
+				 &dp_video_config->color_depth)) {
 		dev_err(dev, "failed to get color-depth\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				&dp_video_config->link_rate)) {
+				 &dp_video_config->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				&dp_video_config->lane_count)) {
+				 &dp_video_config->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
 		return ERR_PTR(-EINVAL);
 	}
@@ -1284,7 +1277,7 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	pm_runtime_enable(dev);
 
 	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
-			irq_flags, "analogix-dp", dp);
+			       irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		goto err_disable_pm_runtime;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 0fff745..d4c4ae2 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -187,50 +187,55 @@ int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
+				   unsigned int reg_addr,
+				   unsigned char data);
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
+				    unsigned int reg_addr,
+				    unsigned char *data);
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[]);
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[]);
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
+				  unsigned int device_addr,
+				  unsigned int reg_addr);
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data);
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[]);
 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable);
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern);
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+				      enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
@@ -241,11 +246,12 @@ void analogix_dp_init_video(struct analogix_dp_device *dp);
 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value,
+				 u32 n_value);
 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
-void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
+				     bool enable);
 void analogix_dp_start_video(struct analogix_dp_device *dp);
 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 442cc66..a388c0a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -54,10 +54,10 @@ void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
 
 	if (enable)
 		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+		      LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
 	else
 		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+		      LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
 
 	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
 }
@@ -202,8 +202,8 @@ void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
 }
 
 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
+				       enum analog_power_block block,
+				       bool enable)
 {
 	u32 reg;
 
@@ -399,8 +399,8 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
+	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
@@ -483,8 +483,8 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
 }
 
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
+				   unsigned int reg_addr,
+				   unsigned char data)
 {
 	u32 reg;
 	int i;
@@ -519,17 +519,16 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	return retval;
 }
 
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
+				    unsigned int reg_addr,
+				    unsigned char *data)
 {
 	u32 reg;
 	int i;
@@ -560,9 +559,8 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data buffer */
@@ -573,9 +571,9 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -608,8 +606,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 			     cur_data_idx++) {
 				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
+				writel(reg, dp->reg_base +
+				       ANALOGIX_DP_BUF_DATA_0 +
+				       4 * cur_data_idx);
 			}
 
 			/*
@@ -625,9 +624,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		start_offset += cur_data_count;
@@ -637,9 +636,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -683,9 +682,9 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
@@ -703,8 +702,8 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
+				  unsigned int device_addr,
+				  unsigned int reg_addr)
 {
 	u32 reg;
 	int retval;
@@ -736,9 +735,9 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data)
 {
 	u32 reg;
 	int i;
@@ -750,7 +749,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 		/* Select EDID device */
-		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+		retval = analogix_dp_select_i2c_device(dp, device_addr,
+						       reg_addr);
 		if (retval != 0)
 			continue;
 
@@ -767,9 +767,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data */
@@ -780,10 +779,10 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[])
 {
 	u32 reg;
 	unsigned int i, j;
@@ -828,15 +827,14 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 				retval = analogix_dp_start_aux_transaction(dp);
 				if (retval == 0)
 					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
+
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
 			}
 			/* Check if Rx sends defer */
 			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
 			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
+			    reg == AUX_RX_COMM_I2C_DEFER) {
 				dev_err(dp->dev, "Defer: %d\n\n", reg);
 				defer = 1;
 			}
@@ -885,7 +883,8 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
 	*count = reg;
 }
 
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable)
 {
 	u32 reg;
 
@@ -901,7 +900,7 @@ void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable
 }
 
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern)
+				      enum pattern_set pattern)
 {
 	u32 reg;
 
@@ -933,7 +932,8 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
 	}
 }
 
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -943,7 +943,8 @@ void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -953,7 +954,8 @@ void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -963,7 +965,8 @@ void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -974,7 +977,7 @@ void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level
 }
 
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -983,7 +986,7 @@ void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1001,7 +1004,7 @@ void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1125,9 +1128,8 @@ int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
 }
 
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value, u32 n_value)
 {
 	u32 reg;
 
@@ -1221,7 +1223,7 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 	u32 reg;
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
 	reg |= MASTER_VID_FUNC_EN_N;
 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
index 8456794..8ae3d51 100644
--- a/drivers/gpu/drm/exynos/exynos_dp.c
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -204,7 +204,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 }
 
 static void exynos_dp_unbind(struct device *dev, struct device *master,
-				void *data)
+			     void *data)
 {
 	return analogix_dp_unbind(dev, master, data);
 }
@@ -221,7 +221,7 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	struct exynos_dp_device *dp;
 
 	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
-				GFP_KERNEL);
+			  GFP_KERNEL);
 	if (!dp)
 		return -ENOMEM;
 
-- 
2.6.4

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14.1 04/17] drm: bridge: analogix/dp: fix some obvious code style
  2016-02-15 11:09 ` [PATCH v14 04/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
  2016-03-17 21:48   ` Heiko Stübner
@ 2016-03-17 21:50   ` Heiko Stübner
  1 sibling, 0 replies; 57+ messages in thread
From: Heiko Stübner @ 2016-03-17 21:50 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Mark Yao, Russell King, djkurtz, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, javier, Andy Yan, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v14.1:
- Rebase against drm-next from 2016-03-17

Changes in v14: None
Changes in v13: None
Changes in v12:
- Add the ack from Jingoo

Changes in v11: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
  from exynos_dp code, and rephrase reasonable commit message, and
  remove some controversial style (Krzysztof)
    -           analogix_dp_write_byte_to_dpcd(
    -                           dp, DP_TEST_RESPONSE,
    +           analogix_dp_write_byte_to_dpcd(dp,
    +                           DP_TEST_RESPONSE,
                                DP_TEST_EDID_CHECKSUM_WRITE);

Changes in v4: None
Changes in v3: None
Changes in v2:
- Improved commit message more readable, and avoid using some
  uncommon style like bellow: (Joe Preches)
    -  retval = exynos_dp_read_bytes_from_i2c(...
                                  ...);
    +  retval =
    +  exynos_dp_read_bytes_from_i2c(......);

 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++++++++++-----------
 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  72 ++++++------
 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 124 ++++++++++----------
 drivers/gpu/drm/exynos/exynos_dp.c                 |   4 +-
 4 files changed, 165 insertions(+), 164 deletions(-)

diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 392c296..6901a6f 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -64,7 +64,7 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
 
 	while (analogix_dp_get_plug_in_status(dp) != 0) {
 		timeout_loop++;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "failed to get hpd plug status\n");
 			return -ETIMEDOUT;
 		}
@@ -101,8 +101,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
 	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
-				EDID_EXTENSION_FLAG,
-				&extend_block);
+						EDID_EXTENSION_FLAG,
+						&extend_block);
 	if (retval)
 		return retval;
 
@@ -110,7 +110,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
 
 		/* Read EDID data */
-		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+		retval = analogix_dp_read_bytes_from_i2c(dp,
+						I2C_EDID_DEVICE_ADDR,
 						EDID_HEADER_PATTERN,
 						EDID_BLOCK_LENGTH,
 						&edid[EDID_HEADER_PATTERN]);
@@ -141,7 +142,7 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 		}
 
 		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
-					&test_vector);
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
 				DP_TEST_EDID_CHECKSUM,
@@ -155,10 +156,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 
 		/* Read EDID data */
 		retval = analogix_dp_read_bytes_from_i2c(dp,
-				I2C_EDID_DEVICE_ADDR,
-				EDID_HEADER_PATTERN,
-				EDID_BLOCK_LENGTH,
-				&edid[EDID_HEADER_PATTERN]);
+				I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
+				EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
 		if (retval != 0) {
 			dev_err(dp->dev, "EDID Read failed!\n");
 			return -EIO;
@@ -169,16 +168,13 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
 			return -EIO;
 		}
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TEST_REQUEST,
-			&test_vector);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+						&test_vector);
 		if (test_vector & DP_TEST_LINK_EDID_READ) {
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_EDID_CHECKSUM,
-				edid[EDID_CHECKSUM]);
+				DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
 			analogix_dp_write_byte_to_dpcd(dp,
-				DP_TEST_RESPONSE,
-				DP_TEST_EDID_CHECKSUM_WRITE);
+				DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE);
 		}
 	}
 
@@ -193,8 +189,7 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	int retval;
 
 	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
-	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
-				12, buf);
+	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
 	if (retval)
 		return retval;
 
@@ -208,8 +203,9 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
-						bool enable)
+static void
+analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
+				       bool enable)
 {
 	u8 data;
 
@@ -217,11 +213,11 @@ static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp
 
 	if (enable)
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DP_LANE_COUNT_ENHANCED_FRAME_EN |
-			DPCD_LANE_COUNT_SET(data));
+					       DP_LANE_COUNT_ENHANCED_FRAME_EN |
+					       DPCD_LANE_COUNT_SET(data));
 	else
 		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
-			DPCD_LANE_COUNT_SET(data));
+					       DPCD_LANE_COUNT_SET(data));
 }
 
 static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
@@ -248,13 +244,13 @@ static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
 {
 	analogix_dp_set_training_pattern(dp, DP_NONE);
 
-	analogix_dp_write_byte_to_dpcd(dp,
-		DP_TRAINING_PATTERN_SET,
-		DP_TRAINING_PATTERN_DISABLE);
+	analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+				       DP_TRAINING_PATTERN_DISABLE);
 }
 
-static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
-					int pre_emphasis, int lane)
+static void
+analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
+				       int pre_emphasis, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -294,8 +290,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 	/* Setup RX configuration */
 	buf[0] = dp->link_train.link_rate;
 	buf[1] = dp->link_train.lane_count;
-	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
-				2, buf);
+	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
 	if (retval)
 		return retval;
 
@@ -331,7 +326,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
 
 	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
-			lane_count, buf);
+						 lane_count, buf);
 
 	return retval;
 }
@@ -339,7 +334,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
 static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = link_status[lane>>1];
+	u8 link_value = link_status[lane >> 1];
 
 	return (link_value >> shift) & 0xf;
 }
@@ -358,7 +353,7 @@ static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
 }
 
 static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
-				int lane_count)
+				     int lane_count)
 {
 	int lane;
 	u8 lane_status;
@@ -376,11 +371,11 @@ static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
 	return 0;
 }
 
-static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
-							int lane)
+static unsigned char
+analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return (link_value >> shift) & 0x3;
 }
@@ -390,13 +385,13 @@ static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
 					int lane)
 {
 	int shift = (lane & 1) * 4;
-	u8 link_value = adjust_request[lane>>1];
+	u8 link_value = adjust_request[lane >> 1];
 
 	return ((link_value >> shift) & 0xc) >> 2;
 }
 
 static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
-					u8 training_lane_set, int lane)
+					       u8 training_lane_set, int lane)
 {
 	switch (lane) {
 	case 0:
@@ -416,9 +411,9 @@ static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
 	}
 }
 
-static unsigned int analogix_dp_get_lane_link_training(
-				struct analogix_dp_device *dp,
-				int lane)
+static unsigned int
+analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
+				   int lane)
 {
 	u32 reg;
 
@@ -452,7 +447,7 @@ static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
-					u8 adjust_request[2])
+						 u8 adjust_request[2])
 {
 	int lane, lane_count;
 	u8 voltage_swing, pre_emphasis, training_lane;
@@ -625,7 +620,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
 }
 
 static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
-					u8 *bandwidth)
+					     u8 *bandwidth)
 {
 	u8 data;
 
@@ -638,7 +633,7 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
-					u8 *lane_count)
+					      u8 *lane_count)
 {
 	u8 data;
 
@@ -651,8 +646,8 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
 }
 
 static void analogix_dp_init_training(struct analogix_dp_device *dp,
-			enum link_lane_count_type max_lane,
-			enum link_rate_type max_rate)
+				      enum link_lane_count_type max_lane,
+				      enum link_rate_type max_rate)
 {
 	/*
 	 * MACRO_RST must be applied after the PLL_LOCK to avoid
@@ -665,7 +660,7 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
 	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
 
 	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
-	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+	    (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
 		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
 			dp->link_train.link_rate);
 		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -725,8 +720,7 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
 }
 
 static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
-				u32 count,
-				u32 bwtype)
+				      u32 count, u32 bwtype)
 {
 	int i;
 	int retval;
@@ -762,7 +756,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		timeout_loop++;
 		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
 			break;
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -793,7 +787,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 		} else if (done_count) {
 			done_count = 0;
 		}
-		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+		if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
 			dev_err(dp->dev, "Timeout of video streamclk ok\n");
 			return -ETIMEDOUT;
 		}
@@ -807,25 +801,24 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
 	return retval;
 }
 
-static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
+					bool enable)
 {
 	u8 data;
 
 	if (enable) {
 		analogix_dp_enable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
 	} else {
 		analogix_dp_disable_scrambling(dp);
 
-		analogix_dp_read_byte_from_dpcd(dp,
-			DP_TRAINING_PATTERN_SET,
-			&data);
+		analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+						&data);
 		analogix_dp_write_byte_to_dpcd(dp,
 			DP_TRAINING_PATTERN_SET,
 			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
@@ -898,7 +891,7 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
 	}
 
 	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
-					dp->video_info->link_rate);
+					 dp->video_info->link_rate);
 	if (ret) {
 		dev_err(dp->dev, "unable to do link train\n");
 		return;
@@ -1130,8 +1123,8 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 	struct device_node *dp_node = dev->of_node;
 	struct video_info *dp_video_config;
 
-	dp_video_config = devm_kzalloc(dev,
-				sizeof(*dp_video_config), GFP_KERNEL);
+	dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
+				       GFP_KERNEL);
 	if (!dp_video_config)
 		return ERR_PTR(-ENOMEM);
 
@@ -1145,37 +1138,37 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
 		of_property_read_bool(dp_node, "interlaced");
 
 	if (of_property_read_u32(dp_node, "samsung,color-space",
-				&dp_video_config->color_space)) {
+				 &dp_video_config->color_space)) {
 		dev_err(dev, "failed to get color-space\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
-				&dp_video_config->dynamic_range)) {
+				 &dp_video_config->dynamic_range)) {
 		dev_err(dev, "failed to get dynamic-range\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
-				&dp_video_config->ycbcr_coeff)) {
+				 &dp_video_config->ycbcr_coeff)) {
 		dev_err(dev, "failed to get ycbcr-coeff\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,color-depth",
-				&dp_video_config->color_depth)) {
+				 &dp_video_config->color_depth)) {
 		dev_err(dev, "failed to get color-depth\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,link-rate",
-				&dp_video_config->link_rate)) {
+				 &dp_video_config->link_rate)) {
 		dev_err(dev, "failed to get link-rate\n");
 		return ERR_PTR(-EINVAL);
 	}
 
 	if (of_property_read_u32(dp_node, "samsung,lane-count",
-				&dp_video_config->lane_count)) {
+				 &dp_video_config->lane_count)) {
 		dev_err(dev, "failed to get lane-count\n");
 		return ERR_PTR(-EINVAL);
 	}
@@ -1284,7 +1277,7 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
 	pm_runtime_enable(dev);
 
 	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
-			irq_flags, "analogix-dp", dp);
+			       irq_flags, "analogix-dp", dp);
 	if (ret) {
 		dev_err(&pdev->dev, "failed to request irq\n");
 		goto err_disable_pm_runtime;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 0fff745..d4c4ae2 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -187,50 +187,55 @@ int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data);
+				   unsigned int reg_addr,
+				   unsigned char data);
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data);
+				    unsigned int reg_addr,
+				    unsigned char *data);
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[]);
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[]);
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[]);
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr);
+				  unsigned int device_addr,
+				  unsigned int reg_addr);
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data);
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data);
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[]);
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[]);
 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable);
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern);
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+				      enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level);
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-				u32 training_lane);
+					 u32 training_lane);
 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
@@ -241,11 +246,12 @@ void analogix_dp_init_video(struct analogix_dp_device *dp);
 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-			enum clock_recovery_m_value_type type,
-			u32 m_value,
-			u32 n_value);
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value,
+				 u32 n_value);
 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
-void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
+				     bool enable);
 void analogix_dp_start_video(struct analogix_dp_device *dp);
 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 442cc66..a388c0a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -54,10 +54,10 @@ void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
 
 	if (enable)
 		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
-			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+		      LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
 	else
 		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
-			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+		      LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
 
 	writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
 }
@@ -202,8 +202,8 @@ void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
 }
 
 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
-				enum analog_power_block block,
-				bool enable)
+				       enum analog_power_block block,
+				       bool enable)
 {
 	u32 reg;
 
@@ -399,8 +399,8 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
 	analogix_dp_reset_aux(dp);
 
 	/* Disable AUX transaction H/W retry */
-	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
-		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
+	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
 	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
 
 	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
@@ -483,8 +483,8 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
 }
 
 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char data)
+				   unsigned int reg_addr,
+				   unsigned char data)
 {
 	u32 reg;
 	int i;
@@ -519,17 +519,16 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	return retval;
 }
 
 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned char *data)
+				    unsigned int reg_addr,
+				    unsigned char *data)
 {
 	u32 reg;
 	int i;
@@ -560,9 +559,8 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data buffer */
@@ -573,9 +571,9 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -608,8 +606,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
 			     cur_data_idx++) {
 				reg = data[start_offset + cur_data_idx];
-				writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
-							  + 4 * cur_data_idx);
+				writel(reg, dp->reg_base +
+				       ANALOGIX_DP_BUF_DATA_0 +
+				       4 * cur_data_idx);
 			}
 
 			/*
@@ -625,9 +624,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		start_offset += cur_data_count;
@@ -637,9 +636,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char data[])
+				     unsigned int reg_addr,
+				     unsigned int count,
+				     unsigned char data[])
 {
 	u32 reg;
 	unsigned int start_offset;
@@ -683,9 +682,9 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 			retval = analogix_dp_start_aux_transaction(dp);
 			if (retval == 0)
 				break;
-			else
-				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-					__func__);
+
+			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+				__func__);
 		}
 
 		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
@@ -703,8 +702,8 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr)
+				  unsigned int device_addr,
+				  unsigned int reg_addr)
 {
 	u32 reg;
 	int retval;
@@ -736,9 +735,9 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int *data)
+				   unsigned int device_addr,
+				   unsigned int reg_addr,
+				   unsigned int *data)
 {
 	u32 reg;
 	int i;
@@ -750,7 +749,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
 
 		/* Select EDID device */
-		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+		retval = analogix_dp_select_i2c_device(dp, device_addr,
+						       reg_addr);
 		if (retval != 0)
 			continue;
 
@@ -767,9 +767,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 		retval = analogix_dp_start_aux_transaction(dp);
 		if (retval == 0)
 			break;
-		else
-			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
-				__func__);
+
+		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
 	}
 
 	/* Read data */
@@ -780,10 +779,10 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
 }
 
 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
-				unsigned int device_addr,
-				unsigned int reg_addr,
-				unsigned int count,
-				unsigned char edid[])
+				    unsigned int device_addr,
+				    unsigned int reg_addr,
+				    unsigned int count,
+				    unsigned char edid[])
 {
 	u32 reg;
 	unsigned int i, j;
@@ -828,15 +827,14 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
 				retval = analogix_dp_start_aux_transaction(dp);
 				if (retval == 0)
 					break;
-				else
-					dev_dbg(dp->dev,
-						"%s: Aux Transaction fail!\n",
-						__func__);
+
+				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+					__func__);
 			}
 			/* Check if Rx sends defer */
 			reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
 			if (reg == AUX_RX_COMM_AUX_DEFER ||
-				reg == AUX_RX_COMM_I2C_DEFER) {
+			    reg == AUX_RX_COMM_I2C_DEFER) {
 				dev_err(dp->dev, "Defer: %d\n\n", reg);
 				defer = 1;
 			}
@@ -885,7 +883,8 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
 	*count = reg;
 }
 
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+				      bool enable)
 {
 	u32 reg;
 
@@ -901,7 +900,7 @@ void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable
 }
 
 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
-				enum pattern_set pattern)
+				      enum pattern_set pattern)
 {
 	u32 reg;
 
@@ -933,7 +932,8 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
 	}
 }
 
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -943,7 +943,8 @@ void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -953,7 +954,8 @@ void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -963,7 +965,8 @@ void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level
 	writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
 }
 
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+					u32 level)
 {
 	u32 reg;
 
@@ -974,7 +977,7 @@ void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level
 }
 
 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -983,7 +986,7 @@ void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1001,7 +1004,7 @@ void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
 }
 
 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
-					u32 training_lane)
+					 u32 training_lane)
 {
 	u32 reg;
 
@@ -1125,9 +1128,8 @@ int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
 }
 
 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
-		enum clock_recovery_m_value_type type,
-		u32 m_value,
-		u32 n_value)
+				 enum clock_recovery_m_value_type type,
+				 u32 m_value, u32 n_value)
 {
 	u32 reg;
 
@@ -1221,7 +1223,7 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
 	u32 reg;
 
 	reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
-	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+	reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
 	reg |= MASTER_VID_FUNC_EN_N;
 	writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
 
diff --git a/drivers/gpu/drm/exynos/exynos_dp.c b/drivers/gpu/drm/exynos/exynos_dp.c
index 8456794..8ae3d51 100644
--- a/drivers/gpu/drm/exynos/exynos_dp.c
+++ b/drivers/gpu/drm/exynos/exynos_dp.c
@@ -204,7 +204,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
 }
 
 static void exynos_dp_unbind(struct device *dev, struct device *master,
-				void *data)
+			     void *data)
 {
 	return analogix_dp_unbind(dev, master, data);
 }
@@ -221,7 +221,7 @@ static int exynos_dp_probe(struct platform_device *pdev)
 	struct exynos_dp_device *dp;
 
 	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
-				GFP_KERNEL);
+			  GFP_KERNEL);
 	if (!dp)
 		return -ENOMEM;
 
-- 
2.6.4

^ permalink raw reply	[flat|nested] 57+ messages in thread

* [PATCH v14.1 09/17] drm: rockchip: dp: add rockchip platform dp driver
  2016-02-15 11:10 ` [PATCH v14 09/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
@ 2016-03-17 21:51   ` Heiko Stübner
  2016-03-18  6:45     ` Caesar Wang
  2016-03-23  1:08   ` [PATCH v14 " Mark yao
  1 sibling, 1 reply; 57+ messages in thread
From: Heiko Stübner @ 2016-03-17 21:51 UTC (permalink / raw)
  To: Yakir Yang
  Cc: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Jingoo Han, Thierry Reding, Krzysztof Kozlowski,
	Rob Herring, Mark Yao, Russell King, djkurtz, Sean Paul,
	Kukjin Kim, Kumar Gala, emil.l.velikov, Ian Campbell,
	Gustavo Padovan, Kishon Vijay Abraham I, Pawel Moll, ajaynumb,
	robherring2, javier, Andy Yan, dri-devel, devicetree,
	linux-kernel, linux-samsung-soc, linux-rockchip,
	linux-arm-kernel

Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
Changes in v14.1:
- replace rockchip_drm_encoder_get_mux_id with the new
  drm_of_encoder_active_endpoint_id

Changes in v14: None
Changes in v13:
- Use .enable instead of preprare/commit in encoder_helper_funcs (Heiko)
- Fix the missing parameters with drm_encoder_init() helper function. (Heiko)

Changes in v12: None
Changes in v11: None
Changes in v10:
- Correct the ROCKCHIP_ANALOGIX_DP indentation in Kconfig to tabs here (Heiko)

Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
  numbers in the example DT node, and remove the regulator iomux setting
  in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
  support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)

Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.

Changes in v3:
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
  and leave "sclk_edp" to analogix dp core driver which name to "dp",
  and leave "pclk_edp" to rockchip dp platform driver which name to
  "pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
  node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.

Changes in v2:
- Get panel node with remote-endpoint method, and create devicetree binding
  for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
  leave those clock to rockchip dp phy driver.

 drivers/gpu/drm/rockchip/Kconfig                |   9 +
 drivers/gpu/drm/rockchip/Makefile               |   1 +
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 384 ++++++++++++++++++++++++
 include/drm/bridge/analogix_dp.h                |   1 +
 4 files changed, 395 insertions(+)
 create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 76b3362..d30bdc3 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -16,6 +16,15 @@ config DRM_ROCKCHIP
 	  2D or 3D acceleration; acceleration is performed by other
 	  IP found on the SoC.
 
+config ROCKCHIP_ANALOGIX_DP
+	tristate "Rockchip specific extensions for Analogix DP driver"
+	depends on DRM_ROCKCHIP
+	select DRM_ANALOGIX_DP
+	help
+	  This selects support for Rockchip SoC specific extensions
+	  for the Analogix Core DP driver. If you want to enable DP
+	  on RK3288 based SoC, you should selet this option.
+
 config ROCKCHIP_DW_HDMI
         tristate "Rockchip specific extensions for Synopsys DW HDMI"
         depends on DRM_ROCKCHIP
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index df8fbef..05d0713 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,6 +6,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
 		rockchip_drm_gem.o rockchip_drm_vop.o
 rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
 
+obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
 obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
 obj-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
new file mode 100644
index 0000000..a1d94d8
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -0,0 +1,384 @@
+/*
+ * Rockchip SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ *         Yakir Yang <ykk@rock-chips.com>
+ *         Jeff Chen <jeff.chen@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)
+
+/* dp grf register offset */
+#define GRF_SOC_CON6                            0x025c
+#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
+#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
+#define GRF_EDP_SEL_VOP_BIG                     0
+
+struct rockchip_dp_device {
+	struct drm_device        *drm_dev;
+	struct device            *dev;
+	struct drm_encoder       encoder;
+	struct drm_display_mode  mode;
+
+	struct clk               *pclk;
+	struct regmap            *grf;
+	struct reset_control     *rst;
+
+	struct analogix_dp_plat_data plat_data;
+};
+
+static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+{
+	reset_control_assert(dp->rst);
+	usleep_range(10, 20);
+	reset_control_deassert(dp->rst);
+
+	return 0;
+}
+
+static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+	int ret;
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
+{
+	struct rockchip_dp_device *dp = to_dp(plat_data);
+
+	clk_disable_unprepare(dp->pclk);
+
+	return 0;
+}
+
+static bool
+rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
+				   const struct drm_display_mode *mode,
+				   struct drm_display_mode *adjusted_mode)
+{
+	/* do nothing */
+	return true;
+}
+
+static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
+					     struct drm_display_mode *mode,
+					     struct drm_display_mode *adjusted)
+{
+	/* do nothing */
+}
+
+static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
+{
+	struct rockchip_dp_device *dp = to_dp(encoder);
+	int ret;
+	u32 val;
+
+	/*
+	 * FIXME(Yakir): driver should configure the CRTC output video
+	 * mode with the display information which indicated the monitor
+	 * support colorimetry.
+	 *
+	 * But don't know why the CRTC driver seems could only output the
+	 * RGBaaa rightly. For example, if connect the "innolux,n116bge"
+	 * eDP screen, EDID would indicated that screen only accepted the
+	 * 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
+	 * screen would show a blue picture (RGB888 show a green picture).
+	 * But if I configure CTRC to RGBaaa, and eDP driver still keep
+	 * RGB666 input video mode, then screen would works prefect.
+	 */
+	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+					    DRM_MODE_CONNECTOR_eDP,
+					    ROCKCHIP_OUT_MODE_AAAA);
+	if (ret < 0) {
+		dev_err(dp->dev, "Could not set crtc mode config (%d)\n", ret);
+		return;
+	}
+
+	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
+	if (ret < 0)
+		return;
+
+	if (ret)
+		val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
+	else
+		val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
+
+	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
+
+	ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
+	if (ret != 0) {
+		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+		return;
+	}
+}
+
+static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
+{
+	/* do nothing */
+}
+
+static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
+	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
+	.mode_set = rockchip_dp_drm_encoder_mode_set,
+	.enable = rockchip_dp_drm_encoder_enable,
+	.disable = rockchip_dp_drm_encoder_nop,
+};
+
+static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+	drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
+	.destroy = rockchip_dp_drm_encoder_destroy,
+};
+
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+	struct device *dev = dp->dev;
+	struct device_node *np = dev->of_node;
+	int ret;
+
+	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+	if (IS_ERR(dp->grf)) {
+		dev_err(dev, "failed to get rockchip,grf property\n");
+		return PTR_ERR(dp->grf);
+	}
+
+	dp->pclk = devm_clk_get(dev, "pclk");
+	if (IS_ERR(dp->pclk)) {
+		dev_err(dev, "failed to get pclk property\n");
+		return PTR_ERR(dp->pclk);
+	}
+
+	dp->rst = devm_reset_control_get(dev, "dp");
+	if (IS_ERR(dp->rst)) {
+		dev_err(dev, "failed to get dp reset control\n");
+		return PTR_ERR(dp->rst);
+	}
+
+	ret = clk_prepare_enable(dp->pclk);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+		return ret;
+	}
+
+	ret = rockchip_dp_pre_init(dp);
+	if (ret < 0) {
+		dev_err(dp->dev, "failed to pre init %d\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
+{
+	struct drm_encoder *encoder = &dp->encoder;
+	struct drm_device *drm_dev = dp->drm_dev;
+	struct device *dev = dp->dev;
+	int ret;
+
+	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+							     dev->of_node);
+	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
+			       DRM_MODE_ENCODER_TMDS, NULL);
+	if (ret) {
+		DRM_ERROR("failed to initialize encoder with drm\n");
+		return ret;
+	}
+
+	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
+
+	return 0;
+}
+
+static int rockchip_dp_bind(struct device *dev, struct device *master,
+			    void *data)
+{
+	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+	struct drm_device *drm_dev = data;
+	int ret;
+
+	/*
+	 * Just like the probe function said, we don't need the
+	 * device drvrate anymore, we should leave the charge to
+	 * analogix dp driver, set the device drvdata to NULL.
+	 */
+	dev_set_drvdata(dev, NULL);
+
+	ret = rockchip_dp_init(dp);
+	if (ret < 0)
+		return ret;
+
+	dp->drm_dev = drm_dev;
+
+	ret = rockchip_dp_drm_create_encoder(dp);
+	if (ret) {
+		DRM_ERROR("failed to create drm encoder\n");
+		return ret;
+	}
+
+	dp->plat_data.encoder = &dp->encoder;
+
+	dp->plat_data.dev_type = RK3288_DP;
+	dp->plat_data.power_on = rockchip_dp_poweron;
+	dp->plat_data.power_off = rockchip_dp_powerdown;
+
+	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
+}
+
+static void rockchip_dp_unbind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops rockchip_dp_component_ops = {
+	.bind = rockchip_dp_bind,
+	.unbind = rockchip_dp_unbind,
+};
+
+static int rockchip_dp_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *panel_node, *port, *endpoint;
+	struct rockchip_dp_device *dp;
+	struct drm_panel *panel;
+
+	port = of_graph_get_port_by_id(dev->of_node, 1);
+	if (!port) {
+		dev_err(dev, "can't find output port\n");
+		return -EINVAL;
+	}
+
+	endpoint = of_get_child_by_name(port, "endpoint");
+	of_node_put(port);
+	if (!endpoint) {
+		dev_err(dev, "no output endpoint found\n");
+		return -EINVAL;
+	}
+
+	panel_node = of_graph_get_remote_port_parent(endpoint);
+	of_node_put(endpoint);
+	if (!panel_node) {
+		dev_err(dev, "no output node found\n");
+		return -EINVAL;
+	}
+
+	panel = of_drm_find_panel(panel_node);
+	if (!panel) {
+		DRM_ERROR("failed to find panel\n");
+		of_node_put(panel_node);
+		return -EPROBE_DEFER;
+	}
+
+	of_node_put(panel_node);
+
+	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+	if (!dp)
+		return -ENOMEM;
+
+	dp->dev = dev;
+
+	dp->plat_data.panel = panel;
+
+	/*
+	 * We just use the drvdata until driver run into component
+	 * add function, and then we would set drvdata to null, so
+	 * that analogix dp driver could take charge of the drvdata.
+	 */
+	platform_set_drvdata(pdev, dp);
+
+	return component_add(dev, &rockchip_dp_component_ops);
+}
+
+static int rockchip_dp_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &rockchip_dp_component_ops);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_dp_suspend(struct device *dev)
+{
+	return analogix_dp_suspend(dev);
+}
+
+static int rockchip_dp_resume(struct device *dev)
+{
+	return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops rockchip_dp_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
+};
+
+static const struct of_device_id rockchip_dp_dt_ids[] = {
+	{.compatible = "rockchip,rk3288-dp",},
+	{}
+};
+MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
+
+static struct platform_driver rockchip_dp_driver = {
+	.probe = rockchip_dp_probe,
+	.remove = rockchip_dp_remove,
+	.driver = {
+		   .name = "rockchip-dp",
+		   .owner = THIS_MODULE,
+		   .pm = &rockchip_dp_pm_ops,
+		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
+	},
+};
+
+module_platform_driver(rockchip_dp_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index d1188db..25afb31 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -15,6 +15,7 @@
 
 enum analogix_dp_devtype {
 	EXYNOS_DP,
+	RK3288_DP,
 };
 
 struct analogix_dp_plat_data {
-- 
2.6.4

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [PATCH v14 0/17] Add Analogix Core Display Port Driver
  2016-02-15 11:08 [PATCH v14 0/17] Add Analogix Core Display Port Driver Yakir Yang
                   ` (16 preceding siblings ...)
  2016-02-15 11:11 ` [PATCH v14 17/17] drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time Yakir Yang
@ 2016-03-18  6:41 ` Caesar Wang
  2016-03-18 22:53   ` Doug Anderson
  2016-03-24 13:01 ` [PATCH v14 0/17] Add Analogix Core Display Port Driver Heiko Stübner
  2016-03-31 10:15 ` Daniel Vetter
  19 siblings, 1 reply; 57+ messages in thread
From: Caesar Wang @ 2016-03-18  6:41 UTC (permalink / raw)
  To: Yakir Yang, Inki Dae, Andrzej Hajda, Joonyoung Shim,
	Seung-Woo Kim, Kyungmin Park, Jingoo Han, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, Heiko Stuebner, Mark Yao
  Cc: devicetree, linux-samsung-soc, Russell King, Pawel Moll,
	Ian Campbell, linux-rockchip, emil.l.velikov, linux-kernel,
	djkurtz, Kishon Vijay Abraham I, javier, Kukjin Kim, Sean Paul,
	dri-devel, Kumar Gala, ajaynumb, robherring2, Andy Yan,
	Gustavo Padovan, linux-arm-kernel

Hi all,

I pick this series up and test on C101PA chromebook, after Heiko update 
the 3 patches.

[v14.1,09/17] drm: rockchip: dp: add rockchip platform dp driver
[v14.1,04/17] drm: bridge: analogix/dp: fix some obvious code style
[v14.1,01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge 
directory

C101PA chromebook:
http://www.amazon.co.uk/10-1-Inch-Chromebook-Rockchip-Integrated-Graphics/dp/B0107N7WT6/ref=lp_758129031_1_4?s=computers&ie=UTF8&qid=1458282912&sr=1-4

So, verified for the rockchip eDp contrller on my github.
https://github.com/Caesar-github/rockchip/tree/veyron/next-stable-chromeos


在 2016年02月15日 19:08, Yakir Yang 写道:
> Hi all,
>
>    The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM
>
> But there are still three light registers setting different between
> exynos and rk3288.
> 1. RK3288 have five special pll registers which not indicate in exynos
>     dp controller.
> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>     between rk3288 and exynos.
> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>     register).
>
> Due to Mark Yao have introduced the ATOMIC support to Rockchip drm, so it's
> okay to use the ATOMIC helpers functions in connector_funcs. No need to splict
> the connector init to platform driver anymore, and this is the biggest change
> since version 11.
>
> This v14 didn't have lots of new changes which seems not the correct time to
> upgrade the version number, but I have changed ordering of patches (adding 2
> more, and removing 2 out). Especially to prevent confusing people, so I updated
> the whole series.
>
> Thanks,
> - Yakir
>
>
> Changes in v14:
> - Rebase the new changes in imx-dp driver
> - Split up this patch into 3 parts, make this easy to review (Heiko)
> - Remove the Rockchip DP PHY to an separate thread (Heiko)
>      https://patchwork.kernel.org/patch/8312701/
>
> Changes in v13:
> - Use .enable instead of preprare/commit in encoder_helper_funcs (Heiko)
> - Fix the missing parameters with drm_encoder_init() helper function. (Heiko)
>
> Changes in v12:
> - Move the connector init to analogix_dp driver, and using ATOMIC helper (Heiko)
> - Add the ack from Jingoo
> - Remove the enum link_rate_type struct, using the marcos in drm_dp_helper.h (Jingoo)
>
> Changes in v11:
> - Uses tabs to fix the indentation issues in analogix_dp_core.h (Heiko)
> - Rename the "analogix,need-force-hpd" to common 'force-hpd' (Rob)
> - Add the ack from Rob Herring
> - Revert parts of Gustavo Padovan's changes in commit:
> 	drm/exynos: do not start enabling DP at bind() phase
>    Add dp phy poweron function in bind time.
> - Move the panel prepare from get_modes time to bind time, and move
>    the panel unprepare from bridge->disable to unbind time. (Heiko)
>
> Changes in v10:
> - Add the ack from Rob Herring
> - Correct the ROCKCHIP_ANALOGIX_DP indentation in Kconfig to tabs here (Heiko)
> - Add the ack from Rob Herring
> - Remove the surplus "plat_data" check. (Heiko)
> -       switch (dp->plat_data && dp->plat_data->dev_type) {
> +       switch (dp->plat_data->dev_type) {
>
> Changes in v9:
> - Document more details for 'ports' property.
>
> Changes in v8:
> - Correct the right document path of display-timing.txt (Heiko)
> - Correct the misspell of 'from' to 'frm'. (Heiko)
> - Modify the commit subject name. (Heiko)
>
> Changes in v7:
> - Back to use the of_property_read_bool() interfacs to provoid backward
>    compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
>    to avoid -EOVERFLOW error (Krzysztof)
>
> Changes in v6:
> - Fix the Kconfig recursive dependency (Javier)
> - Fix Peach Pit hpd property name error:
> -       hpd-gpio = <&gpx2 6 0>;
> +       hpd-gpios = <&gpx2 6 0>;
>
> Changes in v5:
> - Correct the check condition of gpio_is_valid when driver try to get
>    the "hpd-gpios" DT propery. (Heiko)
> - Move the platform attach callback in the front of core driver bridge
>    attch function. Cause once platform failed at attach, core driver should
>    still failed, so no need to init connector before platform attached (Krzysztof)
> - Keep code style no changes with the previous exynos_dp_code.c in this
>    patch, and update commit message about the new export symbol (Krzysztof)
> - Gather the device type patch (v4 11/16) into this one. (Krzysztof)
> - leave out the connector registration to analogix platform driver. (Thierry)
> - Resequence this patch after analogix_dp driver have been split
>    from exynos_dp code, and rephrase reasonable commit message, and
>    remove some controversial style (Krzysztof)
>      -		analogix_dp_write_byte_to_dpcd(
>      - 				dp, DP_TEST_RESPONSE,
>      +		analogix_dp_write_byte_to_dpcd(dp,
>      +				DP_TEST_RESPONSE,
> 				DP_TEST_EDID_CHECKSUM_WRITE);
> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
>    to get the backword timing values. Krzysztof suggest me that driver could use
>    the "of_property_read_bool" to get backword timing values, but that interfacs
>    would modify the original drm_display_mode timing directly (whether those
>    properties exists or not).
> - Correct the misspell in commit message. (Krzysztof)
> - Remove the empty line at the end of document, and correct the endpoint
>    numbers in the example DT node, and remove the regulator iomux setting
>    in driver code while using the pinctl in devicetree instead. (Heiko)
> - Add device type declared, cause the previous "platform device type
>    support (v4 11/16)" already merge into (v5 02/14).
> - Implement connector registration code. (Thierry)
> - Split binding doc's from driver changes. (Rob)
> - Add eDP hotplug pinctrl property. (Heiko)
>
> Changes in v4:
> - Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
> - Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
> - Create a separate folder for analogix code in bridge/ (Archit)
> - Update commit message more readable. (Jingoo)
> - Adjust the order from 05 to 04
> - Provide backword compatibility with samsung. (Krzysztof)
> - Split all DTS changes, and provide backward compatibility. Mark old
>    properties as deprecated but still support them. (Krzysztof)
> - Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
> - Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
>      "analogix,color-space" & "analogix,color-depth"   &
>      "analogix,link-rate"   & "analogix,lane-count"    &
>      "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
>      "vsync-active-high"    & "hsync-active-high"      & "interlaces"
> - Separate all DTS changes to a separate patch. (Krzysztof)
> - Remove some deprecated DT properties in rockchip dp document.
> - Seprate the link-rate and lane-count limit out with the device_type
>    flag. (Thierry)
> - Take Jingoo suggest, add commit messages.
> - Call drm_panel_prepare() in .get_modes function, ensure panel should
>    power on before driver try to read edid message.
>
> Changes in v3:
> - Move exynos's video_timing code to analogix_dp-exynos platform driver,
>    add get_modes method to struct analogix_dp_plat_data. (Thierry)
> - Rename some "samsung*" dts propery to "analogix*". (Heiko)
> - The link_rate and lane_count shouldn't config to the DT property value
>    directly, but we can take those as hardware limite. For example, RK3288
>    only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
>    like "link-rate = 0x0a" "lane-count = 4". (Thierry)
> - Dynamic parse video timing info from struct drm_display_mode and
>    struct drm_display_info. (Thierry)
> - Add devicetree binding documents. (Heiko)
> - Remove sync pol & colorimetry properies from the new analogix dp driver
>    devicetree binding. (Thierry)
> - Update the exist exynos dtsi file with the latest DP DT properies.
> - Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
>    and leave "sclk_edp" to analogix dp core driver which name to "dp",
>    and leave "pclk_edp" to rockchip dp platform driver which name to
>    "pclk". (Thierry & Heiko)
> - Add devicetree binding document. (Heiko)
> - Remove "rockchip,panel" DT property, take use of remote point to get panel
>    node. (Heiko)
> - Add the new function point dp_platdata->get_modes() init.
> - Add "analogix,need-force-hpd" to indicate whether driver need foce
>    hpd when hpd detect failed.
> - move dp hpd detect to connector detect function.
> - Add edid modes parse support
>
> Changes in v2:
> - Remove new copyright (Jingoo)
> - Fix compiled failed due to analogix_dp_device misspell
> - Improved commit message more readable, and avoid using some
>    uncommon style like bellow: (Joe Preches)
>      -  retval = exynos_dp_read_bytes_from_i2c(...
>    				  ...);
>      +  retval =
>      +  exynos_dp_read_bytes_from_i2c(......);
> - Get panel node with remote-endpoint method, and create devicetree binding
>    for driver. (Heiko)
> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>    leave those clock to rockchip dp phy driver.
> - Fix compile failed dut to phy_pd_addr variable misspell error
>
> Heiko Stuebner (2):
>    drm/exynos: dp: rename implementation specific driver part
>    drm: bridge: analogix/dp: rename register constants
>
> Yakir Yang (15):
>    drm: bridge: analogix/dp: split exynos dp driver to bridge directory
>    drm: bridge: analogix/dp: fix some obvious code style
>    drm: bridge: analogix/dp: remove duplicate configuration of link rate
>      and link count
>    drm: bridge: analogix/dp: dynamic parse sync_pol & interlace &
>      dynamic_range
>    dt-bindings: add document for analogix display port driver
>    ARM: dts: exynos/dp: remove some properties that deprecated by
>      analogix_dp driver
>    drm: rockchip: dp: add rockchip platform dp driver
>    dt-bindings: add document for rockchip variant of analogix_dp
>    drm: bridge: analogix/dp: add some rk3288 special registers setting
>    drm: bridge: analogix/dp: add max link rate and lane count limit for
>      RK3288
>    drm: bridge: analogix/dp: try force hpd after plug in lookup failed
>    drm: bridge: analogix/dp: move hpd detect to connector detect function
>    drm: bridge: analogix/dp: add edid modes parse in get_modes method
>    drm: bridge: analogix/dp: add panel prepare/unprepare in
>      suspend/resume time
>    drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable
>      time
>
>   .../bindings/display/bridge/analogix_dp.txt        |   52 +
>   .../bindings/display/exynos/exynos_dp.txt          |   93 +-
>   .../display/rockchip/analogix_dp-rockchip.txt      |   92 ++
>   arch/arm/boot/dts/exynos5250-arndale.dts           |    2 -
>   arch/arm/boot/dts/exynos5250-smdk5250.dts          |    2 -
>   arch/arm/boot/dts/exynos5250-snow-common.dtsi      |    4 +-
>   arch/arm/boot/dts/exynos5250-spring.dts            |    4 +-
>   arch/arm/boot/dts/exynos5420-peach-pit.dts         |    4 +-
>   arch/arm/boot/dts/exynos5420-smdk5420.dts          |    2 -
>   arch/arm/boot/dts/exynos5800-peach-pi.dts          |    2 -
>   drivers/gpu/drm/bridge/Kconfig                     |    2 +
>   drivers/gpu/drm/bridge/Makefile                    |    1 +
>   drivers/gpu/drm/bridge/analogix/Kconfig            |    3 +
>   drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1430 ++++++++++++++++++
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  281 ++++
>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1320 +++++++++++++++++
>   .../analogix/analogix_dp_reg.h}                    |  270 ++--
>   drivers/gpu/drm/exynos/Kconfig                     |    3 +-
>   drivers/gpu/drm/exynos/Makefile                    |    2 +-
>   drivers/gpu/drm/exynos/exynos_dp.c                 |  324 +++++
>   drivers/gpu/drm/exynos/exynos_dp_core.c            | 1510 --------------------
>   drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 ----
>   drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 ----------------
>   drivers/gpu/drm/rockchip/Kconfig                   |    9 +
>   drivers/gpu/drm/rockchip/Makefile                  |    1 +
>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c    |  384 +++++
>   include/drm/bridge/analogix_dp.h                   |   41 +
>   28 files changed, 4115 insertions(+), 3269 deletions(-)
>   create mode 100644 Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
>   create mode 100644 Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
>   create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
>   create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>   rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (62%)
>   create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.c
>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
>   create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>   create mode 100644 include/drm/bridge/analogix_dp.h
>


-- 
Thanks,
Caesar

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [PATCH v14.1 09/17] drm: rockchip: dp: add rockchip platform dp driver
  2016-03-17 21:51   ` [PATCH v14.1 " Heiko Stübner
@ 2016-03-18  6:45     ` Caesar Wang
  0 siblings, 0 replies; 57+ messages in thread
From: Caesar Wang @ 2016-03-18  6:45 UTC (permalink / raw)
  To: Heiko Stübner, Yakir Yang
  Cc: Krzysztof Kozlowski, Seung-Woo Kim, djkurtz, Andrzej Hajda,
	Gustavo Padovan, linux-samsung-soc, Russell King, Joonyoung Shim,
	linux-rockchip, Kishon Vijay Abraham I, javier, Kukjin Kim,
	robherring2, Thierry Reding, devicetree, Pawel Moll,
	Ian Campbell, Inki Dae, Rob Herring, Sean Paul, dri-devel,
	linux-arm-kernel, Mark Yao, Jingoo Han, emil.l.velikov,
	linux-kernel, Kyungmin Park, Kumar Gala, ajaynumb, Andy Yan



在 2016年03月18日 05:51, Heiko Stübner 写道:
> Rockchip have three clocks for dp controller, we leave pclk_edp
> to analogix_dp driver control, and keep the sclk_edp_24m and
> sclk_edp in platform driver.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>

Tested-by: Caesar Wang <wxt@rock-chips.com>

As the cover-letter said, verified on 
https://github.com/Caesar-github/rockchip/tree/veyron/next-stable-chromeos
with linux-next for 20160317.

> ---
> Changes in v14.1:
> - replace rockchip_drm_encoder_get_mux_id with the new
>    drm_of_encoder_active_endpoint_id
>
> Changes in v14: None
> Changes in v13:
> - Use .enable instead of preprare/commit in encoder_helper_funcs (Heiko)
> - Fix the missing parameters with drm_encoder_init() helper function. (Heiko)
>
> Changes in v12: None
> Changes in v11: None
> Changes in v10:
> - Correct the ROCKCHIP_ANALOGIX_DP indentation in Kconfig to tabs here (Heiko)
>
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
> Changes in v6: None
> Changes in v5:
> - Remove the empty line at the end of document, and correct the endpoint
>    numbers in the example DT node, and remove the regulator iomux setting
>    in driver code while using the pinctl in devicetree instead. (Heiko)
> - Add device type declared, cause the previous "platform device type
>    support (v4 11/16)" already merge into (v5 02/14).
> - Implement connector registration code. (Thierry)
>
> Changes in v4:
> - Remove some deprecated DT properties in rockchip dp document.
>
> Changes in v3:
> - Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
>    and leave "sclk_edp" to analogix dp core driver which name to "dp",
>    and leave "pclk_edp" to rockchip dp platform driver which name to
>    "pclk". (Thierry & Heiko)
> - Add devicetree binding document. (Heiko)
> - Remove "rockchip,panel" DT property, take use of remote point to get panel
>    node. (Heiko)
> - Add the new function point dp_platdata->get_modes() init.
>
> Changes in v2:
> - Get panel node with remote-endpoint method, and create devicetree binding
>    for driver. (Heiko)
> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
>    leave those clock to rockchip dp phy driver.
>
>   drivers/gpu/drm/rockchip/Kconfig                |   9 +
>   drivers/gpu/drm/rockchip/Makefile               |   1 +
>   drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 384 ++++++++++++++++++++++++
>   include/drm/bridge/analogix_dp.h                |   1 +
>   4 files changed, 395 insertions(+)
>   create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
>
> diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
> index 76b3362..d30bdc3 100644
> --- a/drivers/gpu/drm/rockchip/Kconfig
> +++ b/drivers/gpu/drm/rockchip/Kconfig
> @@ -16,6 +16,15 @@ config DRM_ROCKCHIP
>   	  2D or 3D acceleration; acceleration is performed by other
>   	  IP found on the SoC.
>   
> +config ROCKCHIP_ANALOGIX_DP
> +	tristate "Rockchip specific extensions for Analogix DP driver"
> +	depends on DRM_ROCKCHIP
> +	select DRM_ANALOGIX_DP
> +	help
> +	  This selects support for Rockchip SoC specific extensions
> +	  for the Analogix Core DP driver. If you want to enable DP
> +	  on RK3288 based SoC, you should selet this option.
> +
>   config ROCKCHIP_DW_HDMI
>           tristate "Rockchip specific extensions for Synopsys DW HDMI"
>           depends on DRM_ROCKCHIP
> diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
> index df8fbef..05d0713 100644
> --- a/drivers/gpu/drm/rockchip/Makefile
> +++ b/drivers/gpu/drm/rockchip/Makefile
> @@ -6,6 +6,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
>   		rockchip_drm_gem.o rockchip_drm_vop.o
>   rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
>   
> +obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
>   obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
>   obj-$(CONFIG_ROCKCHIP_DW_MIPI_DSI) += dw-mipi-dsi.o
>   obj-$(CONFIG_ROCKCHIP_INNO_HDMI) += inno_hdmi.o
> diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> new file mode 100644
> index 0000000..a1d94d8
> --- /dev/null
> +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> @@ -0,0 +1,384 @@
> +/*
> + * Rockchip SoC DP (Display Port) interface driver.
> + *
> + * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
> + * Author: Andy Yan <andy.yan@rock-chips.com>
> + *         Yakir Yang <ykk@rock-chips.com>
> + *         Jeff Chen <jeff.chen@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/component.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/of_graph.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/clk.h>
> +
> +#include <drm/drmP.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_dp_helper.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_panel.h>
> +
> +#include <video/of_videomode.h>
> +#include <video/videomode.h>
> +
> +#include <drm/bridge/analogix_dp.h>
> +
> +#include "rockchip_drm_drv.h"
> +#include "rockchip_drm_vop.h"
> +
> +#define to_dp(nm)	container_of(nm, struct rockchip_dp_device, nm)
> +
> +/* dp grf register offset */
> +#define GRF_SOC_CON6                            0x025c
> +#define GRF_EDP_LCD_SEL_MASK                    BIT(5)
> +#define GRF_EDP_SEL_VOP_LIT                     BIT(5)
> +#define GRF_EDP_SEL_VOP_BIG                     0
> +
> +struct rockchip_dp_device {
> +	struct drm_device        *drm_dev;
> +	struct device            *dev;
> +	struct drm_encoder       encoder;
> +	struct drm_display_mode  mode;
> +
> +	struct clk               *pclk;
> +	struct regmap            *grf;
> +	struct reset_control     *rst;
> +
> +	struct analogix_dp_plat_data plat_data;
> +};
> +
> +static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
> +{
> +	reset_control_assert(dp->rst);
> +	usleep_range(10, 20);
> +	reset_control_deassert(dp->rst);
> +
> +	return 0;
> +}
> +
> +static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
> +{
> +	struct rockchip_dp_device *dp = to_dp(plat_data);
> +	int ret;
> +
> +	ret = clk_prepare_enable(dp->pclk);
> +	if (ret < 0) {
> +		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = rockchip_dp_pre_init(dp);
> +	if (ret < 0) {
> +		dev_err(dp->dev, "failed to dp pre init %d\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
> +{
> +	struct rockchip_dp_device *dp = to_dp(plat_data);
> +
> +	clk_disable_unprepare(dp->pclk);
> +
> +	return 0;
> +}
> +
> +static bool
> +rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
> +				   const struct drm_display_mode *mode,
> +				   struct drm_display_mode *adjusted_mode)
> +{
> +	/* do nothing */
> +	return true;
> +}
> +
> +static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
> +					     struct drm_display_mode *mode,
> +					     struct drm_display_mode *adjusted)
> +{
> +	/* do nothing */
> +}
> +
> +static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
> +{
> +	struct rockchip_dp_device *dp = to_dp(encoder);
> +	int ret;
> +	u32 val;
> +
> +	/*
> +	 * FIXME(Yakir): driver should configure the CRTC output video
> +	 * mode with the display information which indicated the monitor
> +	 * support colorimetry.
> +	 *
> +	 * But don't know why the CRTC driver seems could only output the
> +	 * RGBaaa rightly. For example, if connect the "innolux,n116bge"
> +	 * eDP screen, EDID would indicated that screen only accepted the
> +	 * 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
> +	 * screen would show a blue picture (RGB888 show a green picture).
> +	 * But if I configure CTRC to RGBaaa, and eDP driver still keep
> +	 * RGB666 input video mode, then screen would works prefect.
> +	 */
> +	ret = rockchip_drm_crtc_mode_config(encoder->crtc,
> +					    DRM_MODE_CONNECTOR_eDP,
> +					    ROCKCHIP_OUT_MODE_AAAA);
> +	if (ret < 0) {
> +		dev_err(dp->dev, "Could not set crtc mode config (%d)\n", ret);
> +		return;
> +	}
> +
> +	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
> +	if (ret < 0)
> +		return;
> +
> +	if (ret)
> +		val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
> +	else
> +		val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
> +
> +	dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
> +
> +	ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
> +	if (ret != 0) {
> +		dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
> +		return;
> +	}
> +}
> +
> +static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
> +{
> +	/* do nothing */
> +}
> +
> +static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
> +	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
> +	.mode_set = rockchip_dp_drm_encoder_mode_set,
> +	.enable = rockchip_dp_drm_encoder_enable,
> +	.disable = rockchip_dp_drm_encoder_nop,
> +};
> +
> +static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
> +{
> +	drm_encoder_cleanup(encoder);
> +}
> +
> +static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
> +	.destroy = rockchip_dp_drm_encoder_destroy,
> +};
> +
> +static int rockchip_dp_init(struct rockchip_dp_device *dp)
> +{
> +	struct device *dev = dp->dev;
> +	struct device_node *np = dev->of_node;
> +	int ret;
> +
> +	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
> +	if (IS_ERR(dp->grf)) {
> +		dev_err(dev, "failed to get rockchip,grf property\n");
> +		return PTR_ERR(dp->grf);
> +	}
> +
> +	dp->pclk = devm_clk_get(dev, "pclk");
> +	if (IS_ERR(dp->pclk)) {
> +		dev_err(dev, "failed to get pclk property\n");
> +		return PTR_ERR(dp->pclk);
> +	}
> +
> +	dp->rst = devm_reset_control_get(dev, "dp");
> +	if (IS_ERR(dp->rst)) {
> +		dev_err(dev, "failed to get dp reset control\n");
> +		return PTR_ERR(dp->rst);
> +	}
> +
> +	ret = clk_prepare_enable(dp->pclk);
> +	if (ret < 0) {
> +		dev_err(dp->dev, "failed to enable pclk %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = rockchip_dp_pre_init(dp);
> +	if (ret < 0) {
> +		dev_err(dp->dev, "failed to pre init %d\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
> +{
> +	struct drm_encoder *encoder = &dp->encoder;
> +	struct drm_device *drm_dev = dp->drm_dev;
> +	struct device *dev = dp->dev;
> +	int ret;
> +
> +	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
> +							     dev->of_node);
> +	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
> +
> +	ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
> +			       DRM_MODE_ENCODER_TMDS, NULL);
> +	if (ret) {
> +		DRM_ERROR("failed to initialize encoder with drm\n");
> +		return ret;
> +	}
> +
> +	drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
> +
> +	return 0;
> +}
> +
> +static int rockchip_dp_bind(struct device *dev, struct device *master,
> +			    void *data)
> +{
> +	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
> +	struct drm_device *drm_dev = data;
> +	int ret;
> +
> +	/*
> +	 * Just like the probe function said, we don't need the
> +	 * device drvrate anymore, we should leave the charge to
> +	 * analogix dp driver, set the device drvdata to NULL.
> +	 */
> +	dev_set_drvdata(dev, NULL);
> +
> +	ret = rockchip_dp_init(dp);
> +	if (ret < 0)
> +		return ret;
> +
> +	dp->drm_dev = drm_dev;
> +
> +	ret = rockchip_dp_drm_create_encoder(dp);
> +	if (ret) {
> +		DRM_ERROR("failed to create drm encoder\n");
> +		return ret;
> +	}
> +
> +	dp->plat_data.encoder = &dp->encoder;
> +
> +	dp->plat_data.dev_type = RK3288_DP;
> +	dp->plat_data.power_on = rockchip_dp_poweron;
> +	dp->plat_data.power_off = rockchip_dp_powerdown;
> +
> +	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
> +}
> +
> +static void rockchip_dp_unbind(struct device *dev, struct device *master,
> +			       void *data)
> +{
> +	return analogix_dp_unbind(dev, master, data);
> +}
> +
> +static const struct component_ops rockchip_dp_component_ops = {
> +	.bind = rockchip_dp_bind,
> +	.unbind = rockchip_dp_unbind,
> +};
> +
> +static int rockchip_dp_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *panel_node, *port, *endpoint;
> +	struct rockchip_dp_device *dp;
> +	struct drm_panel *panel;
> +
> +	port = of_graph_get_port_by_id(dev->of_node, 1);
> +	if (!port) {
> +		dev_err(dev, "can't find output port\n");
> +		return -EINVAL;
> +	}
> +
> +	endpoint = of_get_child_by_name(port, "endpoint");
> +	of_node_put(port);
> +	if (!endpoint) {
> +		dev_err(dev, "no output endpoint found\n");
> +		return -EINVAL;
> +	}
> +
> +	panel_node = of_graph_get_remote_port_parent(endpoint);
> +	of_node_put(endpoint);
> +	if (!panel_node) {
> +		dev_err(dev, "no output node found\n");
> +		return -EINVAL;
> +	}
> +
> +	panel = of_drm_find_panel(panel_node);
> +	if (!panel) {
> +		DRM_ERROR("failed to find panel\n");
> +		of_node_put(panel_node);
> +		return -EPROBE_DEFER;
> +	}
> +
> +	of_node_put(panel_node);
> +
> +	dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
> +	if (!dp)
> +		return -ENOMEM;
> +
> +	dp->dev = dev;
> +
> +	dp->plat_data.panel = panel;
> +
> +	/*
> +	 * We just use the drvdata until driver run into component
> +	 * add function, and then we would set drvdata to null, so
> +	 * that analogix dp driver could take charge of the drvdata.
> +	 */
> +	platform_set_drvdata(pdev, dp);
> +
> +	return component_add(dev, &rockchip_dp_component_ops);
> +}
> +
> +static int rockchip_dp_remove(struct platform_device *pdev)
> +{
> +	component_del(&pdev->dev, &rockchip_dp_component_ops);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int rockchip_dp_suspend(struct device *dev)
> +{
> +	return analogix_dp_suspend(dev);
> +}
> +
> +static int rockchip_dp_resume(struct device *dev)
> +{
> +	return analogix_dp_resume(dev);
> +}
> +#endif
> +
> +static const struct dev_pm_ops rockchip_dp_pm_ops = {
> +	SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
> +};
> +
> +static const struct of_device_id rockchip_dp_dt_ids[] = {
> +	{.compatible = "rockchip,rk3288-dp",},
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
> +
> +static struct platform_driver rockchip_dp_driver = {
> +	.probe = rockchip_dp_probe,
> +	.remove = rockchip_dp_remove,
> +	.driver = {
> +		   .name = "rockchip-dp",
> +		   .owner = THIS_MODULE,
> +		   .pm = &rockchip_dp_pm_ops,
> +		   .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
> +	},
> +};
> +
> +module_platform_driver(rockchip_dp_driver);
> +
> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
> +MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
> +MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
> +MODULE_LICENSE("GPL v2");
> diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
> index d1188db..25afb31 100644
> --- a/include/drm/bridge/analogix_dp.h
> +++ b/include/drm/bridge/analogix_dp.h
> @@ -15,6 +15,7 @@
>   
>   enum analogix_dp_devtype {
>   	EXYNOS_DP,
> +	RK3288_DP,
>   };
>   
>   struct analogix_dp_plat_data {


-- 
Thanks,
Caesar

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [PATCH v14 11/17] drm: bridge: analogix/dp: add some rk3288 special registers setting
  2016-02-15 11:10 ` [PATCH v14 11/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
@ 2016-03-18  6:56   ` Caesar Wang
  0 siblings, 0 replies; 57+ messages in thread
From: Caesar Wang @ 2016-03-18  6:56 UTC (permalink / raw)
  To: Yakir Yang, Kyungmin Park
  Cc: Inki Dae, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Jingoo Han, Thierry Reding, Krzysztof Kozlowski, Rob Herring,
	Heiko Stuebner, Mark Yao, devicetree, linux-samsung-soc,
	Russell King, Pawel Moll, Ian Campbell, linux-rockchip,
	emil.l.velikov, linux-kernel, djkurtz, Kishon Vijay Abraham I,
	javier, Kukjin Kim, Sean Paul, dri-devel, Kumar Gala, ajaynumb,
	robherring2, Andy Yan, Gustavo Padovan, linux-arm-kernel



在 2016年02月15日 19:10, Yakir Yang 写道:
> RK3288 need some special registers setting, we can separate
> them out by the dev_type of plat_data.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>

Tested-by: Caesar Wang <wxt@rock-chips.com>

> ---
> Changes in v14: None
> Changes in v13: None
> Changes in v12: None
> Changes in v11: None
> Changes in v10: None
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Fix compile failed dut to phy_pd_addr variable misspell error
>
>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++++++++++++++---------
>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 ++++
>   2 files changed, 60 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> index 3858df5..1e24b37 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -15,6 +15,8 @@
>   #include <linux/delay.h>
>   #include <linux/gpio.h>
>   
> +#include <drm/bridge/analogix_dp.h>
> +
>   #include "analogix_dp_core.h"
>   #include "analogix_dp_reg.h"
>   
> @@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
>   	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
>   	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
>   
> +	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
> +		writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
> +		writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
> +		writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
> +		writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
> +		writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
> +	}
> +

In general, I will say what's mean for the number.

Okay that's the rk3288 special registers setting.

>   	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
>   	writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
>   
> @@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
>   				       bool enable)
>   {
>   	u32 reg;
> +	u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
> +
> +	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
> +		phy_pd_addr = ANALOGIX_DP_PD;
>   
>   	switch (block) {
>   	case AUX_BLOCK:
>   		if (enable) {
> -			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			reg = readl(dp->reg_base + phy_pd_addr);
>   			reg |= AUX_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		} else {
> -			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			reg = readl(dp->reg_base + phy_pd_addr);
>   			reg &= ~AUX_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		}
>   		break;
>   	case CH0_BLOCK:
>   		if (enable) {
> -			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			reg = readl(dp->reg_base + phy_pd_addr);
>   			reg |= CH0_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		} else {
> -			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			reg = readl(dp->reg_base + phy_pd_addr);
>   			reg &= ~CH0_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		}
>   		break;
>   	case CH1_BLOCK:
>   		if (enable) {
> -			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			reg = readl(dp->reg_base + phy_pd_addr);
>   			reg |= CH1_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		} else {
> -			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			reg = readl(dp->reg_base + phy_pd_addr);
>   			reg &= ~CH1_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		}
>   		break;
>   	case CH2_BLOCK:
>   		if (enable) {
> -			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			reg = readl(dp->reg_base + phy_pd_addr);
>   			reg |= CH2_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		} else {
> -			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			reg = readl(dp->reg_base + phy_pd_addr);
>   			reg &= ~CH2_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		}
>   		break;
>   	case CH3_BLOCK:
>   		if (enable) {
> -			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			reg = readl(dp->reg_base + phy_pd_addr);
>   			reg |= CH3_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		} else {
> -			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			reg = readl(dp->reg_base + phy_pd_addr);
>   			reg &= ~CH3_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		}
>   		break;
>   	case ANALOG_TOTAL:
>   		if (enable) {
> -			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			reg = readl(dp->reg_base + phy_pd_addr);
>   			reg |= DP_PHY_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		} else {
> -			reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			reg = readl(dp->reg_base + phy_pd_addr);
>   			reg &= ~DP_PHY_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		}
>   		break;
>   	case POWER_ALL:
>   		if (enable) {
>   			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
>   				CH1_PD | CH0_PD;
> -			writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(reg, dp->reg_base + phy_pd_addr);
>   		} else {
> -			writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
> +			writel(0x00, dp->reg_base + phy_pd_addr);
>   		}
>   		break;
>   	default:
> @@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
>   	analogix_dp_reset_aux(dp);
>   
>   	/* Disable AUX transaction H/W retry */
> -	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
> -	      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> +	if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
> +		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
> +		      AUX_HW_RETRY_COUNT_SEL(3) |
> +		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> +	else
> +		reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
> +		      AUX_HW_RETRY_COUNT_SEL(0) |
> +		      AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
>   	writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
>   
>   	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> index 738db4c..337912b 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> @@ -22,6 +22,14 @@
>   #define ANALOGIX_DP_VIDEO_CTL_8			0x3C
>   #define ANALOGIX_DP_VIDEO_CTL_10		0x44
>   
> +#define ANALOGIX_DP_PLL_REG_1			0xfc
> +#define ANALOGIX_DP_PLL_REG_2			0x9e4
> +#define ANALOGIX_DP_PLL_REG_3			0x9e8
> +#define ANALOGIX_DP_PLL_REG_4			0x9ec
> +#define ANALOGIX_DP_PLL_REG_5			0xa00
> +
> +#define ANALOGIX_DP_PD				0x12c
> +
>   #define ANALOGIX_DP_LANE_MAP			0x35C
>   
>   #define ANALOGIX_DP_ANALOG_CTL_1		0x370
> @@ -154,6 +162,10 @@
>   #define VSYNC_POLARITY_CFG			(0x1 << 1)
>   #define HSYNC_POLARITY_CFG			(0x1 << 0)
>   
> +/* ANALOGIX_DP_PLL_REG_1 */
> +#define REF_CLK_24M				(0x1 << 1)
> +#define REF_CLK_27M				(0x0 << 1)
> +
>   /* ANALOGIX_DP_LANE_MAP */
>   #define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
>   #define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)


-- 
Thanks,
Caesar

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [PATCH v14.1 01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
  2016-03-17 21:47   ` [PATCH v14.1 " Heiko Stübner
@ 2016-03-18  7:01     ` Caesar Wang
  2016-06-07 17:06     ` Javier Martinez Canillas
  1 sibling, 0 replies; 57+ messages in thread
From: Caesar Wang @ 2016-03-18  7:01 UTC (permalink / raw)
  To: Heiko Stübner, Yakir Yang
  Cc: Krzysztof Kozlowski, Seung-Woo Kim, djkurtz, Andrzej Hajda,
	Gustavo Padovan, linux-samsung-soc, Russell King, Joonyoung Shim,
	linux-rockchip, Kishon Vijay Abraham I, javier, Kukjin Kim,
	robherring2, Thierry Reding, devicetree, Pawel Moll,
	Ian Campbell, Inki Dae, Rob Herring, Sean Paul, dri-devel,
	linux-arm-kernel, Mark Yao, Jingoo Han, emil.l.velikov,
	linux-kernel, Kyungmin Park, Kumar Gala, ajaynumb, Andy Yan,
	Doug Anderson

Hi Samsung Guys,

Can you take your time to test or review for exynos controller?:-)

Anyway, verified on rockchip controller.
So feel free add my test tag for this patch.


在 2016年03月18日 05:47, Heiko Stübner 写道:
> Split the dp core driver from exynos directory to bridge directory,
> and rename the core driver to analogix_dp_*, rename the platform
> code to exynos_dp.
>
> Beside the new analogix_dp driver would export six hooks.
> "analogix_dp_bind()" and "analogix_dp_unbind()"
> "analogix_dp_suspned()" and "analogix_dp_resume()"
> "analogix_dp_detect()" and "analogix_dp_get_modes()"
>
> The bind/unbind symbols is used for analogix platform driver to connect
> with analogix_dp core driver. And the detect/get_modes is used for analogix
> platform driver to init the connector.
>
> They reason why connector need register in helper driver is rockchip drm
> haven't implement the atomic API, but Exynos drm have implement it, so
> there would need two different connector helper functions, that's why we
> leave the connector register in helper driver.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>

Tested-by: Caesar Wang <wxt@rock-chips.com>

> ---
> Changes in v14.1:
> - Rebase against drm-next from 2016-03-17
>    (adapt to another round of exynos-dp changes)
>
> Changes in v14:
> - Rebase the new changes in imx-dp driver
> - Split up this patch into 3 parts, make this easy to review (Heiko)
>
> Changes in v13: None
> Changes in v12:
> - Move the connector init to analogix_dp driver, and using ATOMIC helper (Heiko)
>
> Changes in v11:
> - Uses tabs to fix the indentation issues in analogix_dp_core.h (Heiko)
>
> Changes in v10: None
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
> Changes in v6:
> - Fix the Kconfig recursive dependency (Javier)
>
> Changes in v5:
> - Correct the check condition of gpio_is_valid when driver try to get
>    the "hpd-gpios" DT propery. (Heiko)
> - Move the platform attach callback in the front of core driver bridge
>    attch function. Cause once platform failed at attach, core driver should
>    still failed, so no need to init connector before platform attached (Krzysztof)
> - Keep code style no changes with the previous exynos_dp_code.c in this
>    patch, and update commit message about the new export symbol (Krzysztof)
> - Gather the device type patch (v4 11/16) into this one. (Krzysztof)
> - leave out the connector registration to analogix platform driver. (Thierry)
>
> Changes in v4:
> - Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
> - Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
> - Create a separate folder for analogix code in bridge/ (Archit)
>
> Changes in v3:
> - Move exynos's video_timing code to analogix_dp-exynos platform driver,
>    add get_modes method to struct analogix_dp_plat_data. (Thierry)
> - Rename some "samsung*" dts propery to "analogix*". (Heiko)
>
> Changes in v2:
> - Remove new copyright (Jingoo)
> - Fix compiled failed due to analogix_dp_device misspell
>
>
>   drivers/gpu/drm/bridge/Kconfig                     |    2 +
>   drivers/gpu/drm/bridge/Makefile                    |    1 +
>   drivers/gpu/drm/bridge/analogix/Kconfig            |    3 +
>   drivers/gpu/drm/bridge/analogix/Makefile           |    1 +
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1351 +++++++++++++++++++
>   drivers/gpu/drm/bridge/analogix/analogix_dp_core.h |  277 ++++
>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c  | 1263 ++++++++++++++++++
>   drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h  |  366 ++++++
>   drivers/gpu/drm/exynos/Kconfig                     |    3 +-
>   drivers/gpu/drm/exynos/Makefile                    |    2 +-
>   drivers/gpu/drm/exynos/exynos_dp_core.c            | 1353 ++------------------
>   drivers/gpu/drm/exynos/exynos_dp_core.h            |  282 ----
>   drivers/gpu/drm/exynos/exynos_dp_reg.c             | 1263 ------------------
>   drivers/gpu/drm/exynos/exynos_dp_reg.h             |  366 ------
>   include/drm/bridge/analogix_dp.h                   |   40 +
>   15 files changed, 3391 insertions(+), 3182 deletions(-)
>   create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
>   create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
>   create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
>   delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.h
>   create mode 100644 include/drm/bridge/analogix_dp.h
>
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 27e2022..efd94e0 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -40,4 +40,6 @@ config DRM_PARADE_PS8622
>   	---help---
>   	  Parade eDP-LVDS bridge chip driver.
>   
> +source "drivers/gpu/drm/bridge/analogix/Kconfig"
> +
>   endmenu
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index f13c33d..ff821f4 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -4,3 +4,4 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
>   obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
>   obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
>   obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
> diff --git a/drivers/gpu/drm/bridge/analogix/Kconfig b/drivers/gpu/drm/bridge/analogix/Kconfig
> new file mode 100644
> index 0000000..80f286f
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/Kconfig
> @@ -0,0 +1,3 @@
> +config DRM_ANALOGIX_DP
> +	tristate
> +	depends on DRM
> diff --git a/drivers/gpu/drm/bridge/analogix/Makefile b/drivers/gpu/drm/bridge/analogix/Makefile
> new file mode 100644
> index 0000000..9107b86
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix_dp_core.o analogix_dp_reg.o
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> new file mode 100644
> index 0000000..392c296
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -0,0 +1,1351 @@
> +/*
> +* Analogix DP (Display Port) core interface driver.
> +*
> +* Copyright (C) 2012 Samsung Electronics Co., Ltd.
> +* Author: Jingoo Han <jg1.han@samsung.com>
> +*
> +* This program is free software; you can redistribute it and/or modify it
> +* under the terms of the GNU General Public License as published by the
> +* Free Software Foundation; either version 2 of the License, or (at your
> +* option) any later version.
> +*/
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/err.h>
> +#include <linux/clk.h>
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/of.h>
> +#include <linux/of_gpio.h>
> +#include <linux/gpio.h>
> +#include <linux/component.h>
> +#include <linux/phy/phy.h>
> +
> +#include <drm/drmP.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_panel.h>
> +
> +#include <drm/bridge/analogix_dp.h>
> +
> +#include "analogix_dp_core.h"
> +
> +#define to_dp(nm)	container_of(nm, struct analogix_dp_device, nm)
> +
> +struct bridge_init {
> +	struct i2c_client *client;
> +	struct device_node *node;
> +};
> +
> +static void analogix_dp_init_dp(struct analogix_dp_device *dp)
> +{
> +	analogix_dp_reset(dp);
> +
> +	analogix_dp_swreset(dp);
> +
> +	analogix_dp_init_analog_param(dp);
> +	analogix_dp_init_interrupt(dp);
> +
> +	/* SW defined function Normal operation */
> +	analogix_dp_enable_sw_function(dp);
> +
> +	analogix_dp_config_interrupt(dp);
> +	analogix_dp_init_analog_func(dp);
> +
> +	analogix_dp_init_hpd(dp);
> +	analogix_dp_init_aux(dp);
> +}
> +
> +static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
> +{
> +	int timeout_loop = 0;
> +
> +	while (analogix_dp_get_plug_in_status(dp) != 0) {
> +		timeout_loop++;
> +		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> +			dev_err(dp->dev, "failed to get hpd plug status\n");
> +			return -ETIMEDOUT;
> +		}
> +		usleep_range(10, 11);
> +	}
> +
> +	return 0;
> +}
> +
> +static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
> +{
> +	int i;
> +	unsigned char sum = 0;
> +
> +	for (i = 0; i < EDID_BLOCK_LENGTH; i++)
> +		sum = sum + edid_data[i];
> +
> +	return sum;
> +}
> +
> +static int analogix_dp_read_edid(struct analogix_dp_device *dp)
> +{
> +	unsigned char edid[EDID_BLOCK_LENGTH * 2];
> +	unsigned int extend_block = 0;
> +	unsigned char sum;
> +	unsigned char test_vector;
> +	int retval;
> +
> +	/*
> +	 * EDID device address is 0x50.
> +	 * However, if necessary, you must have set upper address
> +	 * into E-EDID in I2C device, 0x30.
> +	 */
> +
> +	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
> +	retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> +				EDID_EXTENSION_FLAG,
> +				&extend_block);
> +	if (retval)
> +		return retval;
> +
> +	if (extend_block > 0) {
> +		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
> +
> +		/* Read EDID data */
> +		retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> +						EDID_HEADER_PATTERN,
> +						EDID_BLOCK_LENGTH,
> +						&edid[EDID_HEADER_PATTERN]);
> +		if (retval != 0) {
> +			dev_err(dp->dev, "EDID Read failed!\n");
> +			return -EIO;
> +		}
> +		sum = analogix_dp_calc_edid_check_sum(edid);
> +		if (sum != 0) {
> +			dev_err(dp->dev, "EDID bad checksum!\n");
> +			return -EIO;
> +		}
> +
> +		/* Read additional EDID data */
> +		retval = analogix_dp_read_bytes_from_i2c(dp,
> +				I2C_EDID_DEVICE_ADDR,
> +				EDID_BLOCK_LENGTH,
> +				EDID_BLOCK_LENGTH,
> +				&edid[EDID_BLOCK_LENGTH]);
> +		if (retval != 0) {
> +			dev_err(dp->dev, "EDID Read failed!\n");
> +			return -EIO;
> +		}
> +		sum = analogix_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
> +		if (sum != 0) {
> +			dev_err(dp->dev, "EDID bad checksum!\n");
> +			return -EIO;
> +		}
> +
> +		analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
> +					&test_vector);
> +		if (test_vector & DP_TEST_LINK_EDID_READ) {
> +			analogix_dp_write_byte_to_dpcd(dp,
> +				DP_TEST_EDID_CHECKSUM,
> +				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
> +			analogix_dp_write_byte_to_dpcd(dp,
> +				DP_TEST_RESPONSE,
> +				DP_TEST_EDID_CHECKSUM_WRITE);
> +		}
> +	} else {
> +		dev_info(dp->dev, "EDID data does not include any extensions.\n");
> +
> +		/* Read EDID data */
> +		retval = analogix_dp_read_bytes_from_i2c(dp,
> +				I2C_EDID_DEVICE_ADDR,
> +				EDID_HEADER_PATTERN,
> +				EDID_BLOCK_LENGTH,
> +				&edid[EDID_HEADER_PATTERN]);
> +		if (retval != 0) {
> +			dev_err(dp->dev, "EDID Read failed!\n");
> +			return -EIO;
> +		}
> +		sum = analogix_dp_calc_edid_check_sum(edid);
> +		if (sum != 0) {
> +			dev_err(dp->dev, "EDID bad checksum!\n");
> +			return -EIO;
> +		}
> +
> +		analogix_dp_read_byte_from_dpcd(dp,
> +			DP_TEST_REQUEST,
> +			&test_vector);
> +		if (test_vector & DP_TEST_LINK_EDID_READ) {
> +			analogix_dp_write_byte_to_dpcd(dp,
> +				DP_TEST_EDID_CHECKSUM,
> +				edid[EDID_CHECKSUM]);
> +			analogix_dp_write_byte_to_dpcd(dp,
> +				DP_TEST_RESPONSE,
> +				DP_TEST_EDID_CHECKSUM_WRITE);
> +		}
> +	}
> +
> +	dev_dbg(dp->dev, "EDID Read success!\n");
> +	return 0;
> +}
> +
> +static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
> +{
> +	u8 buf[12];
> +	int i;
> +	int retval;
> +
> +	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
> +	retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
> +				12, buf);
> +	if (retval)
> +		return retval;
> +
> +	/* Read EDID */
> +	for (i = 0; i < 3; i++) {
> +		retval = analogix_dp_read_edid(dp);
> +		if (!retval)
> +			break;
> +	}
> +
> +	return retval;
> +}
> +
> +static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
> +						bool enable)
> +{
> +	u8 data;
> +
> +	analogix_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
> +
> +	if (enable)
> +		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
> +			DP_LANE_COUNT_ENHANCED_FRAME_EN |
> +			DPCD_LANE_COUNT_SET(data));
> +	else
> +		analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
> +			DPCD_LANE_COUNT_SET(data));
> +}
> +
> +static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
> +{
> +	u8 data;
> +	int retval;
> +
> +	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
> +	retval = DPCD_ENHANCED_FRAME_CAP(data);
> +
> +	return retval;
> +}
> +
> +static void analogix_dp_set_enhanced_mode(struct analogix_dp_device *dp)
> +{
> +	u8 data;
> +
> +	data = analogix_dp_is_enhanced_mode_available(dp);
> +	analogix_dp_enable_rx_to_enhanced_mode(dp, data);
> +	analogix_dp_enable_enhanced_mode(dp, data);
> +}
> +
> +static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
> +{
> +	analogix_dp_set_training_pattern(dp, DP_NONE);
> +
> +	analogix_dp_write_byte_to_dpcd(dp,
> +		DP_TRAINING_PATTERN_SET,
> +		DP_TRAINING_PATTERN_DISABLE);
> +}
> +
> +static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
> +					int pre_emphasis, int lane)
> +{
> +	switch (lane) {
> +	case 0:
> +		analogix_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
> +		break;
> +	case 1:
> +		analogix_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
> +		break;
> +
> +	case 2:
> +		analogix_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
> +		break;
> +
> +	case 3:
> +		analogix_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
> +		break;
> +	}
> +}
> +
> +static int analogix_dp_link_start(struct analogix_dp_device *dp)
> +{
> +	u8 buf[4];
> +	int lane, lane_count, pll_tries, retval;
> +
> +	lane_count = dp->link_train.lane_count;
> +
> +	dp->link_train.lt_state = CLOCK_RECOVERY;
> +	dp->link_train.eq_loop = 0;
> +
> +	for (lane = 0; lane < lane_count; lane++)
> +		dp->link_train.cr_loop[lane] = 0;
> +
> +	/* Set link rate and count as you want to establish*/
> +	analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
> +	analogix_dp_set_lane_count(dp, dp->link_train.lane_count);
> +
> +	/* Setup RX configuration */
> +	buf[0] = dp->link_train.link_rate;
> +	buf[1] = dp->link_train.lane_count;
> +	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
> +				2, buf);
> +	if (retval)
> +		return retval;
> +
> +	/* Set TX pre-emphasis to minimum */
> +	for (lane = 0; lane < lane_count; lane++)
> +		analogix_dp_set_lane_lane_pre_emphasis(dp,
> +			PRE_EMPHASIS_LEVEL_0, lane);
> +
> +	/* Wait for PLL lock */
> +	pll_tries = 0;
> +	while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
> +		if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
> +			dev_err(dp->dev, "Wait for PLL lock timed out\n");
> +			return -ETIMEDOUT;
> +		}
> +
> +		pll_tries++;
> +		usleep_range(90, 120);
> +	}
> +
> +	/* Set training pattern 1 */
> +	analogix_dp_set_training_pattern(dp, TRAINING_PTN1);
> +
> +	/* Set RX training pattern */
> +	retval = analogix_dp_write_byte_to_dpcd(dp,
> +			DP_TRAINING_PATTERN_SET,
> +			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
> +	if (retval)
> +		return retval;
> +
> +	for (lane = 0; lane < lane_count; lane++)
> +		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
> +			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
> +
> +	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
> +			lane_count, buf);
> +
> +	return retval;
> +}
> +
> +static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
> +{
> +	int shift = (lane & 1) * 4;
> +	u8 link_value = link_status[lane>>1];
> +
> +	return (link_value >> shift) & 0xf;
> +}
> +
> +static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
> +{
> +	int lane;
> +	u8 lane_status;
> +
> +	for (lane = 0; lane < lane_count; lane++) {
> +		lane_status = analogix_dp_get_lane_status(link_status, lane);
> +		if ((lane_status & DP_LANE_CR_DONE) == 0)
> +			return -EINVAL;
> +	}
> +	return 0;
> +}
> +
> +static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
> +				int lane_count)
> +{
> +	int lane;
> +	u8 lane_status;
> +
> +	if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
> +		return -EINVAL;
> +
> +	for (lane = 0; lane < lane_count; lane++) {
> +		lane_status = analogix_dp_get_lane_status(link_status, lane);
> +		lane_status &= DP_CHANNEL_EQ_BITS;
> +		if (lane_status != DP_CHANNEL_EQ_BITS)
> +			return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
> +							int lane)
> +{
> +	int shift = (lane & 1) * 4;
> +	u8 link_value = adjust_request[lane>>1];
> +
> +	return (link_value >> shift) & 0x3;
> +}
> +
> +static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
> +					u8 adjust_request[2],
> +					int lane)
> +{
> +	int shift = (lane & 1) * 4;
> +	u8 link_value = adjust_request[lane>>1];
> +
> +	return ((link_value >> shift) & 0xc) >> 2;
> +}
> +
> +static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
> +					u8 training_lane_set, int lane)
> +{
> +	switch (lane) {
> +	case 0:
> +		analogix_dp_set_lane0_link_training(dp, training_lane_set);
> +		break;
> +	case 1:
> +		analogix_dp_set_lane1_link_training(dp, training_lane_set);
> +		break;
> +
> +	case 2:
> +		analogix_dp_set_lane2_link_training(dp, training_lane_set);
> +		break;
> +
> +	case 3:
> +		analogix_dp_set_lane3_link_training(dp, training_lane_set);
> +		break;
> +	}
> +}
> +
> +static unsigned int analogix_dp_get_lane_link_training(
> +				struct analogix_dp_device *dp,
> +				int lane)
> +{
> +	u32 reg;
> +
> +	switch (lane) {
> +	case 0:
> +		reg = analogix_dp_get_lane0_link_training(dp);
> +		break;
> +	case 1:
> +		reg = analogix_dp_get_lane1_link_training(dp);
> +		break;
> +	case 2:
> +		reg = analogix_dp_get_lane2_link_training(dp);
> +		break;
> +	case 3:
> +		reg = analogix_dp_get_lane3_link_training(dp);
> +		break;
> +	default:
> +		WARN_ON(1);
> +		return 0;
> +	}
> +
> +	return reg;
> +}
> +
> +static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
> +{
> +	analogix_dp_training_pattern_dis(dp);
> +	analogix_dp_set_enhanced_mode(dp);
> +
> +	dp->link_train.lt_state = FAILED;
> +}
> +
> +static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
> +					u8 adjust_request[2])
> +{
> +	int lane, lane_count;
> +	u8 voltage_swing, pre_emphasis, training_lane;
> +
> +	lane_count = dp->link_train.lane_count;
> +	for (lane = 0; lane < lane_count; lane++) {
> +		voltage_swing = analogix_dp_get_adjust_request_voltage(
> +						adjust_request, lane);
> +		pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
> +						adjust_request, lane);
> +		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
> +				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
> +
> +		if (voltage_swing == VOLTAGE_LEVEL_3)
> +			training_lane |= DP_TRAIN_MAX_SWING_REACHED;
> +		if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
> +			training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> +
> +		dp->link_train.training_lane[lane] = training_lane;
> +	}
> +}
> +
> +static int analogix_dp_process_clock_recovery(struct analogix_dp_device *dp)
> +{
> +	int lane, lane_count, retval;
> +	u8 voltage_swing, pre_emphasis, training_lane;
> +	u8 link_status[2], adjust_request[2];
> +
> +	usleep_range(100, 101);
> +
> +	lane_count = dp->link_train.lane_count;
> +
> +	retval =  analogix_dp_read_bytes_from_dpcd(dp,
> +			DP_LANE0_1_STATUS, 2, link_status);
> +	if (retval)
> +		return retval;
> +
> +	retval =  analogix_dp_read_bytes_from_dpcd(dp,
> +			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
> +	if (retval)
> +		return retval;
> +
> +	if (analogix_dp_clock_recovery_ok(link_status, lane_count) == 0) {
> +		/* set training pattern 2 for EQ */
> +		analogix_dp_set_training_pattern(dp, TRAINING_PTN2);
> +
> +		retval = analogix_dp_write_byte_to_dpcd(dp,
> +				DP_TRAINING_PATTERN_SET,
> +				DP_LINK_SCRAMBLING_DISABLE |
> +				DP_TRAINING_PATTERN_2);
> +		if (retval)
> +			return retval;
> +
> +		dev_info(dp->dev, "Link Training Clock Recovery success\n");
> +		dp->link_train.lt_state = EQUALIZER_TRAINING;
> +	} else {
> +		for (lane = 0; lane < lane_count; lane++) {
> +			training_lane = analogix_dp_get_lane_link_training(
> +							dp, lane);
> +			voltage_swing = analogix_dp_get_adjust_request_voltage(
> +							adjust_request, lane);
> +			pre_emphasis = analogix_dp_get_adjust_request_pre_emphasis(
> +							adjust_request, lane);
> +
> +			if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
> +					voltage_swing &&
> +			    DPCD_PRE_EMPHASIS_GET(training_lane) ==
> +					pre_emphasis)
> +				dp->link_train.cr_loop[lane]++;
> +
> +			if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
> +			    voltage_swing == VOLTAGE_LEVEL_3 ||
> +			    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
> +				dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
> +					dp->link_train.cr_loop[lane],
> +					voltage_swing, pre_emphasis);
> +				analogix_dp_reduce_link_rate(dp);
> +				return -EIO;
> +			}
> +		}
> +	}
> +
> +	analogix_dp_get_adjust_training_lane(dp, adjust_request);
> +
> +	for (lane = 0; lane < lane_count; lane++)
> +		analogix_dp_set_lane_link_training(dp,
> +			dp->link_train.training_lane[lane], lane);
> +
> +	retval = analogix_dp_write_bytes_to_dpcd(dp,
> +			DP_TRAINING_LANE0_SET, lane_count,
> +			dp->link_train.training_lane);
> +	if (retval)
> +		return retval;
> +
> +	return retval;
> +}
> +
> +static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
> +{
> +	int lane, lane_count, retval;
> +	u32 reg;
> +	u8 link_align, link_status[2], adjust_request[2];
> +
> +	usleep_range(400, 401);
> +
> +	lane_count = dp->link_train.lane_count;
> +
> +	retval = analogix_dp_read_bytes_from_dpcd(dp,
> +			DP_LANE0_1_STATUS, 2, link_status);
> +	if (retval)
> +		return retval;
> +
> +	if (analogix_dp_clock_recovery_ok(link_status, lane_count)) {
> +		analogix_dp_reduce_link_rate(dp);
> +		return -EIO;
> +	}
> +
> +	retval = analogix_dp_read_bytes_from_dpcd(dp,
> +			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
> +	if (retval)
> +		return retval;
> +
> +	retval = analogix_dp_read_byte_from_dpcd(dp,
> +			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
> +	if (retval)
> +		return retval;
> +
> +	analogix_dp_get_adjust_training_lane(dp, adjust_request);
> +
> +	if (!analogix_dp_channel_eq_ok(link_status, link_align, lane_count)) {
> +		/* traing pattern Set to Normal */
> +		analogix_dp_training_pattern_dis(dp);
> +
> +		dev_info(dp->dev, "Link Training success!\n");
> +
> +		analogix_dp_get_link_bandwidth(dp, &reg);
> +		dp->link_train.link_rate = reg;
> +		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
> +			dp->link_train.link_rate);
> +
> +		analogix_dp_get_lane_count(dp, &reg);
> +		dp->link_train.lane_count = reg;
> +		dev_dbg(dp->dev, "final lane count = %.2x\n",
> +			dp->link_train.lane_count);
> +
> +		/* set enhanced mode if available */
> +		analogix_dp_set_enhanced_mode(dp);
> +		dp->link_train.lt_state = FINISHED;
> +
> +		return 0;
> +	}
> +
> +	/* not all locked */
> +	dp->link_train.eq_loop++;
> +
> +	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
> +		dev_err(dp->dev, "EQ Max loop\n");
> +		analogix_dp_reduce_link_rate(dp);
> +		return -EIO;
> +	}
> +
> +	for (lane = 0; lane < lane_count; lane++)
> +		analogix_dp_set_lane_link_training(dp,
> +			dp->link_train.training_lane[lane], lane);
> +
> +	retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
> +			lane_count, dp->link_train.training_lane);
> +
> +	return retval;
> +}
> +
> +static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
> +					u8 *bandwidth)
> +{
> +	u8 data;
> +
> +	/*
> +	 * For DP rev.1.1, Maximum link rate of Main Link lanes
> +	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
> +	 */
> +	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
> +	*bandwidth = data;
> +}
> +
> +static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
> +					u8 *lane_count)
> +{
> +	u8 data;
> +
> +	/*
> +	 * For DP rev.1.1, Maximum number of Main Link lanes
> +	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
> +	 */
> +	analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
> +	*lane_count = DPCD_MAX_LANE_COUNT(data);
> +}
> +
> +static void analogix_dp_init_training(struct analogix_dp_device *dp,
> +			enum link_lane_count_type max_lane,
> +			enum link_rate_type max_rate)
> +{
> +	/*
> +	 * MACRO_RST must be applied after the PLL_LOCK to avoid
> +	 * the DP inter pair skew issue for at least 10 us
> +	 */
> +	analogix_dp_reset_macro(dp);
> +
> +	/* Initialize by reading RX's DPCD */
> +	analogix_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
> +	analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
> +
> +	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
> +	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
> +		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
> +			dp->link_train.link_rate);
> +		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
> +	}
> +
> +	if (dp->link_train.lane_count == 0) {
> +		dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
> +			dp->link_train.lane_count);
> +		dp->link_train.lane_count = (u8)LANE_COUNT1;
> +	}
> +
> +	/* Setup TX lane count & rate */
> +	if (dp->link_train.lane_count > max_lane)
> +		dp->link_train.lane_count = max_lane;
> +	if (dp->link_train.link_rate > max_rate)
> +		dp->link_train.link_rate = max_rate;
> +
> +	/* All DP analog module power up */
> +	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
> +}
> +
> +static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
> +{
> +	int retval = 0, training_finished = 0;
> +
> +	dp->link_train.lt_state = START;
> +
> +	/* Process here */
> +	while (!retval && !training_finished) {
> +		switch (dp->link_train.lt_state) {
> +		case START:
> +			retval = analogix_dp_link_start(dp);
> +			if (retval)
> +				dev_err(dp->dev, "LT link start failed!\n");
> +			break;
> +		case CLOCK_RECOVERY:
> +			retval = analogix_dp_process_clock_recovery(dp);
> +			if (retval)
> +				dev_err(dp->dev, "LT CR failed!\n");
> +			break;
> +		case EQUALIZER_TRAINING:
> +			retval = analogix_dp_process_equalizer_training(dp);
> +			if (retval)
> +				dev_err(dp->dev, "LT EQ failed!\n");
> +			break;
> +		case FINISHED:
> +			training_finished = 1;
> +			break;
> +		case FAILED:
> +			return -EREMOTEIO;
> +		}
> +	}
> +	if (retval)
> +		dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
> +
> +	return retval;
> +}
> +
> +static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
> +				u32 count,
> +				u32 bwtype)
> +{
> +	int i;
> +	int retval;
> +
> +	for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
> +		analogix_dp_init_training(dp, count, bwtype);
> +		retval = analogix_dp_sw_link_training(dp);
> +		if (retval == 0)
> +			break;
> +
> +		usleep_range(100, 110);
> +	}
> +
> +	return retval;
> +}
> +
> +static int analogix_dp_config_video(struct analogix_dp_device *dp)
> +{
> +	int retval = 0;
> +	int timeout_loop = 0;
> +	int done_count = 0;
> +
> +	analogix_dp_config_video_slave_mode(dp);
> +
> +	analogix_dp_set_video_color_format(dp);
> +
> +	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
> +		dev_err(dp->dev, "PLL is not locked yet.\n");
> +		return -EINVAL;
> +	}
> +
> +	for (;;) {
> +		timeout_loop++;
> +		if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
> +			break;
> +		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> +			dev_err(dp->dev, "Timeout of video streamclk ok\n");
> +			return -ETIMEDOUT;
> +		}
> +
> +		usleep_range(1, 2);
> +	}
> +
> +	/* Set to use the register calculated M/N video */
> +	analogix_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
> +
> +	/* For video bist, Video timing must be generated by register */
> +	analogix_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
> +
> +	/* Disable video mute */
> +	analogix_dp_enable_video_mute(dp, 0);
> +
> +	/* Configure video slave mode */
> +	analogix_dp_enable_video_master(dp, 0);
> +
> +	timeout_loop = 0;
> +
> +	for (;;) {
> +		timeout_loop++;
> +		if (analogix_dp_is_video_stream_on(dp) == 0) {
> +			done_count++;
> +			if (done_count > 10)
> +				break;
> +		} else if (done_count) {
> +			done_count = 0;
> +		}
> +		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> +			dev_err(dp->dev, "Timeout of video streamclk ok\n");
> +			return -ETIMEDOUT;
> +		}
> +
> +		usleep_range(1000, 1001);
> +	}
> +
> +	if (retval != 0)
> +		dev_err(dp->dev, "Video stream is not detected!\n");
> +
> +	return retval;
> +}
> +
> +static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
> +{
> +	u8 data;
> +
> +	if (enable) {
> +		analogix_dp_enable_scrambling(dp);
> +
> +		analogix_dp_read_byte_from_dpcd(dp,
> +			DP_TRAINING_PATTERN_SET,
> +			&data);
> +		analogix_dp_write_byte_to_dpcd(dp,
> +			DP_TRAINING_PATTERN_SET,
> +			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
> +	} else {
> +		analogix_dp_disable_scrambling(dp);
> +
> +		analogix_dp_read_byte_from_dpcd(dp,
> +			DP_TRAINING_PATTERN_SET,
> +			&data);
> +		analogix_dp_write_byte_to_dpcd(dp,
> +			DP_TRAINING_PATTERN_SET,
> +			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
> +	}
> +}
> +
> +static irqreturn_t analogix_dp_irq_handler(int irq, void *arg)
> +{
> +	struct analogix_dp_device *dp = arg;
> +
> +	enum dp_irq_type irq_type;
> +
> +	irq_type = analogix_dp_get_irq_type(dp);
> +	switch (irq_type) {
> +	case DP_IRQ_TYPE_HP_CABLE_IN:
> +		dev_dbg(dp->dev, "Received irq - cable in\n");
> +		schedule_work(&dp->hotplug_work);
> +		analogix_dp_clear_hotplug_interrupts(dp);
> +		break;
> +	case DP_IRQ_TYPE_HP_CABLE_OUT:
> +		dev_dbg(dp->dev, "Received irq - cable out\n");
> +		analogix_dp_clear_hotplug_interrupts(dp);
> +		break;
> +	case DP_IRQ_TYPE_HP_CHANGE:
> +		/*
> +		 * We get these change notifications once in a while, but there
> +		 * is nothing we can do with them. Just ignore it for now and
> +		 * only handle cable changes.
> +		 */
> +		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
> +		analogix_dp_clear_hotplug_interrupts(dp);
> +		break;
> +	default:
> +		dev_err(dp->dev, "Received irq - unknown type!\n");
> +		break;
> +	}
> +	return IRQ_HANDLED;
> +}
> +
> +static void analogix_dp_hotplug(struct work_struct *work)
> +{
> +	struct analogix_dp_device *dp;
> +
> +	dp = container_of(work, struct analogix_dp_device, hotplug_work);
> +
> +	if (dp->drm_dev)
> +		drm_helper_hpd_irq_event(dp->drm_dev);
> +}
> +
> +static void analogix_dp_commit(struct analogix_dp_device *dp)
> +{
> +	int ret;
> +
> +	/* Keep the panel disabled while we configure video */
> +	if (dp->plat_data->panel) {
> +		if (drm_panel_disable(dp->plat_data->panel))
> +			DRM_ERROR("failed to disable the panel\n");
> +	}
> +
> +	ret = analogix_dp_detect_hpd(dp);
> +	if (ret) {
> +		/* Cable has been disconnected, we're done */
> +		return;
> +	}
> +
> +	ret = analogix_dp_handle_edid(dp);
> +	if (ret) {
> +		dev_err(dp->dev, "unable to handle edid\n");
> +		return;
> +	}
> +
> +	ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
> +					dp->video_info->link_rate);
> +	if (ret) {
> +		dev_err(dp->dev, "unable to do link train\n");
> +		return;
> +	}
> +
> +	analogix_dp_enable_scramble(dp, 1);
> +	analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
> +	analogix_dp_enable_enhanced_mode(dp, 1);
> +
> +	analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
> +	analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
> +
> +	analogix_dp_init_video(dp);
> +	ret = analogix_dp_config_video(dp);
> +	if (ret)
> +		dev_err(dp->dev, "unable to config video\n");
> +
> +	/* Safe to enable the panel now */
> +	if (dp->plat_data->panel) {
> +		if (drm_panel_enable(dp->plat_data->panel))
> +			DRM_ERROR("failed to enable the panel\n");
> +	}
> +
> +	/* Enable video */
> +	analogix_dp_start_video(dp);
> +}
> +
> +int analogix_dp_get_modes(struct drm_connector *connector)
> +{
> +	struct analogix_dp_device *dp = to_dp(connector);
> +	int num_modes = 0;
> +
> +	if (dp->plat_data->panel)
> +		num_modes += drm_panel_get_modes(dp->plat_data->panel);
> +
> +	if (dp->plat_data->get_modes)
> +		num_modes += dp->plat_data->get_modes(dp->plat_data);
> +
> +	return num_modes;
> +}
> +
> +static struct drm_encoder *
> +analogix_dp_best_encoder(struct drm_connector *connector)
> +{
> +	struct analogix_dp_device *dp = to_dp(connector);
> +
> +	return dp->encoder;
> +}
> +
> +static const struct drm_connector_helper_funcs analogix_dp_connector_helper_funcs = {
> +	.get_modes = analogix_dp_get_modes,
> +	.best_encoder = analogix_dp_best_encoder,
> +};
> +
> +enum drm_connector_status
> +analogix_dp_detect(struct drm_connector *connector, bool force)
> +{
> +	return connector_status_connected;
> +}
> +
> +static void analogix_dp_connector_destroy(struct drm_connector *connector)
> +{
> +	drm_connector_unregister(connector);
> +	drm_connector_cleanup(connector);
> +}
> +
> +static const struct drm_connector_funcs analogix_dp_connector_funcs = {
> +	.dpms = drm_atomic_helper_connector_dpms,
> +	.fill_modes = drm_helper_probe_single_connector_modes,
> +	.detect = analogix_dp_detect,
> +	.destroy = analogix_dp_connector_destroy,
> +	.reset = drm_atomic_helper_connector_reset,
> +	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> +	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> +};
> +
> +static int analogix_dp_bridge_attach(struct drm_bridge *bridge)
> +{
> +	struct analogix_dp_device *dp = bridge->driver_private;
> +	struct drm_encoder *encoder = dp->encoder;
> +	struct drm_connector *connector = &dp->connector;
> +	int ret;
> +
> +	if (!bridge->encoder) {
> +		DRM_ERROR("Parent encoder object not found");
> +		return -ENODEV;
> +	}
> +
> +	connector->polled = DRM_CONNECTOR_POLL_HPD;
> +
> +	ret = drm_connector_init(dp->drm_dev, connector,
> +				 &analogix_dp_connector_funcs,
> +				 DRM_MODE_CONNECTOR_eDP);
> +	if (ret) {
> +		DRM_ERROR("Failed to initialize connector with drm\n");
> +		return ret;
> +	}
> +
> +	drm_connector_helper_add(connector,
> +				 &analogix_dp_connector_helper_funcs);
> +	drm_mode_connector_attach_encoder(connector, encoder);
> +
> +	/*
> +	 * NOTE: the connector registration is implemented in analogix
> +	 * platform driver, that to say connector would be exist after
> +	 * plat_data->attch return, that's why we record the connector
> +	 * point after plat attached.
> +	 */
> +	 if (dp->plat_data->attach) {
> +		 ret = dp->plat_data->attach(dp->plat_data, bridge, connector);
> +		 if (ret) {
> +			 DRM_ERROR("Failed at platform attch func\n");
> +			 return ret;
> +		 }
> +	}
> +
> +	if (dp->plat_data->panel) {
> +		ret = drm_panel_attach(dp->plat_data->panel, &dp->connector);
> +		if (ret) {
> +			DRM_ERROR("Failed to attach panel\n");
> +			return ret;
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +static void analogix_dp_bridge_enable(struct drm_bridge *bridge)
> +{
> +	struct analogix_dp_device *dp = bridge->driver_private;
> +
> +	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
> +		return;
> +
> +	pm_runtime_get_sync(dp->dev);
> +
> +	if (dp->plat_data->panel) {
> +		if (drm_panel_prepare(dp->plat_data->panel)) {
> +			DRM_ERROR("failed to setup the panel\n");
> +			return;
> +		}
> +	}
> +
> +	if (dp->plat_data->power_on)
> +		dp->plat_data->power_on(dp->plat_data);
> +
> +	phy_power_on(dp->phy);
> +	analogix_dp_init_dp(dp);
> +	enable_irq(dp->irq);
> +	analogix_dp_commit(dp);
> +
> +	dp->dpms_mode = DRM_MODE_DPMS_ON;
> +}
> +
> +static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
> +{
> +	struct analogix_dp_device *dp = bridge->driver_private;
> +
> +	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
> +		return;
> +
> +	if (dp->plat_data->panel) {
> +		if (drm_panel_disable(dp->plat_data->panel)) {
> +			DRM_ERROR("failed to disable the panel\n");
> +			return;
> +		}
> +	}
> +
> +	disable_irq(dp->irq);
> +	flush_work(&dp->hotplug_work);
> +	phy_power_off(dp->phy);
> +
> +	if (dp->plat_data->power_off)
> +		dp->plat_data->power_off(dp->plat_data);
> +
> +	if (dp->plat_data->panel) {
> +		if (drm_panel_unprepare(dp->plat_data->panel))
> +			DRM_ERROR("failed to turnoff the panel\n");
> +	}
> +
> +	pm_runtime_put_sync(dp->dev);
> +
> +	dp->dpms_mode = DRM_MODE_DPMS_OFF;
> +}
> +
> +static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
> +{
> +	/* do nothing */
> +}
> +
> +static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
> +	.enable = analogix_dp_bridge_enable,
> +	.disable = analogix_dp_bridge_disable,
> +	.pre_enable = analogix_dp_bridge_nop,
> +	.post_disable = analogix_dp_bridge_nop,
> +	.attach = analogix_dp_bridge_attach,
> +};
> +
> +static int analogix_dp_create_bridge(struct drm_device *drm_dev,
> +				     struct analogix_dp_device *dp)
> +{
> +	struct drm_bridge *bridge;
> +	int ret;
> +
> +	bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
> +	if (!bridge) {
> +		DRM_ERROR("failed to allocate for drm bridge\n");
> +		return -ENOMEM;
> +	}
> +
> +	dp->bridge = bridge;
> +
> +	dp->encoder->bridge = bridge;
> +	bridge->driver_private = dp;
> +	bridge->encoder = dp->encoder;
> +	bridge->funcs = &analogix_dp_bridge_funcs;
> +
> +	ret = drm_bridge_attach(drm_dev, bridge);
> +	if (ret) {
> +		DRM_ERROR("failed to attach drm bridge\n");
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
> +{
> +	struct device_node *dp_node = dev->of_node;
> +	struct video_info *dp_video_config;
> +
> +	dp_video_config = devm_kzalloc(dev,
> +				sizeof(*dp_video_config), GFP_KERNEL);
> +	if (!dp_video_config)
> +		return ERR_PTR(-ENOMEM);
> +
> +	dp_video_config->h_sync_polarity =
> +		of_property_read_bool(dp_node, "hsync-active-high");
> +
> +	dp_video_config->v_sync_polarity =
> +		of_property_read_bool(dp_node, "vsync-active-high");
> +
> +	dp_video_config->interlaced =
> +		of_property_read_bool(dp_node, "interlaced");
> +
> +	if (of_property_read_u32(dp_node, "samsung,color-space",
> +				&dp_video_config->color_space)) {
> +		dev_err(dev, "failed to get color-space\n");
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
> +				&dp_video_config->dynamic_range)) {
> +		dev_err(dev, "failed to get dynamic-range\n");
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> +				&dp_video_config->ycbcr_coeff)) {
> +		dev_err(dev, "failed to get ycbcr-coeff\n");
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	if (of_property_read_u32(dp_node, "samsung,color-depth",
> +				&dp_video_config->color_depth)) {
> +		dev_err(dev, "failed to get color-depth\n");
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	if (of_property_read_u32(dp_node, "samsung,link-rate",
> +				&dp_video_config->link_rate)) {
> +		dev_err(dev, "failed to get link-rate\n");
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	if (of_property_read_u32(dp_node, "samsung,lane-count",
> +				&dp_video_config->lane_count)) {
> +		dev_err(dev, "failed to get lane-count\n");
> +		return ERR_PTR(-EINVAL);
> +	}
> +
> +	return dp_video_config;
> +}
> +
> +int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
> +		     struct analogix_dp_plat_data *plat_data)
> +{
> +	struct platform_device *pdev = to_platform_device(dev);
> +	struct analogix_dp_device *dp;
> +	struct resource *res;
> +	unsigned int irq_flags;
> +	int ret;
> +
> +	if (!plat_data) {
> +		dev_err(dev, "Invalided input plat_data\n");
> +		return -EINVAL;
> +	}
> +
> +	dp = devm_kzalloc(dev, sizeof(struct analogix_dp_device), GFP_KERNEL);
> +	if (!dp)
> +		return -ENOMEM;
> +
> +	dev_set_drvdata(dev, dp);
> +
> +	dp->dev = &pdev->dev;
> +	dp->dpms_mode = DRM_MODE_DPMS_OFF;
> +
> +	/*
> +	 * platform dp driver need containor_of the plat_data to get
> +	 * the driver private data, so we need to store the point of
> +	 * plat_data, not the context of plat_data.
> +	 */
> +	dp->plat_data = plat_data;
> +
> +	dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
> +	if (IS_ERR(dp->video_info))
> +		return PTR_ERR(dp->video_info);
> +
> +	dp->phy = devm_phy_get(dp->dev, "dp");
> +	if (IS_ERR(dp->phy)) {
> +		dev_err(dp->dev, "no DP phy configured\n");
> +		ret = PTR_ERR(dp->phy);
> +		if (ret) {
> +			/*
> +			 * phy itself is not enabled, so we can move forward
> +			 * assigning NULL to phy pointer.
> +			 */
> +			if (ret == -ENOSYS || ret == -ENODEV)
> +				dp->phy = NULL;
> +			else
> +				return ret;
> +		}
> +	}
> +
> +	dp->clock = devm_clk_get(&pdev->dev, "dp");
> +	if (IS_ERR(dp->clock)) {
> +		dev_err(&pdev->dev, "failed to get clock\n");
> +		return PTR_ERR(dp->clock);
> +	}
> +
> +	clk_prepare_enable(dp->clock);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> +	dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
> +	if (IS_ERR(dp->reg_base))
> +		return PTR_ERR(dp->reg_base);
> +
> +	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
> +	if (!gpio_is_valid(dp->hpd_gpio))
> +		dp->hpd_gpio = of_get_named_gpio(dev->of_node,
> +						 "samsung,hpd-gpio", 0);
> +
> +	if (gpio_is_valid(dp->hpd_gpio)) {
> +		/*
> +		 * Set up the hotplug GPIO from the device tree as an interrupt.
> +		 * Simply specifying a different interrupt in the device tree
> +		 * doesn't work since we handle hotplug rather differently when
> +		 * using a GPIO.  We also need the actual GPIO specifier so
> +		 * that we can get the current state of the GPIO.
> +		 */
> +		ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
> +					    "hpd_gpio");
> +		if (ret) {
> +			dev_err(&pdev->dev, "failed to get hpd gpio\n");
> +			return ret;
> +		}
> +		dp->irq = gpio_to_irq(dp->hpd_gpio);
> +		irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
> +	} else {
> +		dp->hpd_gpio = -ENODEV;
> +		dp->irq = platform_get_irq(pdev, 0);
> +		irq_flags = 0;
> +	}
> +
> +	if (dp->irq == -ENXIO) {
> +		dev_err(&pdev->dev, "failed to get irq\n");
> +		return -ENODEV;
> +	}
> +
> +	INIT_WORK(&dp->hotplug_work, analogix_dp_hotplug);
> +
> +	pm_runtime_enable(dev);
> +
> +	ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
> +			irq_flags, "analogix-dp", dp);
> +	if (ret) {
> +		dev_err(&pdev->dev, "failed to request irq\n");
> +		goto err_disable_pm_runtime;
> +	}
> +	disable_irq(dp->irq);
> +
> +	dp->drm_dev = drm_dev;
> +	dp->encoder = dp->plat_data->encoder;
> +
> +	ret = analogix_dp_create_bridge(drm_dev, dp);
> +	if (ret) {
> +		DRM_ERROR("failed to create bridge (%d)\n", ret);
> +		drm_encoder_cleanup(dp->encoder);
> +		goto err_disable_pm_runtime;
> +	}
> +
> +	return 0;
> +
> +err_disable_pm_runtime:
> +	pm_runtime_disable(dev);
> +
> +	return ret;
> +}
> +EXPORT_SYMBOL_GPL(analogix_dp_bind);
> +
> +void analogix_dp_unbind(struct device *dev, struct device *master,
> +			void *data)
> +{
> +	struct analogix_dp_device *dp = dev_get_drvdata(dev);
> +
> +	analogix_dp_bridge_disable(dp->bridge);
> +	pm_runtime_disable(dev);
> +}
> +EXPORT_SYMBOL_GPL(analogix_dp_unbind);
> +
> +#ifdef CONFIG_PM
> +int analogix_dp_suspend(struct device *dev)
> +{
> +	struct analogix_dp_device *dp = dev_get_drvdata(dev);
> +
> +	clk_disable_unprepare(dp->clock);
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(analogix_dp_suspend);
> +
> +int analogix_dp_resume(struct device *dev)
> +{
> +	struct analogix_dp_device *dp = dev_get_drvdata(dev);
> +	int ret;
> +
> +	ret = clk_prepare_enable(dp->clock);
> +	if (ret < 0) {
> +		DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +EXPORT_SYMBOL_GPL(analogix_dp_resume);
> +#endif
> +
> +MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
> +MODULE_DESCRIPTION("Analogix DP Core Driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> new file mode 100644
> index 0000000..0fff745
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> @@ -0,0 +1,277 @@
> +/*
> + * Header file for Analogix DP (Display Port) core interface driver.
> + *
> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> + * Author: Jingoo Han <jg1.han@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +#ifndef _ANALOGIX_DP_CORE_H
> +#define _ANALOGIX_DP_CORE_H
> +
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_dp_helper.h>
> +
> +#define DP_TIMEOUT_LOOP_COUNT 100
> +#define MAX_CR_LOOP 5
> +#define MAX_EQ_LOOP 5
> +
> +enum link_rate_type {
> +	LINK_RATE_1_62GBPS = 0x06,
> +	LINK_RATE_2_70GBPS = 0x0a
> +};
> +
> +enum link_lane_count_type {
> +	LANE_COUNT1 = 1,
> +	LANE_COUNT2 = 2,
> +	LANE_COUNT4 = 4
> +};
> +
> +enum link_training_state {
> +	START,
> +	CLOCK_RECOVERY,
> +	EQUALIZER_TRAINING,
> +	FINISHED,
> +	FAILED
> +};
> +
> +enum voltage_swing_level {
> +	VOLTAGE_LEVEL_0,
> +	VOLTAGE_LEVEL_1,
> +	VOLTAGE_LEVEL_2,
> +	VOLTAGE_LEVEL_3,
> +};
> +
> +enum pre_emphasis_level {
> +	PRE_EMPHASIS_LEVEL_0,
> +	PRE_EMPHASIS_LEVEL_1,
> +	PRE_EMPHASIS_LEVEL_2,
> +	PRE_EMPHASIS_LEVEL_3,
> +};
> +
> +enum pattern_set {
> +	PRBS7,
> +	D10_2,
> +	TRAINING_PTN1,
> +	TRAINING_PTN2,
> +	DP_NONE
> +};
> +
> +enum color_space {
> +	COLOR_RGB,
> +	COLOR_YCBCR422,
> +	COLOR_YCBCR444
> +};
> +
> +enum color_depth {
> +	COLOR_6,
> +	COLOR_8,
> +	COLOR_10,
> +	COLOR_12
> +};
> +
> +enum color_coefficient {
> +	COLOR_YCBCR601,
> +	COLOR_YCBCR709
> +};
> +
> +enum dynamic_range {
> +	VESA,
> +	CEA
> +};
> +
> +enum pll_status {
> +	PLL_UNLOCKED,
> +	PLL_LOCKED
> +};
> +
> +enum clock_recovery_m_value_type {
> +	CALCULATED_M,
> +	REGISTER_M
> +};
> +
> +enum video_timing_recognition_type {
> +	VIDEO_TIMING_FROM_CAPTURE,
> +	VIDEO_TIMING_FROM_REGISTER
> +};
> +
> +enum analog_power_block {
> +	AUX_BLOCK,
> +	CH0_BLOCK,
> +	CH1_BLOCK,
> +	CH2_BLOCK,
> +	CH3_BLOCK,
> +	ANALOG_TOTAL,
> +	POWER_ALL
> +};
> +
> +enum dp_irq_type {
> +	DP_IRQ_TYPE_HP_CABLE_IN,
> +	DP_IRQ_TYPE_HP_CABLE_OUT,
> +	DP_IRQ_TYPE_HP_CHANGE,
> +	DP_IRQ_TYPE_UNKNOWN,
> +};
> +
> +struct video_info {
> +	char *name;
> +
> +	bool h_sync_polarity;
> +	bool v_sync_polarity;
> +	bool interlaced;
> +
> +	enum color_space color_space;
> +	enum dynamic_range dynamic_range;
> +	enum color_coefficient ycbcr_coeff;
> +	enum color_depth color_depth;
> +
> +	enum link_rate_type link_rate;
> +	enum link_lane_count_type lane_count;
> +};
> +
> +struct link_train {
> +	int eq_loop;
> +	int cr_loop[4];
> +
> +	u8 link_rate;
> +	u8 lane_count;
> +	u8 training_lane[4];
> +
> +	enum link_training_state lt_state;
> +};
> +
> +struct analogix_dp_device {
> +	struct drm_encoder	*encoder;
> +	struct device		*dev;
> +	struct drm_device	*drm_dev;
> +	struct drm_connector	connector;
> +	struct drm_bridge	*bridge;
> +	struct clk		*clock;
> +	unsigned int		irq;
> +	void __iomem		*reg_base;
> +
> +	struct video_info	*video_info;
> +	struct link_train	link_train;
> +	struct work_struct	hotplug_work;
> +	struct phy		*phy;
> +	int			dpms_mode;
> +	int			hpd_gpio;
> +
> +	struct analogix_dp_plat_data *plat_data;
> +};
> +
> +/* analogix_dp_reg.c */
> +void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable);
> +void analogix_dp_stop_video(struct analogix_dp_device *dp);
> +void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable);
> +void analogix_dp_init_analog_param(struct analogix_dp_device *dp);
> +void analogix_dp_init_interrupt(struct analogix_dp_device *dp);
> +void analogix_dp_reset(struct analogix_dp_device *dp);
> +void analogix_dp_swreset(struct analogix_dp_device *dp);
> +void analogix_dp_config_interrupt(struct analogix_dp_device *dp);
> +enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp);
> +void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable);
> +void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
> +				       enum analog_power_block block,
> +				       bool enable);
> +void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
> +void analogix_dp_init_hpd(struct analogix_dp_device *dp);
> +enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
> +void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
> +void analogix_dp_reset_aux(struct analogix_dp_device *dp);
> +void analogix_dp_init_aux(struct analogix_dp_device *dp);
> +int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
> +void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
> +int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
> +int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
> +				unsigned int reg_addr,
> +				unsigned char data);
> +int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
> +				unsigned int reg_addr,
> +				unsigned char *data);
> +int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
> +				unsigned int reg_addr,
> +				unsigned int count,
> +				unsigned char data[]);
> +int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
> +				unsigned int reg_addr,
> +				unsigned int count,
> +				unsigned char data[]);
> +int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
> +				unsigned int device_addr,
> +				unsigned int reg_addr);
> +int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
> +				unsigned int device_addr,
> +				unsigned int reg_addr,
> +				unsigned int *data);
> +int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
> +				unsigned int device_addr,
> +				unsigned int reg_addr,
> +				unsigned int count,
> +				unsigned char edid[]);
> +void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
> +void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
> +void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
> +void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
> +void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
> +void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
> +				enum pattern_set pattern);
> +void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
> +void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
> +void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
> +void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
> +void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
> +				u32 training_lane);
> +void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
> +				u32 training_lane);
> +void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
> +				u32 training_lane);
> +void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
> +				u32 training_lane);
> +u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
> +u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
> +u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
> +u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp);
> +void analogix_dp_reset_macro(struct analogix_dp_device *dp);
> +void analogix_dp_init_video(struct analogix_dp_device *dp);
> +
> +void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
> +int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
> +void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
> +			enum clock_recovery_m_value_type type,
> +			u32 m_value,
> +			u32 n_value);
> +void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
> +void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
> +void analogix_dp_start_video(struct analogix_dp_device *dp);
> +int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
> +void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
> +void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
> +void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
> +
> +/* I2C EDID Chip ID, Slave Address */
> +#define I2C_EDID_DEVICE_ADDR			0x50
> +#define I2C_E_EDID_DEVICE_ADDR			0x30
> +
> +#define EDID_BLOCK_LENGTH			0x80
> +#define EDID_HEADER_PATTERN			0x00
> +#define EDID_EXTENSION_FLAG			0x7e
> +#define EDID_CHECKSUM				0x7f
> +
> +/* DP_MAX_LANE_COUNT */
> +#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
> +#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
> +
> +/* DP_LANE_COUNT_SET */
> +#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
> +
> +/* DP_TRAINING_LANE0_SET */
> +#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
> +#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
> +#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
> +#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
> +
> +#endif /* _ANALOGIX_DP_CORE_H */
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> new file mode 100644
> index 0000000..0b926ea
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> @@ -0,0 +1,1263 @@
> +/*
> + * Analogix DP (Display port) core register interface driver.
> + *
> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> + * Author: Jingoo Han <jg1.han@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/device.h>
> +#include <linux/io.h>
> +#include <linux/delay.h>
> +#include <linux/gpio.h>
> +
> +#include "analogix_dp_core.h"
> +#include "analogix_dp_reg.h"
> +
> +#define COMMON_INT_MASK_1	0
> +#define COMMON_INT_MASK_2	0
> +#define COMMON_INT_MASK_3	0
> +#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
> +#define INT_STA_MASK		INT_HPD
> +
> +void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable)
> +{
> +	u32 reg;
> +
> +	if (enable) {
> +		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> +		reg |= HDCP_VIDEO_MUTE;
> +		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> +	} else {
> +		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> +		reg &= ~HDCP_VIDEO_MUTE;
> +		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> +	}
> +}
> +
> +void analogix_dp_stop_video(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> +	reg &= ~VIDEO_EN;
> +	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> +}
> +
> +void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
> +{
> +	u32 reg;
> +
> +	if (enable)
> +		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
> +			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
> +	else
> +		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
> +			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
> +
> +	writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
> +}
> +
> +void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = TX_TERMINAL_CTRL_50_OHM;
> +	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
> +
> +	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
> +	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
> +
> +	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
> +	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
> +
> +	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
> +		TX_CUR1_2X | TX_CUR_16_MA;
> +	writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
> +
> +	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
> +		CH1_AMP_400_MV | CH0_AMP_400_MV;
> +	writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
> +}
> +
> +void analogix_dp_init_interrupt(struct analogix_dp_device *dp)
> +{
> +	/* Set interrupt pin assertion polarity as high */
> +	writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
> +
> +	/* Clear pending regisers */
> +	writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
> +	writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
> +	writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
> +	writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
> +	writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
> +
> +	/* 0:mask,1: unmask */
> +	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
> +	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
> +	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
> +	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
> +	writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
> +}
> +
> +void analogix_dp_reset(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	analogix_dp_stop_video(dp);
> +	analogix_dp_enable_video_mute(dp, 0);
> +
> +	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
> +		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
> +		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
> +	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
> +
> +	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
> +		SERDES_FIFO_FUNC_EN_N |
> +		LS_CLK_DOMAIN_FUNC_EN_N;
> +	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> +
> +	usleep_range(20, 30);
> +
> +	analogix_dp_lane_swap(dp, 0);
> +
> +	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
> +	writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
> +	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> +	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> +
> +	writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
> +	writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
> +
> +	writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
> +	writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
> +
> +	writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
> +
> +	writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
> +
> +	writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
> +	writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
> +
> +	writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
> +	writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
> +
> +	writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
> +}
> +
> +void analogix_dp_swreset(struct analogix_dp_device *dp)
> +{
> +	writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
> +}
> +
> +void analogix_dp_config_interrupt(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	/* 0: mask, 1: unmask */
> +	reg = COMMON_INT_MASK_1;
> +	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
> +
> +	reg = COMMON_INT_MASK_2;
> +	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
> +
> +	reg = COMMON_INT_MASK_3;
> +	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
> +
> +	reg = COMMON_INT_MASK_4;
> +	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
> +
> +	reg = INT_STA_MASK;
> +	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
> +}
> +
> +enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
> +	if (reg & PLL_LOCK)
> +		return PLL_LOCKED;
> +	else
> +		return PLL_UNLOCKED;
> +}
> +
> +void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
> +{
> +	u32 reg;
> +
> +	if (enable) {
> +		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
> +		reg |= DP_PLL_PD;
> +		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
> +	} else {
> +		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
> +		reg &= ~DP_PLL_PD;
> +		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
> +	}
> +}
> +
> +void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
> +				enum analog_power_block block,
> +				bool enable)
> +{
> +	u32 reg;
> +
> +	switch (block) {
> +	case AUX_BLOCK:
> +		if (enable) {
> +			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> +			reg |= AUX_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		} else {
> +			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> +			reg &= ~AUX_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		}
> +		break;
> +	case CH0_BLOCK:
> +		if (enable) {
> +			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> +			reg |= CH0_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		} else {
> +			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> +			reg &= ~CH0_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		}
> +		break;
> +	case CH1_BLOCK:
> +		if (enable) {
> +			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> +			reg |= CH1_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		} else {
> +			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> +			reg &= ~CH1_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		}
> +		break;
> +	case CH2_BLOCK:
> +		if (enable) {
> +			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> +			reg |= CH2_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		} else {
> +			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> +			reg &= ~CH2_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		}
> +		break;
> +	case CH3_BLOCK:
> +		if (enable) {
> +			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> +			reg |= CH3_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		} else {
> +			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> +			reg &= ~CH3_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		}
> +		break;
> +	case ANALOG_TOTAL:
> +		if (enable) {
> +			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> +			reg |= DP_PHY_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		} else {
> +			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> +			reg &= ~DP_PHY_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		}
> +		break;
> +	case POWER_ALL:
> +		if (enable) {
> +			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
> +				CH1_PD | CH0_PD;
> +			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		} else {
> +			writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
> +		}
> +		break;
> +	default:
> +		break;
> +	}
> +}
> +
> +void analogix_dp_init_analog_func(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +	int timeout_loop = 0;
> +
> +	analogix_dp_set_analog_power_down(dp, POWER_ALL, 0);
> +
> +	reg = PLL_LOCK_CHG;
> +	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
> +	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
> +	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
> +
> +	/* Power up PLL */
> +	if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
> +		analogix_dp_set_pll_power_down(dp, 0);
> +
> +		while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
> +			timeout_loop++;
> +			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> +				dev_err(dp->dev, "failed to get pll lock status\n");
> +				return;
> +			}
> +			usleep_range(10, 20);
> +		}
> +	}
> +
> +	/* Enable Serdes FIFO function and Link symbol clock domain module */
> +	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> +	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
> +		| AUX_FUNC_EN_N);
> +	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> +}
> +
> +void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	if (gpio_is_valid(dp->hpd_gpio))
> +		return;
> +
> +	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
> +	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
> +
> +	reg = INT_HPD;
> +	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
> +}
> +
> +void analogix_dp_init_hpd(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	if (gpio_is_valid(dp->hpd_gpio))
> +		return;
> +
> +	analogix_dp_clear_hotplug_interrupts(dp);
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> +	reg &= ~(F_HPD | HPD_CTRL);
> +	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> +}
> +
> +enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	if (gpio_is_valid(dp->hpd_gpio)) {
> +		reg = gpio_get_value(dp->hpd_gpio);
> +		if (reg)
> +			return DP_IRQ_TYPE_HP_CABLE_IN;
> +		else
> +			return DP_IRQ_TYPE_HP_CABLE_OUT;
> +	} else {
> +		/* Parse hotplug interrupt status register */
> +		reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
> +
> +		if (reg & PLUG)
> +			return DP_IRQ_TYPE_HP_CABLE_IN;
> +
> +		if (reg & HPD_LOST)
> +			return DP_IRQ_TYPE_HP_CABLE_OUT;
> +
> +		if (reg & HOTPLUG_CHG)
> +			return DP_IRQ_TYPE_HP_CHANGE;
> +
> +		return DP_IRQ_TYPE_UNKNOWN;
> +	}
> +}
> +
> +void analogix_dp_reset_aux(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	/* Disable AUX channel module */
> +	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> +	reg |= AUX_FUNC_EN_N;
> +	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> +}
> +
> +void analogix_dp_init_aux(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	/* Clear inerrupts related to AUX channel */
> +	reg = RPLY_RECEIV | AUX_ERR;
> +	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
> +
> +	analogix_dp_reset_aux(dp);
> +
> +	/* Disable AUX transaction H/W retry */
> +	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
> +		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> +	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
> +
> +	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
> +	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
> +	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
> +
> +	/* Enable AUX channel module */
> +	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> +	reg &= ~AUX_FUNC_EN_N;
> +	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> +}
> +
> +int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	if (gpio_is_valid(dp->hpd_gpio)) {
> +		if (gpio_get_value(dp->hpd_gpio))
> +			return 0;
> +	} else {
> +		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> +		if (reg & HPD_STATUS)
> +			return 0;
> +	}
> +
> +	return -EINVAL;
> +}
> +
> +void analogix_dp_enable_sw_function(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
> +	reg &= ~SW_FUNC_EN_N;
> +	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
> +}
> +
> +int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
> +{
> +	int reg;
> +	int retval = 0;
> +	int timeout_loop = 0;
> +
> +	/* Enable AUX CH operation */
> +	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
> +	reg |= AUX_EN;
> +	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
> +
> +	/* Is AUX CH command reply received? */
> +	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
> +	while (!(reg & RPLY_RECEIV)) {
> +		timeout_loop++;
> +		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> +			dev_err(dp->dev, "AUX CH command reply failed!\n");
> +			return -ETIMEDOUT;
> +		}
> +		reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
> +		usleep_range(10, 11);
> +	}
> +
> +	/* Clear interrupt source for AUX CH command reply */
> +	writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
> +
> +	/* Clear interrupt source for AUX CH access error */
> +	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
> +	if (reg & AUX_ERR) {
> +		writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
> +		return -EREMOTEIO;
> +	}
> +
> +	/* Check AUX CH error access status */
> +	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
> +	if ((reg & AUX_STATUS_MASK) != 0) {
> +		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
> +			reg & AUX_STATUS_MASK);
> +		return -EREMOTEIO;
> +	}
> +
> +	return retval;
> +}
> +
> +int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
> +				unsigned int reg_addr,
> +				unsigned char data)
> +{
> +	u32 reg;
> +	int i;
> +	int retval;
> +
> +	for (i = 0; i < 3; i++) {
> +		/* Clear AUX CH data buffer */
> +		reg = BUF_CLR;
> +		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
> +
> +		/* Select DPCD device address */
> +		reg = AUX_ADDR_7_0(reg_addr);
> +		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
> +		reg = AUX_ADDR_15_8(reg_addr);
> +		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
> +		reg = AUX_ADDR_19_16(reg_addr);
> +		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
> +
> +		/* Write data buffer */
> +		reg = (unsigned int)data;
> +		writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
> +
> +		/*
> +		 * Set DisplayPort transaction and write 1 byte
> +		 * If bit 3 is 1, DisplayPort transaction.
> +		 * If Bit 3 is 0, I2C transaction.
> +		 */
> +		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
> +		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
> +
> +		/* Start AUX transaction */
> +		retval = analogix_dp_start_aux_transaction(dp);
> +		if (retval == 0)
> +			break;
> +		else
> +			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> +				__func__);
> +	}
> +
> +	return retval;
> +}
> +
> +int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
> +				unsigned int reg_addr,
> +				unsigned char *data)
> +{
> +	u32 reg;
> +	int i;
> +	int retval;
> +
> +	for (i = 0; i < 3; i++) {
> +		/* Clear AUX CH data buffer */
> +		reg = BUF_CLR;
> +		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
> +
> +		/* Select DPCD device address */
> +		reg = AUX_ADDR_7_0(reg_addr);
> +		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
> +		reg = AUX_ADDR_15_8(reg_addr);
> +		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
> +		reg = AUX_ADDR_19_16(reg_addr);
> +		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
> +
> +		/*
> +		 * Set DisplayPort transaction and read 1 byte
> +		 * If bit 3 is 1, DisplayPort transaction.
> +		 * If Bit 3 is 0, I2C transaction.
> +		 */
> +		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
> +		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
> +
> +		/* Start AUX transaction */
> +		retval = analogix_dp_start_aux_transaction(dp);
> +		if (retval == 0)
> +			break;
> +		else
> +			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> +				__func__);
> +	}
> +
> +	/* Read data buffer */
> +	reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
> +	*data = (unsigned char)(reg & 0xff);
> +
> +	return retval;
> +}
> +
> +int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
> +				unsigned int reg_addr,
> +				unsigned int count,
> +				unsigned char data[])
> +{
> +	u32 reg;
> +	unsigned int start_offset;
> +	unsigned int cur_data_count;
> +	unsigned int cur_data_idx;
> +	int i;
> +	int retval = 0;
> +
> +	/* Clear AUX CH data buffer */
> +	reg = BUF_CLR;
> +	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
> +
> +	start_offset = 0;
> +	while (start_offset < count) {
> +		/* Buffer size of AUX CH is 16 * 4bytes */
> +		if ((count - start_offset) > 16)
> +			cur_data_count = 16;
> +		else
> +			cur_data_count = count - start_offset;
> +
> +		for (i = 0; i < 3; i++) {
> +			/* Select DPCD device address */
> +			reg = AUX_ADDR_7_0(reg_addr + start_offset);
> +			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
> +			reg = AUX_ADDR_15_8(reg_addr + start_offset);
> +			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
> +			reg = AUX_ADDR_19_16(reg_addr + start_offset);
> +			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
> +
> +			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
> +			     cur_data_idx++) {
> +				reg = data[start_offset + cur_data_idx];
> +				writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
> +							  + 4 * cur_data_idx);
> +			}
> +
> +			/*
> +			 * Set DisplayPort transaction and write
> +			 * If bit 3 is 1, DisplayPort transaction.
> +			 * If Bit 3 is 0, I2C transaction.
> +			 */
> +			reg = AUX_LENGTH(cur_data_count) |
> +				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
> +			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
> +
> +			/* Start AUX transaction */
> +			retval = analogix_dp_start_aux_transaction(dp);
> +			if (retval == 0)
> +				break;
> +			else
> +				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> +					__func__);
> +		}
> +
> +		start_offset += cur_data_count;
> +	}
> +
> +	return retval;
> +}
> +
> +int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
> +				unsigned int reg_addr,
> +				unsigned int count,
> +				unsigned char data[])
> +{
> +	u32 reg;
> +	unsigned int start_offset;
> +	unsigned int cur_data_count;
> +	unsigned int cur_data_idx;
> +	int i;
> +	int retval = 0;
> +
> +	/* Clear AUX CH data buffer */
> +	reg = BUF_CLR;
> +	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
> +
> +	start_offset = 0;
> +	while (start_offset < count) {
> +		/* Buffer size of AUX CH is 16 * 4bytes */
> +		if ((count - start_offset) > 16)
> +			cur_data_count = 16;
> +		else
> +			cur_data_count = count - start_offset;
> +
> +		/* AUX CH Request Transaction process */
> +		for (i = 0; i < 3; i++) {
> +			/* Select DPCD device address */
> +			reg = AUX_ADDR_7_0(reg_addr + start_offset);
> +			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
> +			reg = AUX_ADDR_15_8(reg_addr + start_offset);
> +			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
> +			reg = AUX_ADDR_19_16(reg_addr + start_offset);
> +			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
> +
> +			/*
> +			 * Set DisplayPort transaction and read
> +			 * If bit 3 is 1, DisplayPort transaction.
> +			 * If Bit 3 is 0, I2C transaction.
> +			 */
> +			reg = AUX_LENGTH(cur_data_count) |
> +				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
> +			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
> +
> +			/* Start AUX transaction */
> +			retval = analogix_dp_start_aux_transaction(dp);
> +			if (retval == 0)
> +				break;
> +			else
> +				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> +					__func__);
> +		}
> +
> +		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
> +		    cur_data_idx++) {
> +			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
> +						 + 4 * cur_data_idx);
> +			data[start_offset + cur_data_idx] =
> +				(unsigned char)reg;
> +		}
> +
> +		start_offset += cur_data_count;
> +	}
> +
> +	return retval;
> +}
> +
> +int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
> +				unsigned int device_addr,
> +				unsigned int reg_addr)
> +{
> +	u32 reg;
> +	int retval;
> +
> +	/* Set EDID device address */
> +	reg = device_addr;
> +	writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
> +	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
> +	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
> +
> +	/* Set offset from base address of EDID device */
> +	writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
> +
> +	/*
> +	 * Set I2C transaction and write address
> +	 * If bit 3 is 1, DisplayPort transaction.
> +	 * If Bit 3 is 0, I2C transaction.
> +	 */
> +	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
> +		AUX_TX_COMM_WRITE;
> +	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
> +
> +	/* Start AUX transaction */
> +	retval = analogix_dp_start_aux_transaction(dp);
> +	if (retval != 0)
> +		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
> +
> +	return retval;
> +}
> +
> +int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
> +				unsigned int device_addr,
> +				unsigned int reg_addr,
> +				unsigned int *data)
> +{
> +	u32 reg;
> +	int i;
> +	int retval;
> +
> +	for (i = 0; i < 3; i++) {
> +		/* Clear AUX CH data buffer */
> +		reg = BUF_CLR;
> +		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
> +
> +		/* Select EDID device */
> +		retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
> +		if (retval != 0)
> +			continue;
> +
> +		/*
> +		 * Set I2C transaction and read data
> +		 * If bit 3 is 1, DisplayPort transaction.
> +		 * If Bit 3 is 0, I2C transaction.
> +		 */
> +		reg = AUX_TX_COMM_I2C_TRANSACTION |
> +			AUX_TX_COMM_READ;
> +		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
> +
> +		/* Start AUX transaction */
> +		retval = analogix_dp_start_aux_transaction(dp);
> +		if (retval == 0)
> +			break;
> +		else
> +			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> +				__func__);
> +	}
> +
> +	/* Read data */
> +	if (retval == 0)
> +		*data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
> +
> +	return retval;
> +}
> +
> +int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
> +				unsigned int device_addr,
> +				unsigned int reg_addr,
> +				unsigned int count,
> +				unsigned char edid[])
> +{
> +	u32 reg;
> +	unsigned int i, j;
> +	unsigned int cur_data_idx;
> +	unsigned int defer = 0;
> +	int retval = 0;
> +
> +	for (i = 0; i < count; i += 16) {
> +		for (j = 0; j < 3; j++) {
> +			/* Clear AUX CH data buffer */
> +			reg = BUF_CLR;
> +			writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
> +
> +			/* Set normal AUX CH command */
> +			reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
> +			reg &= ~ADDR_ONLY;
> +			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
> +
> +			/*
> +			 * If Rx sends defer, Tx sends only reads
> +			 * request without sending address
> +			 */
> +			if (!defer)
> +				retval = analogix_dp_select_i2c_device(dp,
> +						device_addr, reg_addr + i);
> +			else
> +				defer = 0;
> +
> +			if (retval == 0) {
> +				/*
> +				 * Set I2C transaction and write data
> +				 * If bit 3 is 1, DisplayPort transaction.
> +				 * If Bit 3 is 0, I2C transaction.
> +				 */
> +				reg = AUX_LENGTH(16) |
> +					AUX_TX_COMM_I2C_TRANSACTION |
> +					AUX_TX_COMM_READ;
> +				writel(reg, dp->reg_base +
> +					EXYNOS_DP_AUX_CH_CTL_1);
> +
> +				/* Start AUX transaction */
> +				retval = analogix_dp_start_aux_transaction(dp);
> +				if (retval == 0)
> +					break;
> +				else
> +					dev_dbg(dp->dev,
> +						"%s: Aux Transaction fail!\n",
> +						__func__);
> +			}
> +			/* Check if Rx sends defer */
> +			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
> +			if (reg == AUX_RX_COMM_AUX_DEFER ||
> +				reg == AUX_RX_COMM_I2C_DEFER) {
> +				dev_err(dp->dev, "Defer: %d\n\n", reg);
> +				defer = 1;
> +			}
> +		}
> +
> +		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
> +			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
> +						 + 4 * cur_data_idx);
> +			edid[i + cur_data_idx] = (unsigned char)reg;
> +		}
> +	}
> +
> +	return retval;
> +}
> +
> +void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype)
> +{
> +	u32 reg;
> +
> +	reg = bwtype;
> +	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
> +		writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
> +}
> +
> +void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
> +	*bwtype = reg;
> +}
> +
> +void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count)
> +{
> +	u32 reg;
> +
> +	reg = count;
> +	writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
> +}
> +
> +void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
> +	*count = reg;
> +}
> +
> +void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
> +{
> +	u32 reg;
> +
> +	if (enable) {
> +		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> +		reg |= ENHANCED;
> +		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> +	} else {
> +		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> +		reg &= ~ENHANCED;
> +		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> +	}
> +}
> +
> +void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
> +				enum pattern_set pattern)
> +{
> +	u32 reg;
> +
> +	switch (pattern) {
> +	case PRBS7:
> +		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
> +		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> +		break;
> +	case D10_2:
> +		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
> +		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> +		break;
> +	case TRAINING_PTN1:
> +		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
> +		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> +		break;
> +	case TRAINING_PTN2:
> +		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
> +		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> +		break;
> +	case DP_NONE:
> +		reg = SCRAMBLING_ENABLE |
> +			LINK_QUAL_PATTERN_SET_DISABLE |
> +			SW_TRAINING_PATTERN_SET_NORMAL;
> +		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> +		break;
> +	default:
> +		break;
> +	}
> +}
> +
> +void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
> +	reg &= ~PRE_EMPHASIS_SET_MASK;
> +	reg |= level << PRE_EMPHASIS_SET_SHIFT;
> +	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
> +}
> +
> +void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
> +	reg &= ~PRE_EMPHASIS_SET_MASK;
> +	reg |= level << PRE_EMPHASIS_SET_SHIFT;
> +	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
> +}
> +
> +void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
> +	reg &= ~PRE_EMPHASIS_SET_MASK;
> +	reg |= level << PRE_EMPHASIS_SET_SHIFT;
> +	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
> +}
> +
> +void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
> +	reg &= ~PRE_EMPHASIS_SET_MASK;
> +	reg |= level << PRE_EMPHASIS_SET_SHIFT;
> +	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
> +}
> +
> +void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
> +					u32 training_lane)
> +{
> +	u32 reg;
> +
> +	reg = training_lane;
> +	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
> +}
> +
> +void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
> +					u32 training_lane)
> +{
> +	u32 reg;
> +
> +	reg = training_lane;
> +	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
> +}
> +
> +void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
> +					 u32 training_lane)
> +{
> +	u32 reg;
> +
> +	reg = training_lane;
> +	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
> +}
> +
> +void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
> +					u32 training_lane)
> +{
> +	u32 reg;
> +
> +	reg = training_lane;
> +	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
> +}
> +
> +u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
> +	return reg;
> +}
> +
> +u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
> +	return reg;
> +}
> +
> +u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
> +	return reg;
> +}
> +
> +u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
> +	return reg;
> +}
> +
> +void analogix_dp_reset_macro(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
> +	reg |= MACRO_RST;
> +	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
> +
> +	/* 10 us is the minimum reset time. */
> +	usleep_range(10, 20);
> +
> +	reg &= ~MACRO_RST;
> +	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
> +}
> +
> +void analogix_dp_init_video(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
> +	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
> +
> +	reg = 0x0;
> +	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
> +
> +	reg = CHA_CRI(4) | CHA_CTRL;
> +	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
> +
> +	reg = 0x0;
> +	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> +
> +	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
> +	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
> +}
> +
> +void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	/* Configure the input color depth, color space, dynamic range */
> +	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
> +		(dp->video_info->color_depth << IN_BPC_SHIFT) |
> +		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
> +	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
> +
> +	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
> +	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
> +	reg &= ~IN_YC_COEFFI_MASK;
> +	if (dp->video_info->ycbcr_coeff)
> +		reg |= IN_YC_COEFFI_ITU709;
> +	else
> +		reg |= IN_YC_COEFFI_ITU601;
> +	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
> +}
> +
> +int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
> +	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
> +
> +	if (!(reg & DET_STA)) {
> +		dev_dbg(dp->dev, "Input stream clock not detected.\n");
> +		return -EINVAL;
> +	}
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
> +	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
> +	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
> +
> +	if (reg & CHA_STA) {
> +		dev_dbg(dp->dev, "Input stream clk is changing\n");
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
> +		enum clock_recovery_m_value_type type,
> +		u32 m_value,
> +		u32 n_value)
> +{
> +	u32 reg;
> +
> +	if (type == REGISTER_M) {
> +		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> +		reg |= FIX_M_VID;
> +		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> +		reg = m_value & 0xff;
> +		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
> +		reg = (m_value >> 8) & 0xff;
> +		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
> +		reg = (m_value >> 16) & 0xff;
> +		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
> +
> +		reg = n_value & 0xff;
> +		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
> +		reg = (n_value >> 8) & 0xff;
> +		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
> +		reg = (n_value >> 16) & 0xff;
> +		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
> +	} else  {
> +		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> +		reg &= ~FIX_M_VID;
> +		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> +
> +		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
> +		writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
> +		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
> +	}
> +}
> +
> +void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type)
> +{
> +	u32 reg;
> +
> +	if (type == VIDEO_TIMING_FROM_CAPTURE) {
> +		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> +		reg &= ~FORMAT_SEL;
> +		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> +	} else {
> +		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> +		reg |= FORMAT_SEL;
> +		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> +	}
> +}
> +
> +void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable)
> +{
> +	u32 reg;
> +
> +	if (enable) {
> +		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
> +		reg &= ~VIDEO_MODE_MASK;
> +		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
> +		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
> +	} else {
> +		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
> +		reg &= ~VIDEO_MODE_MASK;
> +		reg |= VIDEO_MODE_SLAVE_MODE;
> +		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
> +	}
> +}
> +
> +void analogix_dp_start_video(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> +	reg |= VIDEO_EN;
> +	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> +}
> +
> +int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> +	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> +	if (!(reg & STRM_VALID)) {
> +		dev_dbg(dp->dev, "Input video stream is not detected.\n");
> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
> +	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
> +	reg |= MASTER_VID_FUNC_EN_N;
> +	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> +	reg &= ~INTERACE_SCAN_CFG;
> +	reg |= (dp->video_info->interlaced << 2);
> +	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> +	reg &= ~VSYNC_POLARITY_CFG;
> +	reg |= (dp->video_info->v_sync_polarity << 1);
> +	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> +	reg &= ~HSYNC_POLARITY_CFG;
> +	reg |= (dp->video_info->h_sync_polarity << 0);
> +	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> +
> +	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
> +	writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
> +}
> +
> +void analogix_dp_enable_scrambling(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> +	reg &= ~SCRAMBLING_DISABLE;
> +	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> +}
> +
> +void analogix_dp_disable_scrambling(struct analogix_dp_device *dp)
> +{
> +	u32 reg;
> +
> +	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> +	reg |= SCRAMBLING_DISABLE;
> +	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> +}
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> new file mode 100644
> index 0000000..b9661c9
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
> @@ -0,0 +1,366 @@
> +/*
> + * Register definition file for Analogix DP core driver
> + *
> + * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> + * Author: Jingoo Han <jg1.han@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef _ANALOGIX_DP_REG_H
> +#define _ANALOGIX_DP_REG_H
> +
> +#define EXYNOS_DP_TX_SW_RESET			0x14
> +#define EXYNOS_DP_FUNC_EN_1			0x18
> +#define EXYNOS_DP_FUNC_EN_2			0x1C
> +#define EXYNOS_DP_VIDEO_CTL_1			0x20
> +#define EXYNOS_DP_VIDEO_CTL_2			0x24
> +#define EXYNOS_DP_VIDEO_CTL_3			0x28
> +
> +#define EXYNOS_DP_VIDEO_CTL_8			0x3C
> +#define EXYNOS_DP_VIDEO_CTL_10			0x44
> +
> +#define EXYNOS_DP_LANE_MAP			0x35C
> +
> +#define EXYNOS_DP_ANALOG_CTL_1			0x370
> +#define EXYNOS_DP_ANALOG_CTL_2			0x374
> +#define EXYNOS_DP_ANALOG_CTL_3			0x378
> +#define EXYNOS_DP_PLL_FILTER_CTL_1		0x37C
> +#define EXYNOS_DP_TX_AMP_TUNING_CTL		0x380
> +
> +#define EXYNOS_DP_AUX_HW_RETRY_CTL		0x390
> +
> +#define EXYNOS_DP_COMMON_INT_STA_1		0x3C4
> +#define EXYNOS_DP_COMMON_INT_STA_2		0x3C8
> +#define EXYNOS_DP_COMMON_INT_STA_3		0x3CC
> +#define EXYNOS_DP_COMMON_INT_STA_4		0x3D0
> +#define EXYNOS_DP_INT_STA			0x3DC
> +#define EXYNOS_DP_COMMON_INT_MASK_1		0x3E0
> +#define EXYNOS_DP_COMMON_INT_MASK_2		0x3E4
> +#define EXYNOS_DP_COMMON_INT_MASK_3		0x3E8
> +#define EXYNOS_DP_COMMON_INT_MASK_4		0x3EC
> +#define EXYNOS_DP_INT_STA_MASK			0x3F8
> +#define EXYNOS_DP_INT_CTL			0x3FC
> +
> +#define EXYNOS_DP_SYS_CTL_1			0x600
> +#define EXYNOS_DP_SYS_CTL_2			0x604
> +#define EXYNOS_DP_SYS_CTL_3			0x608
> +#define EXYNOS_DP_SYS_CTL_4			0x60C
> +
> +#define EXYNOS_DP_PKT_SEND_CTL			0x640
> +#define EXYNOS_DP_HDCP_CTL			0x648
> +
> +#define EXYNOS_DP_LINK_BW_SET			0x680
> +#define EXYNOS_DP_LANE_COUNT_SET		0x684
> +#define EXYNOS_DP_TRAINING_PTN_SET		0x688
> +#define EXYNOS_DP_LN0_LINK_TRAINING_CTL		0x68C
> +#define EXYNOS_DP_LN1_LINK_TRAINING_CTL		0x690
> +#define EXYNOS_DP_LN2_LINK_TRAINING_CTL		0x694
> +#define EXYNOS_DP_LN3_LINK_TRAINING_CTL		0x698
> +
> +#define EXYNOS_DP_DEBUG_CTL			0x6C0
> +#define EXYNOS_DP_HPD_DEGLITCH_L		0x6C4
> +#define EXYNOS_DP_HPD_DEGLITCH_H		0x6C8
> +#define EXYNOS_DP_LINK_DEBUG_CTL		0x6E0
> +
> +#define EXYNOS_DP_M_VID_0			0x700
> +#define EXYNOS_DP_M_VID_1			0x704
> +#define EXYNOS_DP_M_VID_2			0x708
> +#define EXYNOS_DP_N_VID_0			0x70C
> +#define EXYNOS_DP_N_VID_1			0x710
> +#define EXYNOS_DP_N_VID_2			0x714
> +
> +#define EXYNOS_DP_PLL_CTL			0x71C
> +#define EXYNOS_DP_PHY_PD			0x720
> +#define EXYNOS_DP_PHY_TEST			0x724
> +
> +#define EXYNOS_DP_VIDEO_FIFO_THRD		0x730
> +#define EXYNOS_DP_AUDIO_MARGIN			0x73C
> +
> +#define EXYNOS_DP_M_VID_GEN_FILTER_TH		0x764
> +#define EXYNOS_DP_M_AUD_GEN_FILTER_TH		0x778
> +#define EXYNOS_DP_AUX_CH_STA			0x780
> +#define EXYNOS_DP_AUX_CH_DEFER_CTL		0x788
> +#define EXYNOS_DP_AUX_RX_COMM			0x78C
> +#define EXYNOS_DP_BUFFER_DATA_CTL		0x790
> +#define EXYNOS_DP_AUX_CH_CTL_1			0x794
> +#define EXYNOS_DP_AUX_ADDR_7_0			0x798
> +#define EXYNOS_DP_AUX_ADDR_15_8			0x79C
> +#define EXYNOS_DP_AUX_ADDR_19_16		0x7A0
> +#define EXYNOS_DP_AUX_CH_CTL_2			0x7A4
> +
> +#define EXYNOS_DP_BUF_DATA_0			0x7C0
> +
> +#define EXYNOS_DP_SOC_GENERAL_CTL		0x800
> +
> +/* EXYNOS_DP_TX_SW_RESET */
> +#define RESET_DP_TX				(0x1 << 0)
> +
> +/* EXYNOS_DP_FUNC_EN_1 */
> +#define MASTER_VID_FUNC_EN_N			(0x1 << 7)
> +#define SLAVE_VID_FUNC_EN_N			(0x1 << 5)
> +#define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
> +#define AUD_FUNC_EN_N				(0x1 << 3)
> +#define HDCP_FUNC_EN_N				(0x1 << 2)
> +#define CRC_FUNC_EN_N				(0x1 << 1)
> +#define SW_FUNC_EN_N				(0x1 << 0)
> +
> +/* EXYNOS_DP_FUNC_EN_2 */
> +#define SSC_FUNC_EN_N				(0x1 << 7)
> +#define AUX_FUNC_EN_N				(0x1 << 2)
> +#define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
> +#define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
> +
> +/* EXYNOS_DP_VIDEO_CTL_1 */
> +#define VIDEO_EN				(0x1 << 7)
> +#define HDCP_VIDEO_MUTE				(0x1 << 6)
> +
> +/* EXYNOS_DP_VIDEO_CTL_1 */
> +#define IN_D_RANGE_MASK				(0x1 << 7)
> +#define IN_D_RANGE_SHIFT			(7)
> +#define IN_D_RANGE_CEA				(0x1 << 7)
> +#define IN_D_RANGE_VESA				(0x0 << 7)
> +#define IN_BPC_MASK				(0x7 << 4)
> +#define IN_BPC_SHIFT				(4)
> +#define IN_BPC_12_BITS				(0x3 << 4)
> +#define IN_BPC_10_BITS				(0x2 << 4)
> +#define IN_BPC_8_BITS				(0x1 << 4)
> +#define IN_BPC_6_BITS				(0x0 << 4)
> +#define IN_COLOR_F_MASK				(0x3 << 0)
> +#define IN_COLOR_F_SHIFT			(0)
> +#define IN_COLOR_F_YCBCR444			(0x2 << 0)
> +#define IN_COLOR_F_YCBCR422			(0x1 << 0)
> +#define IN_COLOR_F_RGB				(0x0 << 0)
> +
> +/* EXYNOS_DP_VIDEO_CTL_3 */
> +#define IN_YC_COEFFI_MASK			(0x1 << 7)
> +#define IN_YC_COEFFI_SHIFT			(7)
> +#define IN_YC_COEFFI_ITU709			(0x1 << 7)
> +#define IN_YC_COEFFI_ITU601			(0x0 << 7)
> +#define VID_CHK_UPDATE_TYPE_MASK		(0x1 << 4)
> +#define VID_CHK_UPDATE_TYPE_SHIFT		(4)
> +#define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
> +#define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
> +
> +/* EXYNOS_DP_VIDEO_CTL_8 */
> +#define VID_HRES_TH(x)				(((x) & 0xf) << 4)
> +#define VID_VRES_TH(x)				(((x) & 0xf) << 0)
> +
> +/* EXYNOS_DP_VIDEO_CTL_10 */
> +#define FORMAT_SEL				(0x1 << 4)
> +#define INTERACE_SCAN_CFG			(0x1 << 2)
> +#define VSYNC_POLARITY_CFG			(0x1 << 1)
> +#define HSYNC_POLARITY_CFG			(0x1 << 0)
> +
> +/* EXYNOS_DP_LANE_MAP */
> +#define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
> +#define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
> +#define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
> +#define LANE3_MAP_LOGIC_LANE_3			(0x3 << 6)
> +#define LANE2_MAP_LOGIC_LANE_0			(0x0 << 4)
> +#define LANE2_MAP_LOGIC_LANE_1			(0x1 << 4)
> +#define LANE2_MAP_LOGIC_LANE_2			(0x2 << 4)
> +#define LANE2_MAP_LOGIC_LANE_3			(0x3 << 4)
> +#define LANE1_MAP_LOGIC_LANE_0			(0x0 << 2)
> +#define LANE1_MAP_LOGIC_LANE_1			(0x1 << 2)
> +#define LANE1_MAP_LOGIC_LANE_2			(0x2 << 2)
> +#define LANE1_MAP_LOGIC_LANE_3			(0x3 << 2)
> +#define LANE0_MAP_LOGIC_LANE_0			(0x0 << 0)
> +#define LANE0_MAP_LOGIC_LANE_1			(0x1 << 0)
> +#define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
> +#define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
> +
> +/* EXYNOS_DP_ANALOG_CTL_1 */
> +#define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
> +
> +/* EXYNOS_DP_ANALOG_CTL_2 */
> +#define SEL_24M					(0x1 << 3)
> +#define TX_DVDD_BIT_1_0625V			(0x4 << 0)
> +
> +/* EXYNOS_DP_ANALOG_CTL_3 */
> +#define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
> +#define VCO_BIT_600_MICRO			(0x5 << 0)
> +
> +/* EXYNOS_DP_PLL_FILTER_CTL_1 */
> +#define PD_RING_OSC				(0x1 << 6)
> +#define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
> +#define TX_CUR1_2X				(0x1 << 2)
> +#define TX_CUR_16_MA				(0x3 << 0)
> +
> +/* EXYNOS_DP_TX_AMP_TUNING_CTL */
> +#define CH3_AMP_400_MV				(0x0 << 24)
> +#define CH2_AMP_400_MV				(0x0 << 16)
> +#define CH1_AMP_400_MV				(0x0 << 8)
> +#define CH0_AMP_400_MV				(0x0 << 0)
> +
> +/* EXYNOS_DP_AUX_HW_RETRY_CTL */
> +#define AUX_BIT_PERIOD_EXPECTED_DELAY(x)	(((x) & 0x7) << 8)
> +#define AUX_HW_RETRY_INTERVAL_MASK		(0x3 << 3)
> +#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS	(0x0 << 3)
> +#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS	(0x1 << 3)
> +#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS	(0x2 << 3)
> +#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS	(0x3 << 3)
> +#define AUX_HW_RETRY_COUNT_SEL(x)		(((x) & 0x7) << 0)
> +
> +/* EXYNOS_DP_COMMON_INT_STA_1 */
> +#define VSYNC_DET				(0x1 << 7)
> +#define PLL_LOCK_CHG				(0x1 << 6)
> +#define SPDIF_ERR				(0x1 << 5)
> +#define SPDIF_UNSTBL				(0x1 << 4)
> +#define VID_FORMAT_CHG				(0x1 << 3)
> +#define AUD_CLK_CHG				(0x1 << 2)
> +#define VID_CLK_CHG				(0x1 << 1)
> +#define SW_INT					(0x1 << 0)
> +
> +/* EXYNOS_DP_COMMON_INT_STA_2 */
> +#define ENC_EN_CHG				(0x1 << 6)
> +#define HW_BKSV_RDY				(0x1 << 3)
> +#define HW_SHA_DONE				(0x1 << 2)
> +#define HW_AUTH_STATE_CHG			(0x1 << 1)
> +#define HW_AUTH_DONE				(0x1 << 0)
> +
> +/* EXYNOS_DP_COMMON_INT_STA_3 */
> +#define AFIFO_UNDER				(0x1 << 7)
> +#define AFIFO_OVER				(0x1 << 6)
> +#define R0_CHK_FLAG				(0x1 << 5)
> +
> +/* EXYNOS_DP_COMMON_INT_STA_4 */
> +#define PSR_ACTIVE				(0x1 << 7)
> +#define PSR_INACTIVE				(0x1 << 6)
> +#define SPDIF_BI_PHASE_ERR			(0x1 << 5)
> +#define HOTPLUG_CHG				(0x1 << 2)
> +#define HPD_LOST				(0x1 << 1)
> +#define PLUG					(0x1 << 0)
> +
> +/* EXYNOS_DP_INT_STA */
> +#define INT_HPD					(0x1 << 6)
> +#define HW_TRAINING_FINISH			(0x1 << 5)
> +#define RPLY_RECEIV				(0x1 << 1)
> +#define AUX_ERR					(0x1 << 0)
> +
> +/* EXYNOS_DP_INT_CTL */
> +#define SOFT_INT_CTRL				(0x1 << 2)
> +#define INT_POL1				(0x1 << 1)
> +#define INT_POL0				(0x1 << 0)
> +
> +/* EXYNOS_DP_SYS_CTL_1 */
> +#define DET_STA					(0x1 << 2)
> +#define FORCE_DET				(0x1 << 1)
> +#define DET_CTRL				(0x1 << 0)
> +
> +/* EXYNOS_DP_SYS_CTL_2 */
> +#define CHA_CRI(x)				(((x) & 0xf) << 4)
> +#define CHA_STA					(0x1 << 2)
> +#define FORCE_CHA				(0x1 << 1)
> +#define CHA_CTRL				(0x1 << 0)
> +
> +/* EXYNOS_DP_SYS_CTL_3 */
> +#define HPD_STATUS				(0x1 << 6)
> +#define F_HPD					(0x1 << 5)
> +#define HPD_CTRL				(0x1 << 4)
> +#define HDCP_RDY				(0x1 << 3)
> +#define STRM_VALID				(0x1 << 2)
> +#define F_VALID					(0x1 << 1)
> +#define VALID_CTRL				(0x1 << 0)
> +
> +/* EXYNOS_DP_SYS_CTL_4 */
> +#define FIX_M_AUD				(0x1 << 4)
> +#define ENHANCED				(0x1 << 3)
> +#define FIX_M_VID				(0x1 << 2)
> +#define M_VID_UPDATE_CTRL			(0x3 << 0)
> +
> +/* EXYNOS_DP_TRAINING_PTN_SET */
> +#define SCRAMBLER_TYPE				(0x1 << 9)
> +#define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
> +#define SCRAMBLING_DISABLE			(0x1 << 5)
> +#define SCRAMBLING_ENABLE			(0x0 << 5)
> +#define LINK_QUAL_PATTERN_SET_MASK		(0x3 << 2)
> +#define LINK_QUAL_PATTERN_SET_PRBS7		(0x3 << 2)
> +#define LINK_QUAL_PATTERN_SET_D10_2		(0x1 << 2)
> +#define LINK_QUAL_PATTERN_SET_DISABLE		(0x0 << 2)
> +#define SW_TRAINING_PATTERN_SET_MASK		(0x3 << 0)
> +#define SW_TRAINING_PATTERN_SET_PTN2		(0x2 << 0)
> +#define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
> +#define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
> +
> +/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
> +#define PRE_EMPHASIS_SET_MASK			(0x3 << 3)
> +#define PRE_EMPHASIS_SET_SHIFT			(3)
> +
> +/* EXYNOS_DP_DEBUG_CTL */
> +#define PLL_LOCK				(0x1 << 4)
> +#define F_PLL_LOCK				(0x1 << 3)
> +#define PLL_LOCK_CTRL				(0x1 << 2)
> +#define PN_INV					(0x1 << 0)
> +
> +/* EXYNOS_DP_PLL_CTL */
> +#define DP_PLL_PD				(0x1 << 7)
> +#define DP_PLL_RESET				(0x1 << 6)
> +#define DP_PLL_LOOP_BIT_DEFAULT			(0x1 << 4)
> +#define DP_PLL_REF_BIT_1_1250V			(0x5 << 0)
> +#define DP_PLL_REF_BIT_1_2500V			(0x7 << 0)
> +
> +/* EXYNOS_DP_PHY_PD */
> +#define DP_PHY_PD				(0x1 << 5)
> +#define AUX_PD					(0x1 << 4)
> +#define CH3_PD					(0x1 << 3)
> +#define CH2_PD					(0x1 << 2)
> +#define CH1_PD					(0x1 << 1)
> +#define CH0_PD					(0x1 << 0)
> +
> +/* EXYNOS_DP_PHY_TEST */
> +#define MACRO_RST				(0x1 << 5)
> +#define CH1_TEST				(0x1 << 1)
> +#define CH0_TEST				(0x1 << 0)
> +
> +/* EXYNOS_DP_AUX_CH_STA */
> +#define AUX_BUSY				(0x1 << 4)
> +#define AUX_STATUS_MASK				(0xf << 0)
> +
> +/* EXYNOS_DP_AUX_CH_DEFER_CTL */
> +#define DEFER_CTRL_EN				(0x1 << 7)
> +#define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
> +
> +/* EXYNOS_DP_AUX_RX_COMM */
> +#define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
> +#define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
> +
> +/* EXYNOS_DP_BUFFER_DATA_CTL */
> +#define BUF_CLR					(0x1 << 7)
> +#define BUF_DATA_COUNT(x)			(((x) & 0x1f) << 0)
> +
> +/* EXYNOS_DP_AUX_CH_CTL_1 */
> +#define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
> +#define AUX_TX_COMM_MASK			(0xf << 0)
> +#define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
> +#define AUX_TX_COMM_I2C_TRANSACTION		(0x0 << 3)
> +#define AUX_TX_COMM_MOT				(0x1 << 2)
> +#define AUX_TX_COMM_WRITE			(0x0 << 0)
> +#define AUX_TX_COMM_READ			(0x1 << 0)
> +
> +/* EXYNOS_DP_AUX_ADDR_7_0 */
> +#define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
> +
> +/* EXYNOS_DP_AUX_ADDR_15_8 */
> +#define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
> +
> +/* EXYNOS_DP_AUX_ADDR_19_16 */
> +#define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
> +
> +/* EXYNOS_DP_AUX_CH_CTL_2 */
> +#define ADDR_ONLY				(0x1 << 1)
> +#define AUX_EN					(0x1 << 0)
> +
> +/* EXYNOS_DP_SOC_GENERAL_CTL */
> +#define AUDIO_MODE_SPDIF_MODE			(0x1 << 8)
> +#define AUDIO_MODE_MASTER_MODE			(0x0 << 8)
> +#define MASTER_VIDEO_INTERLACE_EN		(0x1 << 4)
> +#define VIDEO_MASTER_CLK_SEL			(0x1 << 2)
> +#define VIDEO_MASTER_MODE_EN			(0x1 << 1)
> +#define VIDEO_MODE_MASK				(0x1 << 0)
> +#define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
> +#define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
> +
> +#endif /* _ANALOGIX_DP_REG_H */
> diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
> index f17d392..2fadd82 100644
> --- a/drivers/gpu/drm/exynos/Kconfig
> +++ b/drivers/gpu/drm/exynos/Kconfig
> @@ -71,8 +71,9 @@ config DRM_EXYNOS_DSI
>   	  This enables support for Exynos MIPI-DSI device.
>   
>   config DRM_EXYNOS_DP
> -	bool "Display Port"
> +	bool "EXYNOS specific extensions for Analogix DP driver"
>   	depends on DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON
> +	select DRM_ANALOGIX_DP
>   	default DRM_EXYNOS
>   	select DRM_PANEL
>   	help
> diff --git a/drivers/gpu/drm/exynos/Makefile b/drivers/gpu/drm/exynos/Makefile
> index 968b31c..2bdd949 100644
> --- a/drivers/gpu/drm/exynos/Makefile
> +++ b/drivers/gpu/drm/exynos/Makefile
> @@ -12,7 +12,7 @@ exynosdrm-$(CONFIG_DRM_EXYNOS5433_DECON)	+= exynos5433_drm_decon.o
>   exynosdrm-$(CONFIG_DRM_EXYNOS7_DECON)	+= exynos7_drm_decon.o
>   exynosdrm-$(CONFIG_DRM_EXYNOS_DPI)	+= exynos_drm_dpi.o
>   exynosdrm-$(CONFIG_DRM_EXYNOS_DSI)	+= exynos_drm_dsi.o
> -exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o exynos_dp_reg.o
> +exynosdrm-$(CONFIG_DRM_EXYNOS_DP)	+= exynos_dp_core.o
>   exynosdrm-$(CONFIG_DRM_EXYNOS_MIXER)	+= exynos_mixer.o
>   exynosdrm-$(CONFIG_DRM_EXYNOS_HDMI)	+= exynos_hdmi.o
>   exynosdrm-$(CONFIG_DRM_EXYNOS_VIDI)	+= exynos_drm_vidi.o
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
> index cff8dc7..8456794 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
> @@ -14,967 +14,76 @@
>   #include <linux/platform_device.h>
>   #include <linux/err.h>
>   #include <linux/clk.h>
> -#include <linux/io.h>
> -#include <linux/interrupt.h>
> -#include <linux/of.h>
> -#include <linux/of_gpio.h>
>   #include <linux/of_graph.h>
> -#include <linux/gpio.h>
>   #include <linux/component.h>
> -#include <linux/phy/phy.h>
>   #include <video/of_display_timing.h>
>   #include <video/of_videomode.h>
> +#include <video/videomode.h>
>   
>   #include <drm/drmP.h>
>   #include <drm/drm_crtc.h>
>   #include <drm/drm_crtc_helper.h>
> -#include <drm/drm_atomic_helper.h>
>   #include <drm/drm_panel.h>
>   
> -#include "exynos_dp_core.h"
> +#include <drm/bridge/analogix_dp.h>
> +#include <drm/exynos_drm.h>
> +
>   #include "exynos_drm_crtc.h"
>   
> -#define ctx_from_connector(c)	container_of(c, struct exynos_dp_device, \
> -					connector)
> +#define to_dp(nm)	container_of(nm, struct exynos_dp_device, nm)
>   
> -static inline struct exynos_drm_crtc *dp_to_crtc(struct exynos_dp_device *dp)
> -{
> -	return to_exynos_crtc(dp->encoder.crtc);
> -}
> +struct exynos_dp_device {
> +	struct drm_encoder         encoder;
> +	struct drm_connector       connector;
> +	struct drm_bridge          *ptn_bridge;
> +	struct drm_device          *drm_dev;
> +	struct device              *dev;
>   
> -static inline struct exynos_dp_device *encoder_to_dp(
> -						struct drm_encoder *e)
> -{
> -	return container_of(e, struct exynos_dp_device, encoder);
> -}
> -
> -struct bridge_init {
> -	struct i2c_client *client;
> -	struct device_node *node;
> +	struct videomode           vm;
> +	struct analogix_dp_plat_data plat_data;
>   };
>   
> -static void exynos_dp_init_dp(struct exynos_dp_device *dp)
> -{
> -	exynos_dp_reset(dp);
> -
> -	exynos_dp_swreset(dp);
> -
> -	exynos_dp_init_analog_param(dp);
> -	exynos_dp_init_interrupt(dp);
> -
> -	/* SW defined function Normal operation */
> -	exynos_dp_enable_sw_function(dp);
> -
> -	exynos_dp_config_interrupt(dp);
> -	exynos_dp_init_analog_func(dp);
> -
> -	exynos_dp_init_hpd(dp);
> -	exynos_dp_init_aux(dp);
> -}
> -
> -static int exynos_dp_detect_hpd(struct exynos_dp_device *dp)
> -{
> -	int timeout_loop = 0;
> -
> -	while (exynos_dp_get_plug_in_status(dp) != 0) {
> -		timeout_loop++;
> -		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> -			dev_err(dp->dev, "failed to get hpd plug status\n");
> -			return -ETIMEDOUT;
> -		}
> -		usleep_range(10, 11);
> -	}
> -
> -	return 0;
> -}
> -
> -static unsigned char exynos_dp_calc_edid_check_sum(unsigned char *edid_data)
> -{
> -	int i;
> -	unsigned char sum = 0;
> -
> -	for (i = 0; i < EDID_BLOCK_LENGTH; i++)
> -		sum = sum + edid_data[i];
> -
> -	return sum;
> -}
> -
> -static int exynos_dp_read_edid(struct exynos_dp_device *dp)
> -{
> -	unsigned char edid[EDID_BLOCK_LENGTH * 2];
> -	unsigned int extend_block = 0;
> -	unsigned char sum;
> -	unsigned char test_vector;
> -	int retval;
> -
> -	/*
> -	 * EDID device address is 0x50.
> -	 * However, if necessary, you must have set upper address
> -	 * into E-EDID in I2C device, 0x30.
> -	 */
> -
> -	/* Read Extension Flag, Number of 128-byte EDID extension blocks */
> -	retval = exynos_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> -				EDID_EXTENSION_FLAG,
> -				&extend_block);
> -	if (retval)
> -		return retval;
> -
> -	if (extend_block > 0) {
> -		dev_dbg(dp->dev, "EDID data includes a single extension!\n");
> -
> -		/* Read EDID data */
> -		retval = exynos_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
> -						EDID_HEADER_PATTERN,
> -						EDID_BLOCK_LENGTH,
> -						&edid[EDID_HEADER_PATTERN]);
> -		if (retval != 0) {
> -			dev_err(dp->dev, "EDID Read failed!\n");
> -			return -EIO;
> -		}
> -		sum = exynos_dp_calc_edid_check_sum(edid);
> -		if (sum != 0) {
> -			dev_err(dp->dev, "EDID bad checksum!\n");
> -			return -EIO;
> -		}
> -
> -		/* Read additional EDID data */
> -		retval = exynos_dp_read_bytes_from_i2c(dp,
> -				I2C_EDID_DEVICE_ADDR,
> -				EDID_BLOCK_LENGTH,
> -				EDID_BLOCK_LENGTH,
> -				&edid[EDID_BLOCK_LENGTH]);
> -		if (retval != 0) {
> -			dev_err(dp->dev, "EDID Read failed!\n");
> -			return -EIO;
> -		}
> -		sum = exynos_dp_calc_edid_check_sum(&edid[EDID_BLOCK_LENGTH]);
> -		if (sum != 0) {
> -			dev_err(dp->dev, "EDID bad checksum!\n");
> -			return -EIO;
> -		}
> -
> -		exynos_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
> -					&test_vector);
> -		if (test_vector & DP_TEST_LINK_EDID_READ) {
> -			exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TEST_EDID_CHECKSUM,
> -				edid[EDID_BLOCK_LENGTH + EDID_CHECKSUM]);
> -			exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TEST_RESPONSE,
> -				DP_TEST_EDID_CHECKSUM_WRITE);
> -		}
> -	} else {
> -		dev_info(dp->dev, "EDID data does not include any extensions.\n");
> -
> -		/* Read EDID data */
> -		retval = exynos_dp_read_bytes_from_i2c(dp,
> -				I2C_EDID_DEVICE_ADDR,
> -				EDID_HEADER_PATTERN,
> -				EDID_BLOCK_LENGTH,
> -				&edid[EDID_HEADER_PATTERN]);
> -		if (retval != 0) {
> -			dev_err(dp->dev, "EDID Read failed!\n");
> -			return -EIO;
> -		}
> -		sum = exynos_dp_calc_edid_check_sum(edid);
> -		if (sum != 0) {
> -			dev_err(dp->dev, "EDID bad checksum!\n");
> -			return -EIO;
> -		}
> -
> -		exynos_dp_read_byte_from_dpcd(dp,
> -			DP_TEST_REQUEST,
> -			&test_vector);
> -		if (test_vector & DP_TEST_LINK_EDID_READ) {
> -			exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TEST_EDID_CHECKSUM,
> -				edid[EDID_CHECKSUM]);
> -			exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TEST_RESPONSE,
> -				DP_TEST_EDID_CHECKSUM_WRITE);
> -		}
> -	}
> -
> -	dev_dbg(dp->dev, "EDID Read success!\n");
> -	return 0;
> -}
> -
> -static int exynos_dp_handle_edid(struct exynos_dp_device *dp)
> -{
> -	u8 buf[12];
> -	int i;
> -	int retval;
> -
> -	/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
> -	retval = exynos_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
> -				12, buf);
> -	if (retval)
> -		return retval;
> -
> -	/* Read EDID */
> -	for (i = 0; i < 3; i++) {
> -		retval = exynos_dp_read_edid(dp);
> -		if (!retval)
> -			break;
> -	}
> -
> -	return retval;
> -}
> -
> -static void exynos_dp_enable_rx_to_enhanced_mode(struct exynos_dp_device *dp,
> -						bool enable)
> -{
> -	u8 data;
> -
> -	exynos_dp_read_byte_from_dpcd(dp, DP_LANE_COUNT_SET, &data);
> -
> -	if (enable)
> -		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
> -			DP_LANE_COUNT_ENHANCED_FRAME_EN |
> -			DPCD_LANE_COUNT_SET(data));
> -	else
> -		exynos_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
> -			DPCD_LANE_COUNT_SET(data));
> -}
> -
> -static int exynos_dp_is_enhanced_mode_available(struct exynos_dp_device *dp)
> -{
> -	u8 data;
> -	int retval;
> -
> -	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
> -	retval = DPCD_ENHANCED_FRAME_CAP(data);
> -
> -	return retval;
> -}
> -
> -static void exynos_dp_set_enhanced_mode(struct exynos_dp_device *dp)
> -{
> -	u8 data;
> -
> -	data = exynos_dp_is_enhanced_mode_available(dp);
> -	exynos_dp_enable_rx_to_enhanced_mode(dp, data);
> -	exynos_dp_enable_enhanced_mode(dp, data);
> -}
> -
> -static void exynos_dp_training_pattern_dis(struct exynos_dp_device *dp)
> -{
> -	exynos_dp_set_training_pattern(dp, DP_NONE);
> -
> -	exynos_dp_write_byte_to_dpcd(dp,
> -		DP_TRAINING_PATTERN_SET,
> -		DP_TRAINING_PATTERN_DISABLE);
> -}
> -
> -static void exynos_dp_set_lane_lane_pre_emphasis(struct exynos_dp_device *dp,
> -					int pre_emphasis, int lane)
> -{
> -	switch (lane) {
> -	case 0:
> -		exynos_dp_set_lane0_pre_emphasis(dp, pre_emphasis);
> -		break;
> -	case 1:
> -		exynos_dp_set_lane1_pre_emphasis(dp, pre_emphasis);
> -		break;
> -
> -	case 2:
> -		exynos_dp_set_lane2_pre_emphasis(dp, pre_emphasis);
> -		break;
> -
> -	case 3:
> -		exynos_dp_set_lane3_pre_emphasis(dp, pre_emphasis);
> -		break;
> -	}
> -}
> -
> -static int exynos_dp_link_start(struct exynos_dp_device *dp)
> -{
> -	u8 buf[4];
> -	int lane, lane_count, pll_tries, retval;
> -
> -	lane_count = dp->link_train.lane_count;
> -
> -	dp->link_train.lt_state = CLOCK_RECOVERY;
> -	dp->link_train.eq_loop = 0;
> -
> -	for (lane = 0; lane < lane_count; lane++)
> -		dp->link_train.cr_loop[lane] = 0;
> -
> -	/* Set link rate and count as you want to establish*/
> -	exynos_dp_set_link_bandwidth(dp, dp->link_train.link_rate);
> -	exynos_dp_set_lane_count(dp, dp->link_train.lane_count);
> -
> -	/* Setup RX configuration */
> -	buf[0] = dp->link_train.link_rate;
> -	buf[1] = dp->link_train.lane_count;
> -	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
> -				2, buf);
> -	if (retval)
> -		return retval;
> -
> -	/* Set TX pre-emphasis to minimum */
> -	for (lane = 0; lane < lane_count; lane++)
> -		exynos_dp_set_lane_lane_pre_emphasis(dp,
> -			PRE_EMPHASIS_LEVEL_0, lane);
> -
> -	/* Wait for PLL lock */
> -	pll_tries = 0;
> -	while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
> -		if (pll_tries == DP_TIMEOUT_LOOP_COUNT) {
> -			dev_err(dp->dev, "Wait for PLL lock timed out\n");
> -			return -ETIMEDOUT;
> -		}
> -
> -		pll_tries++;
> -		usleep_range(90, 120);
> -	}
> -
> -	/* Set training pattern 1 */
> -	exynos_dp_set_training_pattern(dp, TRAINING_PTN1);
> -
> -	/* Set RX training pattern */
> -	retval = exynos_dp_write_byte_to_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_1);
> -	if (retval)
> -		return retval;
> -
> -	for (lane = 0; lane < lane_count; lane++)
> -		buf[lane] = DP_TRAIN_PRE_EMPH_LEVEL_0 |
> -			    DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
> -
> -	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
> -			lane_count, buf);
> -
> -	return retval;
> -}
> -
> -static unsigned char exynos_dp_get_lane_status(u8 link_status[2], int lane)
> -{
> -	int shift = (lane & 1) * 4;
> -	u8 link_value = link_status[lane>>1];
> -
> -	return (link_value >> shift) & 0xf;
> -}
> -
> -static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
> -{
> -	int lane;
> -	u8 lane_status;
> -
> -	for (lane = 0; lane < lane_count; lane++) {
> -		lane_status = exynos_dp_get_lane_status(link_status, lane);
> -		if ((lane_status & DP_LANE_CR_DONE) == 0)
> -			return -EINVAL;
> -	}
> -	return 0;
> -}
> -
> -static int exynos_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
> -				int lane_count)
> +int exynos_dp_crtc_clock_enable(struct analogix_dp_plat_data *plat_data,
> +				bool enable)
>   {
> -	int lane;
> -	u8 lane_status;
> +	struct exynos_dp_device *dp = to_dp(plat_data);
> +	struct drm_encoder *encoder = &dp->encoder;
> +	struct exynos_drm_crtc *crtc;
>   
> -	if ((link_align & DP_INTERLANE_ALIGN_DONE) == 0)
> -		return -EINVAL;
> +	if (!encoder)
> +		return -1;
>   
> -	for (lane = 0; lane < lane_count; lane++) {
> -		lane_status = exynos_dp_get_lane_status(link_status, lane);
> -		lane_status &= DP_CHANNEL_EQ_BITS;
> -		if (lane_status != DP_CHANNEL_EQ_BITS)
> -			return -EINVAL;
> -	}
> +	crtc = to_exynos_crtc(encoder->crtc);
> +	if (crtc && crtc->ops && crtc->ops->clock_enable)
> +		crtc->ops->clock_enable(crtc, enable);
>   
>   	return 0;
>   }
>   
> -static unsigned char exynos_dp_get_adjust_request_voltage(u8 adjust_request[2],
> -							int lane)
> -{
> -	int shift = (lane & 1) * 4;
> -	u8 link_value = adjust_request[lane>>1];
> -
> -	return (link_value >> shift) & 0x3;
> -}
> -
> -static unsigned char exynos_dp_get_adjust_request_pre_emphasis(
> -					u8 adjust_request[2],
> -					int lane)
> -{
> -	int shift = (lane & 1) * 4;
> -	u8 link_value = adjust_request[lane>>1];
> -
> -	return ((link_value >> shift) & 0xc) >> 2;
> -}
> -
> -static void exynos_dp_set_lane_link_training(struct exynos_dp_device *dp,
> -					u8 training_lane_set, int lane)
> -{
> -	switch (lane) {
> -	case 0:
> -		exynos_dp_set_lane0_link_training(dp, training_lane_set);
> -		break;
> -	case 1:
> -		exynos_dp_set_lane1_link_training(dp, training_lane_set);
> -		break;
> -
> -	case 2:
> -		exynos_dp_set_lane2_link_training(dp, training_lane_set);
> -		break;
> -
> -	case 3:
> -		exynos_dp_set_lane3_link_training(dp, training_lane_set);
> -		break;
> -	}
> -}
> -
> -static unsigned int exynos_dp_get_lane_link_training(
> -				struct exynos_dp_device *dp,
> -				int lane)
> -{
> -	u32 reg;
> -
> -	switch (lane) {
> -	case 0:
> -		reg = exynos_dp_get_lane0_link_training(dp);
> -		break;
> -	case 1:
> -		reg = exynos_dp_get_lane1_link_training(dp);
> -		break;
> -	case 2:
> -		reg = exynos_dp_get_lane2_link_training(dp);
> -		break;
> -	case 3:
> -		reg = exynos_dp_get_lane3_link_training(dp);
> -		break;
> -	default:
> -		WARN_ON(1);
> -		return 0;
> -	}
> -
> -	return reg;
> -}
> -
> -static void exynos_dp_reduce_link_rate(struct exynos_dp_device *dp)
> -{
> -	exynos_dp_training_pattern_dis(dp);
> -	exynos_dp_set_enhanced_mode(dp);
> -
> -	dp->link_train.lt_state = FAILED;
> -}
> -
> -static void exynos_dp_get_adjust_training_lane(struct exynos_dp_device *dp,
> -					u8 adjust_request[2])
> -{
> -	int lane, lane_count;
> -	u8 voltage_swing, pre_emphasis, training_lane;
> -
> -	lane_count = dp->link_train.lane_count;
> -	for (lane = 0; lane < lane_count; lane++) {
> -		voltage_swing = exynos_dp_get_adjust_request_voltage(
> -						adjust_request, lane);
> -		pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
> -						adjust_request, lane);
> -		training_lane = DPCD_VOLTAGE_SWING_SET(voltage_swing) |
> -				DPCD_PRE_EMPHASIS_SET(pre_emphasis);
> -
> -		if (voltage_swing == VOLTAGE_LEVEL_3)
> -			training_lane |= DP_TRAIN_MAX_SWING_REACHED;
> -		if (pre_emphasis == PRE_EMPHASIS_LEVEL_3)
> -			training_lane |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
> -
> -		dp->link_train.training_lane[lane] = training_lane;
> -	}
> -}
> -
> -static int exynos_dp_process_clock_recovery(struct exynos_dp_device *dp)
> -{
> -	int lane, lane_count, retval;
> -	u8 voltage_swing, pre_emphasis, training_lane;
> -	u8 link_status[2], adjust_request[2];
> -
> -	usleep_range(100, 101);
> -
> -	lane_count = dp->link_train.lane_count;
> -
> -	retval =  exynos_dp_read_bytes_from_dpcd(dp,
> -			DP_LANE0_1_STATUS, 2, link_status);
> -	if (retval)
> -		return retval;
> -
> -	retval =  exynos_dp_read_bytes_from_dpcd(dp,
> -			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
> -	if (retval)
> -		return retval;
> -
> -	if (exynos_dp_clock_recovery_ok(link_status, lane_count) == 0) {
> -		/* set training pattern 2 for EQ */
> -		exynos_dp_set_training_pattern(dp, TRAINING_PTN2);
> -
> -		retval = exynos_dp_write_byte_to_dpcd(dp,
> -				DP_TRAINING_PATTERN_SET,
> -				DP_LINK_SCRAMBLING_DISABLE |
> -				DP_TRAINING_PATTERN_2);
> -		if (retval)
> -			return retval;
> -
> -		dev_info(dp->dev, "Link Training Clock Recovery success\n");
> -		dp->link_train.lt_state = EQUALIZER_TRAINING;
> -	} else {
> -		for (lane = 0; lane < lane_count; lane++) {
> -			training_lane = exynos_dp_get_lane_link_training(
> -							dp, lane);
> -			voltage_swing = exynos_dp_get_adjust_request_voltage(
> -							adjust_request, lane);
> -			pre_emphasis = exynos_dp_get_adjust_request_pre_emphasis(
> -							adjust_request, lane);
> -
> -			if (DPCD_VOLTAGE_SWING_GET(training_lane) ==
> -					voltage_swing &&
> -			    DPCD_PRE_EMPHASIS_GET(training_lane) ==
> -					pre_emphasis)
> -				dp->link_train.cr_loop[lane]++;
> -
> -			if (dp->link_train.cr_loop[lane] == MAX_CR_LOOP ||
> -			    voltage_swing == VOLTAGE_LEVEL_3 ||
> -			    pre_emphasis == PRE_EMPHASIS_LEVEL_3) {
> -				dev_err(dp->dev, "CR Max reached (%d,%d,%d)\n",
> -					dp->link_train.cr_loop[lane],
> -					voltage_swing, pre_emphasis);
> -				exynos_dp_reduce_link_rate(dp);
> -				return -EIO;
> -			}
> -		}
> -	}
> -
> -	exynos_dp_get_adjust_training_lane(dp, adjust_request);
> -
> -	for (lane = 0; lane < lane_count; lane++)
> -		exynos_dp_set_lane_link_training(dp,
> -			dp->link_train.training_lane[lane], lane);
> -
> -	retval = exynos_dp_write_bytes_to_dpcd(dp,
> -			DP_TRAINING_LANE0_SET, lane_count,
> -			dp->link_train.training_lane);
> -	if (retval)
> -		return retval;
> -
> -	return retval;
> -}
> -
> -static int exynos_dp_process_equalizer_training(struct exynos_dp_device *dp)
> -{
> -	int lane, lane_count, retval;
> -	u32 reg;
> -	u8 link_align, link_status[2], adjust_request[2];
> -
> -	usleep_range(400, 401);
> -
> -	lane_count = dp->link_train.lane_count;
> -
> -	retval = exynos_dp_read_bytes_from_dpcd(dp,
> -			DP_LANE0_1_STATUS, 2, link_status);
> -	if (retval)
> -		return retval;
> -
> -	if (exynos_dp_clock_recovery_ok(link_status, lane_count)) {
> -		exynos_dp_reduce_link_rate(dp);
> -		return -EIO;
> -	}
> -
> -	retval = exynos_dp_read_bytes_from_dpcd(dp,
> -			DP_ADJUST_REQUEST_LANE0_1, 2, adjust_request);
> -	if (retval)
> -		return retval;
> -
> -	retval = exynos_dp_read_byte_from_dpcd(dp,
> -			DP_LANE_ALIGN_STATUS_UPDATED, &link_align);
> -	if (retval)
> -		return retval;
> -
> -	exynos_dp_get_adjust_training_lane(dp, adjust_request);
> -
> -	if (!exynos_dp_channel_eq_ok(link_status, link_align, lane_count)) {
> -		/* traing pattern Set to Normal */
> -		exynos_dp_training_pattern_dis(dp);
> -
> -		dev_info(dp->dev, "Link Training success!\n");
> -
> -		exynos_dp_get_link_bandwidth(dp, &reg);
> -		dp->link_train.link_rate = reg;
> -		dev_dbg(dp->dev, "final bandwidth = %.2x\n",
> -			dp->link_train.link_rate);
> -
> -		exynos_dp_get_lane_count(dp, &reg);
> -		dp->link_train.lane_count = reg;
> -		dev_dbg(dp->dev, "final lane count = %.2x\n",
> -			dp->link_train.lane_count);
> -
> -		/* set enhanced mode if available */
> -		exynos_dp_set_enhanced_mode(dp);
> -		dp->link_train.lt_state = FINISHED;
> -
> -		return 0;
> -	}
> -
> -	/* not all locked */
> -	dp->link_train.eq_loop++;
> -
> -	if (dp->link_train.eq_loop > MAX_EQ_LOOP) {
> -		dev_err(dp->dev, "EQ Max loop\n");
> -		exynos_dp_reduce_link_rate(dp);
> -		return -EIO;
> -	}
> -
> -	for (lane = 0; lane < lane_count; lane++)
> -		exynos_dp_set_lane_link_training(dp,
> -			dp->link_train.training_lane[lane], lane);
> -
> -	retval = exynos_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
> -			lane_count, dp->link_train.training_lane);
> -
> -	return retval;
> -}
> -
> -static void exynos_dp_get_max_rx_bandwidth(struct exynos_dp_device *dp,
> -					u8 *bandwidth)
> -{
> -	u8 data;
> -
> -	/*
> -	 * For DP rev.1.1, Maximum link rate of Main Link lanes
> -	 * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
> -	 */
> -	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
> -	*bandwidth = data;
> -}
> -
> -static void exynos_dp_get_max_rx_lane_count(struct exynos_dp_device *dp,
> -					u8 *lane_count)
> -{
> -	u8 data;
> -
> -	/*
> -	 * For DP rev.1.1, Maximum number of Main Link lanes
> -	 * 0x01 = 1 lane, 0x02 = 2 lanes, 0x04 = 4 lanes
> -	 */
> -	exynos_dp_read_byte_from_dpcd(dp, DP_MAX_LANE_COUNT, &data);
> -	*lane_count = DPCD_MAX_LANE_COUNT(data);
> -}
> -
> -static void exynos_dp_init_training(struct exynos_dp_device *dp,
> -			enum link_lane_count_type max_lane,
> -			enum link_rate_type max_rate)
> -{
> -	/*
> -	 * MACRO_RST must be applied after the PLL_LOCK to avoid
> -	 * the DP inter pair skew issue for at least 10 us
> -	 */
> -	exynos_dp_reset_macro(dp);
> -
> -	/* Initialize by reading RX's DPCD */
> -	exynos_dp_get_max_rx_bandwidth(dp, &dp->link_train.link_rate);
> -	exynos_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
> -
> -	if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
> -	   (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
> -		dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
> -			dp->link_train.link_rate);
> -		dp->link_train.link_rate = LINK_RATE_1_62GBPS;
> -	}
> -
> -	if (dp->link_train.lane_count == 0) {
> -		dev_err(dp->dev, "Rx Max Lane count is abnormal :%x !\n",
> -			dp->link_train.lane_count);
> -		dp->link_train.lane_count = (u8)LANE_COUNT1;
> -	}
> -
> -	/* Setup TX lane count & rate */
> -	if (dp->link_train.lane_count > max_lane)
> -		dp->link_train.lane_count = max_lane;
> -	if (dp->link_train.link_rate > max_rate)
> -		dp->link_train.link_rate = max_rate;
> -
> -	/* All DP analog module power up */
> -	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
> -}
> -
> -static int exynos_dp_sw_link_training(struct exynos_dp_device *dp)
> +static int exynos_dp_poweron(struct analogix_dp_plat_data *plat_data)
>   {
> -	int retval = 0, training_finished = 0;
> -
> -	dp->link_train.lt_state = START;
> -
> -	/* Process here */
> -	while (!retval && !training_finished) {
> -		switch (dp->link_train.lt_state) {
> -		case START:
> -			retval = exynos_dp_link_start(dp);
> -			if (retval)
> -				dev_err(dp->dev, "LT link start failed!\n");
> -			break;
> -		case CLOCK_RECOVERY:
> -			retval = exynos_dp_process_clock_recovery(dp);
> -			if (retval)
> -				dev_err(dp->dev, "LT CR failed!\n");
> -			break;
> -		case EQUALIZER_TRAINING:
> -			retval = exynos_dp_process_equalizer_training(dp);
> -			if (retval)
> -				dev_err(dp->dev, "LT EQ failed!\n");
> -			break;
> -		case FINISHED:
> -			training_finished = 1;
> -			break;
> -		case FAILED:
> -			return -EREMOTEIO;
> -		}
> -	}
> -	if (retval)
> -		dev_err(dp->dev, "eDP link training failed (%d)\n", retval);
> -
> -	return retval;
> +	return exynos_dp_crtc_clock_enable(plat_data, true);
>   }
>   
> -static int exynos_dp_set_link_train(struct exynos_dp_device *dp,
> -				u32 count,
> -				u32 bwtype)
> +static int exynos_dp_poweroff(struct analogix_dp_plat_data *plat_data)
>   {
> -	int i;
> -	int retval;
> -
> -	for (i = 0; i < DP_TIMEOUT_LOOP_COUNT; i++) {
> -		exynos_dp_init_training(dp, count, bwtype);
> -		retval = exynos_dp_sw_link_training(dp);
> -		if (retval == 0)
> -			break;
> -
> -		usleep_range(100, 110);
> -	}
> -
> -	return retval;
> +	return exynos_dp_crtc_clock_enable(plat_data, false);
>   }
>   
> -static int exynos_dp_config_video(struct exynos_dp_device *dp)
> +static int exynos_dp_get_modes(struct analogix_dp_plat_data *plat_data)
>   {
> -	int retval = 0;
> -	int timeout_loop = 0;
> -	int done_count = 0;
> -
> -	exynos_dp_config_video_slave_mode(dp);
> -
> -	exynos_dp_set_video_color_format(dp);
> -
> -	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
> -		dev_err(dp->dev, "PLL is not locked yet.\n");
> -		return -EINVAL;
> -	}
> -
> -	for (;;) {
> -		timeout_loop++;
> -		if (exynos_dp_is_slave_video_stream_clock_on(dp) == 0)
> -			break;
> -		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> -			dev_err(dp->dev, "Timeout of video streamclk ok\n");
> -			return -ETIMEDOUT;
> -		}
> -
> -		usleep_range(1, 2);
> -	}
> -
> -	/* Set to use the register calculated M/N video */
> -	exynos_dp_set_video_cr_mn(dp, CALCULATED_M, 0, 0);
> -
> -	/* For video bist, Video timing must be generated by register */
> -	exynos_dp_set_video_timing_mode(dp, VIDEO_TIMING_FROM_CAPTURE);
> -
> -	/* Disable video mute */
> -	exynos_dp_enable_video_mute(dp, 0);
> -
> -	/* Configure video slave mode */
> -	exynos_dp_enable_video_master(dp, 0);
> -
> -	timeout_loop = 0;
> -
> -	for (;;) {
> -		timeout_loop++;
> -		if (exynos_dp_is_video_stream_on(dp) == 0) {
> -			done_count++;
> -			if (done_count > 10)
> -				break;
> -		} else if (done_count) {
> -			done_count = 0;
> -		}
> -		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> -			dev_err(dp->dev, "Timeout of video streamclk ok\n");
> -			return -ETIMEDOUT;
> -		}
> -
> -		usleep_range(1000, 1001);
> -	}
> -
> -	if (retval != 0)
> -		dev_err(dp->dev, "Video stream is not detected!\n");
> -
> -	return retval;
> -}
> -
> -static void exynos_dp_enable_scramble(struct exynos_dp_device *dp, bool enable)
> -{
> -	u8 data;
> -
> -	if (enable) {
> -		exynos_dp_enable_scrambling(dp);
> -
> -		exynos_dp_read_byte_from_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			&data);
> -		exynos_dp_write_byte_to_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
> -	} else {
> -		exynos_dp_disable_scrambling(dp);
> -
> -		exynos_dp_read_byte_from_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			&data);
> -		exynos_dp_write_byte_to_dpcd(dp,
> -			DP_TRAINING_PATTERN_SET,
> -			(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
> -	}
> -}
> -
> -static irqreturn_t exynos_dp_irq_handler(int irq, void *arg)
> -{
> -	struct exynos_dp_device *dp = arg;
> -
> -	enum dp_irq_type irq_type;
> -
> -	irq_type = exynos_dp_get_irq_type(dp);
> -	switch (irq_type) {
> -	case DP_IRQ_TYPE_HP_CABLE_IN:
> -		dev_dbg(dp->dev, "Received irq - cable in\n");
> -		schedule_work(&dp->hotplug_work);
> -		exynos_dp_clear_hotplug_interrupts(dp);
> -		break;
> -	case DP_IRQ_TYPE_HP_CABLE_OUT:
> -		dev_dbg(dp->dev, "Received irq - cable out\n");
> -		exynos_dp_clear_hotplug_interrupts(dp);
> -		break;
> -	case DP_IRQ_TYPE_HP_CHANGE:
> -		/*
> -		 * We get these change notifications once in a while, but there
> -		 * is nothing we can do with them. Just ignore it for now and
> -		 * only handle cable changes.
> -		 */
> -		dev_dbg(dp->dev, "Received irq - hotplug change; ignoring.\n");
> -		exynos_dp_clear_hotplug_interrupts(dp);
> -		break;
> -	default:
> -		dev_err(dp->dev, "Received irq - unknown type!\n");
> -		break;
> -	}
> -	return IRQ_HANDLED;
> -}
> -
> -static void exynos_dp_hotplug(struct work_struct *work)
> -{
> -	struct exynos_dp_device *dp;
> -
> -	dp = container_of(work, struct exynos_dp_device, hotplug_work);
> -
> -	if (dp->drm_dev)
> -		drm_helper_hpd_irq_event(dp->drm_dev);
> -}
> -
> -static void exynos_dp_commit(struct drm_encoder *encoder)
> -{
> -	struct exynos_dp_device *dp = encoder_to_dp(encoder);
> -	int ret;
> -
> -	/* Keep the panel disabled while we configure video */
> -	if (dp->panel) {
> -		if (drm_panel_disable(dp->panel))
> -			DRM_ERROR("failed to disable the panel\n");
> -	}
> -
> -	ret = exynos_dp_detect_hpd(dp);
> -	if (ret) {
> -		/* Cable has been disconnected, we're done */
> -		return;
> -	}
> -
> -	ret = exynos_dp_handle_edid(dp);
> -	if (ret) {
> -		dev_err(dp->dev, "unable to handle edid\n");
> -		return;
> -	}
> -
> -	ret = exynos_dp_set_link_train(dp, dp->video_info->lane_count,
> -					dp->video_info->link_rate);
> -	if (ret) {
> -		dev_err(dp->dev, "unable to do link train\n");
> -		return;
> -	}
> -
> -	exynos_dp_enable_scramble(dp, 1);
> -	exynos_dp_enable_rx_to_enhanced_mode(dp, 1);
> -	exynos_dp_enable_enhanced_mode(dp, 1);
> -
> -	exynos_dp_set_lane_count(dp, dp->video_info->lane_count);
> -	exynos_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
> -
> -	exynos_dp_init_video(dp);
> -	ret = exynos_dp_config_video(dp);
> -	if (ret)
> -		dev_err(dp->dev, "unable to config video\n");
> -
> -	/* Safe to enable the panel now */
> -	if (dp->panel) {
> -		if (drm_panel_enable(dp->panel))
> -			DRM_ERROR("failed to enable the panel\n");
> -	}
> -
> -	/* Enable video */
> -	exynos_dp_start_video(dp);
> -}
> -
> -static enum drm_connector_status exynos_dp_detect(
> -				struct drm_connector *connector, bool force)
> -{
> -	return connector_status_connected;
> -}
> -
> -static void exynos_dp_connector_destroy(struct drm_connector *connector)
> -{
> -	drm_connector_unregister(connector);
> -	drm_connector_cleanup(connector);
> -}
> -
> -static const struct drm_connector_funcs exynos_dp_connector_funcs = {
> -	.dpms = drm_atomic_helper_connector_dpms,
> -	.fill_modes = drm_helper_probe_single_connector_modes,
> -	.detect = exynos_dp_detect,
> -	.destroy = exynos_dp_connector_destroy,
> -	.reset = drm_atomic_helper_connector_reset,
> -	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> -	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> -};
> -
> -static int exynos_dp_get_modes(struct drm_connector *connector)
> -{
> -	struct exynos_dp_device *dp = ctx_from_connector(connector);
> +	struct exynos_dp_device *dp = to_dp(plat_data);
> +	struct drm_connector *connector = &dp->connector;
>   	struct drm_display_mode *mode;
> +	int num_modes = 0;
>   
> -	if (dp->panel)
> -		return drm_panel_get_modes(dp->panel);
> +	if (dp->plat_data.panel)
> +		return num_modes;
>   
>   	mode = drm_mode_create(connector->dev);
>   	if (!mode) {
>   		DRM_ERROR("failed to create a new display mode.\n");
> -		return 0;
> +		return num_modes;
>   	}
>   
>   	drm_display_mode_from_videomode(&dp->vm, mode);
> @@ -985,171 +94,31 @@ static int exynos_dp_get_modes(struct drm_connector *connector)
>   	drm_mode_set_name(mode);
>   	drm_mode_probed_add(connector, mode);
>   
> -	return 1;
> -}
> -
> -static struct drm_encoder *exynos_dp_best_encoder(
> -			struct drm_connector *connector)
> -{
> -	struct exynos_dp_device *dp = ctx_from_connector(connector);
> -
> -	return &dp->encoder;
> -}
> -
> -static const struct drm_connector_helper_funcs exynos_dp_connector_helper_funcs = {
> -	.get_modes = exynos_dp_get_modes,
> -	.best_encoder = exynos_dp_best_encoder,
> -};
> -
> -/* returns the number of bridges attached */
> -static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
> -		struct drm_encoder *encoder)
> -{
> -	int ret;
> -
> -	encoder->bridge->next = dp->ptn_bridge;
> -	dp->ptn_bridge->encoder = encoder;
> -	ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
> -	if (ret) {
> -		DRM_ERROR("Failed to attach bridge to drm\n");
> -		return ret;
> -	}
> -
> -	return 0;
> +	return num_modes + 1;
>   }
>   
> -static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
> +static int exynos_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
> +				   struct drm_bridge *bridge,
> +				   struct drm_connector *connector)
>   {
> -	struct exynos_dp_device *dp = bridge->driver_private;
> +	struct exynos_dp_device *dp = to_dp(plat_data);
>   	struct drm_encoder *encoder = &dp->encoder;
> -	struct drm_connector *connector = &dp->connector;
>   	int ret;
>   
> -	/* Pre-empt DP connector creation if there's a bridge */
> -	if (dp->ptn_bridge) {
> -		ret = exynos_drm_attach_lcd_bridge(dp, encoder);
> -		if (!ret)
> -			return 0;
> -	}
> -
> -	connector->polled = DRM_CONNECTOR_POLL_HPD;
> -
> -	ret = drm_connector_init(dp->drm_dev, connector,
> -			&exynos_dp_connector_funcs, DRM_MODE_CONNECTOR_eDP);
> -	if (ret) {
> -		DRM_ERROR("Failed to initialize connector with drm\n");
> -		return ret;
> -	}
> -
> -	drm_connector_helper_add(connector, &exynos_dp_connector_helper_funcs);
>   	drm_connector_register(connector);
> -	drm_mode_connector_attach_encoder(connector, encoder);
> -
> -	if (dp->panel)
> -		ret = drm_panel_attach(dp->panel, &dp->connector);
> -
> -	return ret;
> -}
> -
> -static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
> -{
> -	struct exynos_dp_device *dp = bridge->driver_private;
> -	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
> -
> -	if (dp->dpms_mode == DRM_MODE_DPMS_ON)
> -		return;
> -
> -	pm_runtime_get_sync(dp->dev);
> -
> -	if (dp->panel) {
> -		if (drm_panel_prepare(dp->panel)) {
> -			DRM_ERROR("failed to setup the panel\n");
> -			return;
> -		}
> -	}
> -
> -	if (crtc->ops->clock_enable)
> -		crtc->ops->clock_enable(dp_to_crtc(dp), true);
> -
> -	phy_power_on(dp->phy);
> -	exynos_dp_init_dp(dp);
> -	enable_irq(dp->irq);
> -	exynos_dp_commit(&dp->encoder);
>   
> -	dp->dpms_mode = DRM_MODE_DPMS_ON;
> -}
> -
> -static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
> -{
> -	struct exynos_dp_device *dp = bridge->driver_private;
> -	struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
> -
> -	if (dp->dpms_mode != DRM_MODE_DPMS_ON)
> -		return;
> -
> -	if (dp->panel) {
> -		if (drm_panel_disable(dp->panel)) {
> -			DRM_ERROR("failed to disable the panel\n");
> -			return;
> +	/* Pre-empt DP connector creation if there's a bridge */
> +	if (dp->ptn_bridge) {
> +		bridge->next = dp->ptn_bridge;
> +		dp->ptn_bridge->encoder = encoder;
> +		ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
> +		if (ret) {
> +			DRM_ERROR("Failed to attach bridge to drm\n");
> +			bridge->next = NULL;
> +			return ret;
>   		}
>   	}
>   
> -	disable_irq(dp->irq);
> -	flush_work(&dp->hotplug_work);
> -	phy_power_off(dp->phy);
> -
> -	if (crtc->ops->clock_enable)
> -		crtc->ops->clock_enable(dp_to_crtc(dp), false);
> -
> -	if (dp->panel) {
> -		if (drm_panel_unprepare(dp->panel))
> -			DRM_ERROR("failed to turnoff the panel\n");
> -	}
> -
> -	pm_runtime_put_sync(dp->dev);
> -
> -	dp->dpms_mode = DRM_MODE_DPMS_OFF;
> -}
> -
> -static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
> -{
> -	/* do nothing */
> -}
> -
> -static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
> -	.enable = exynos_dp_bridge_enable,
> -	.disable = exynos_dp_bridge_disable,
> -	.pre_enable = exynos_dp_bridge_nop,
> -	.post_disable = exynos_dp_bridge_nop,
> -	.attach = exynos_dp_bridge_attach,
> -};
> -
> -static int exynos_dp_create_connector(struct drm_encoder *encoder)
> -{
> -	struct exynos_dp_device *dp = encoder_to_dp(encoder);
> -	struct drm_device *drm_dev = dp->drm_dev;
> -	struct drm_bridge *bridge;
> -	int ret;
> -
> -	bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
> -	if (!bridge) {
> -		DRM_ERROR("failed to allocate for drm bridge\n");
> -		return -ENOMEM;
> -	}
> -
> -	dp->bridge = bridge;
> -
> -	encoder->bridge = bridge;
> -	bridge->driver_private = dp;
> -	bridge->encoder = encoder;
> -	bridge->funcs = &exynos_dp_bridge_funcs;
> -
> -	ret = drm_bridge_attach(drm_dev, bridge);
> -	if (ret) {
> -		DRM_ERROR("failed to attach drm bridge\n");
> -		return -EINVAL;
> -	}
> -
>   	return 0;
>   }
>   
> @@ -1159,82 +128,21 @@ static void exynos_dp_mode_set(struct drm_encoder *encoder,
>   {
>   }
>   
> -static void exynos_dp_enable(struct drm_encoder *encoder)
> -{
> -}
> -
> -static void exynos_dp_disable(struct drm_encoder *encoder)
> +static void exynos_dp_nop(struct drm_encoder *encoder)
>   {
> +	/* do nothing */
>   }
>   
>   static const struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
>   	.mode_set = exynos_dp_mode_set,
> -	.enable = exynos_dp_enable,
> -	.disable = exynos_dp_disable,
> +	.enable = exynos_dp_nop,
> +	.disable = exynos_dp_nop,
>   };
>   
>   static const struct drm_encoder_funcs exynos_dp_encoder_funcs = {
>   	.destroy = drm_encoder_cleanup,
>   };
>   
> -static struct video_info *exynos_dp_dt_parse_pdata(struct device *dev)
> -{
> -	struct device_node *dp_node = dev->of_node;
> -	struct video_info *dp_video_config;
> -
> -	dp_video_config = devm_kzalloc(dev,
> -				sizeof(*dp_video_config), GFP_KERNEL);
> -	if (!dp_video_config)
> -		return ERR_PTR(-ENOMEM);
> -
> -	dp_video_config->h_sync_polarity =
> -		of_property_read_bool(dp_node, "hsync-active-high");
> -
> -	dp_video_config->v_sync_polarity =
> -		of_property_read_bool(dp_node, "vsync-active-high");
> -
> -	dp_video_config->interlaced =
> -		of_property_read_bool(dp_node, "interlaced");
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-space",
> -				&dp_video_config->color_space)) {
> -		dev_err(dev, "failed to get color-space\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,dynamic-range",
> -				&dp_video_config->dynamic_range)) {
> -		dev_err(dev, "failed to get dynamic-range\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
> -				&dp_video_config->ycbcr_coeff)) {
> -		dev_err(dev, "failed to get ycbcr-coeff\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,color-depth",
> -				&dp_video_config->color_depth)) {
> -		dev_err(dev, "failed to get color-depth\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,link-rate",
> -				&dp_video_config->link_rate)) {
> -		dev_err(dev, "failed to get link-rate\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	if (of_property_read_u32(dp_node, "samsung,lane-count",
> -				&dp_video_config->lane_count)) {
> -		dev_err(dev, "failed to get lane-count\n");
> -		return ERR_PTR(-EINVAL);
> -	}
> -
> -	return dp_video_config;
> -}
> -
>   static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
>   {
>   	int ret;
> @@ -1250,97 +158,32 @@ static int exynos_dp_dt_parse_panel(struct exynos_dp_device *dp)
>   static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>   {
>   	struct exynos_dp_device *dp = dev_get_drvdata(dev);
> -	struct platform_device *pdev = to_platform_device(dev);
> -	struct drm_device *drm_dev = data;
>   	struct drm_encoder *encoder = &dp->encoder;
> -	struct resource *res;
> -	unsigned int irq_flags;
> -	int pipe, ret = 0;
> +	struct drm_device *drm_dev = data;
> +	int pipe, ret;
>   
> -	dp->dev = &pdev->dev;
> -	dp->dpms_mode = DRM_MODE_DPMS_OFF;
> +	/*
> +	 * Just like the probe function said, we don't need the
> +	 * device drvrate anymore, we should leave the charge to
> +	 * analogix dp driver, set the device drvdata to NULL.
> +	 */
> +	dev_set_drvdata(dev, NULL);
>   
> -	dp->video_info = exynos_dp_dt_parse_pdata(&pdev->dev);
> -	if (IS_ERR(dp->video_info))
> -		return PTR_ERR(dp->video_info);
> +	dp->dev = dev;
> +	dp->drm_dev = drm_dev;
>   
> -	dp->phy = devm_phy_get(dp->dev, "dp");
> -	if (IS_ERR(dp->phy)) {
> -		dev_err(dp->dev, "no DP phy configured\n");
> -		ret = PTR_ERR(dp->phy);
> -		if (ret) {
> -			/*
> -			 * phy itself is not enabled, so we can move forward
> -			 * assigning NULL to phy pointer.
> -			 */
> -			if (ret == -ENOSYS || ret == -ENODEV)
> -				dp->phy = NULL;
> -			else
> -				return ret;
> -		}
> -	}
> +	dp->plat_data.dev_type = EXYNOS_DP;
> +	dp->plat_data.power_on = exynos_dp_poweron;
> +	dp->plat_data.power_off = exynos_dp_poweroff;
> +	dp->plat_data.attach = exynos_dp_bridge_attach;
> +	dp->plat_data.get_modes = exynos_dp_get_modes;
>   
> -	if (!dp->panel && !dp->ptn_bridge) {
> +	if (!dp->plat_data.panel && !dp->ptn_bridge) {
>   		ret = exynos_dp_dt_parse_panel(dp);
>   		if (ret)
>   			return ret;
>   	}
>   
> -	dp->clock = devm_clk_get(&pdev->dev, "dp");
> -	if (IS_ERR(dp->clock)) {
> -		dev_err(&pdev->dev, "failed to get clock\n");
> -		return PTR_ERR(dp->clock);
> -	}
> -
> -	clk_prepare_enable(dp->clock);
> -
> -	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -
> -	dp->reg_base = devm_ioremap_resource(&pdev->dev, res);
> -	if (IS_ERR(dp->reg_base))
> -		return PTR_ERR(dp->reg_base);
> -
> -	dp->hpd_gpio = of_get_named_gpio(dev->of_node, "samsung,hpd-gpio", 0);
> -
> -	if (gpio_is_valid(dp->hpd_gpio)) {
> -		/*
> -		 * Set up the hotplug GPIO from the device tree as an interrupt.
> -		 * Simply specifying a different interrupt in the device tree
> -		 * doesn't work since we handle hotplug rather differently when
> -		 * using a GPIO.  We also need the actual GPIO specifier so
> -		 * that we can get the current state of the GPIO.
> -		 */
> -		ret = devm_gpio_request_one(&pdev->dev, dp->hpd_gpio, GPIOF_IN,
> -					    "hpd_gpio");
> -		if (ret) {
> -			dev_err(&pdev->dev, "failed to get hpd gpio\n");
> -			return ret;
> -		}
> -		dp->irq = gpio_to_irq(dp->hpd_gpio);
> -		irq_flags = IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING;
> -	} else {
> -		dp->hpd_gpio = -ENODEV;
> -		dp->irq = platform_get_irq(pdev, 0);
> -		irq_flags = 0;
> -	}
> -
> -	if (dp->irq == -ENXIO) {
> -		dev_err(&pdev->dev, "failed to get irq\n");
> -		return -ENODEV;
> -	}
> -
> -	INIT_WORK(&dp->hotplug_work, exynos_dp_hotplug);
> -
> -	ret = devm_request_irq(&pdev->dev, dp->irq, exynos_dp_irq_handler,
> -			irq_flags, "exynos-dp", dp);
> -	if (ret) {
> -		dev_err(&pdev->dev, "failed to request irq\n");
> -		return ret;
> -	}
> -	disable_irq(dp->irq);
> -
> -	dp->drm_dev = drm_dev;
> -
>   	pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
>   						  EXYNOS_DISPLAY_TYPE_LCD);
>   	if (pipe < 0)
> @@ -1355,22 +198,15 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
>   
>   	drm_encoder_helper_add(encoder, &exynos_dp_encoder_helper_funcs);
>   
> -	ret = exynos_dp_create_connector(encoder);
> -	if (ret) {
> -		DRM_ERROR("failed to create connector ret = %d\n", ret);
> -		drm_encoder_cleanup(encoder);
> -		return ret;
> -	}
> +	dp->plat_data.encoder = encoder;
>   
> -	return 0;
> +	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
>   }
>   
>   static void exynos_dp_unbind(struct device *dev, struct device *master,
>   				void *data)
>   {
> -	struct exynos_dp_device *dp = dev_get_drvdata(dev);
> -
> -	exynos_dp_disable(&dp->encoder);
> +	return analogix_dp_unbind(dev, master, data);
>   }
>   
>   static const struct component_ops exynos_dp_ops = {
> @@ -1383,21 +219,25 @@ static int exynos_dp_probe(struct platform_device *pdev)
>   	struct device *dev = &pdev->dev;
>   	struct device_node *np = NULL, *endpoint = NULL;
>   	struct exynos_dp_device *dp;
> -	int ret;
>   
>   	dp = devm_kzalloc(&pdev->dev, sizeof(struct exynos_dp_device),
>   				GFP_KERNEL);
>   	if (!dp)
>   		return -ENOMEM;
>   
> +	/*
> +	 * We just use the drvdata until driver run into component
> +	 * add function, and then we would set drvdata to null, so
> +	 * that analogix dp driver would take charge of the drvdata.
> +	 */
>   	platform_set_drvdata(pdev, dp);
>   
>   	/* This is for the backward compatibility. */
>   	np = of_parse_phandle(dev->of_node, "panel", 0);
>   	if (np) {
> -		dp->panel = of_drm_find_panel(np);
> +		dp->plat_data.panel = of_drm_find_panel(np);
>   		of_node_put(np);
> -		if (!dp->panel)
> +		if (!dp->plat_data.panel)
>   			return -EPROBE_DEFER;
>   		goto out;
>   	}
> @@ -1407,8 +247,8 @@ static int exynos_dp_probe(struct platform_device *pdev)
>   		np = of_graph_get_remote_port_parent(endpoint);
>   		if (np) {
>   			/* The remote port can be either a panel or a bridge */
> -			dp->panel = of_drm_find_panel(np);
> -			if (!dp->panel) {
> +			dp->plat_data.panel = of_drm_find_panel(np);
> +			if (!dp->plat_data.panel) {
>   				dp->ptn_bridge = of_drm_find_bridge(np);
>   				if (!dp->ptn_bridge) {
>   					of_node_put(np);
> @@ -1426,23 +266,11 @@ static int exynos_dp_probe(struct platform_device *pdev)
>   	}
>   
>   out:
> -	pm_runtime_enable(dev);
> -
> -	ret = component_add(&pdev->dev, &exynos_dp_ops);
> -	if (ret)
> -		goto err_disable_pm_runtime;
> -
> -	return ret;
> -
> -err_disable_pm_runtime:
> -	pm_runtime_disable(dev);
> -
> -	return ret;
> +	return component_add(&pdev->dev, &exynos_dp_ops);
>   }
>   
>   static int exynos_dp_remove(struct platform_device *pdev)
>   {
> -	pm_runtime_disable(&pdev->dev);
>   	component_del(&pdev->dev, &exynos_dp_ops);
>   
>   	return 0;
> @@ -1451,25 +279,12 @@ static int exynos_dp_remove(struct platform_device *pdev)
>   #ifdef CONFIG_PM
>   static int exynos_dp_suspend(struct device *dev)
>   {
> -	struct exynos_dp_device *dp = dev_get_drvdata(dev);
> -
> -	clk_disable_unprepare(dp->clock);
> -
> -	return 0;
> +	return analogix_dp_suspend(dev);
>   }
>   
>   static int exynos_dp_resume(struct device *dev)
>   {
> -	struct exynos_dp_device *dp = dev_get_drvdata(dev);
> -	int ret;
> -
> -	ret = clk_prepare_enable(dp->clock);
> -	if (ret < 0) {
> -		DRM_ERROR("Failed to prepare_enable the clock clk [%d]\n", ret);
> -		return ret;
> -	}
> -
> -	return 0;
> +	return analogix_dp_resume(dev);
>   }
>   #endif
>   
> @@ -1495,5 +310,5 @@ struct platform_driver dp_driver = {
>   };
>   
>   MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
> -MODULE_DESCRIPTION("Samsung SoC DP Driver");
> +MODULE_DESCRIPTION("Samsung Specific Analogix-DP Driver Extension");
>   MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
> deleted file mode 100644
> index b5c2d8f..0000000
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.h
> +++ /dev/null
> @@ -1,282 +0,0 @@
> -/*
> - * Header file for Samsung DP (Display Port) interface driver.
> - *
> - * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> - * Author: Jingoo Han <jg1.han@samsung.com>
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms of the GNU General Public License as published by the
> - * Free Software Foundation; either version 2 of the License, or (at your
> - * option) any later version.
> - */
> -
> -#ifndef _EXYNOS_DP_CORE_H
> -#define _EXYNOS_DP_CORE_H
> -
> -#include <drm/drm_crtc.h>
> -#include <drm/drm_dp_helper.h>
> -#include <drm/exynos_drm.h>
> -#include <video/videomode.h>
> -
> -#include "exynos_drm_drv.h"
> -
> -#define DP_TIMEOUT_LOOP_COUNT 100
> -#define MAX_CR_LOOP 5
> -#define MAX_EQ_LOOP 5
> -
> -enum link_rate_type {
> -	LINK_RATE_1_62GBPS = 0x06,
> -	LINK_RATE_2_70GBPS = 0x0a
> -};
> -
> -enum link_lane_count_type {
> -	LANE_COUNT1 = 1,
> -	LANE_COUNT2 = 2,
> -	LANE_COUNT4 = 4
> -};
> -
> -enum link_training_state {
> -	START,
> -	CLOCK_RECOVERY,
> -	EQUALIZER_TRAINING,
> -	FINISHED,
> -	FAILED
> -};
> -
> -enum voltage_swing_level {
> -	VOLTAGE_LEVEL_0,
> -	VOLTAGE_LEVEL_1,
> -	VOLTAGE_LEVEL_2,
> -	VOLTAGE_LEVEL_3,
> -};
> -
> -enum pre_emphasis_level {
> -	PRE_EMPHASIS_LEVEL_0,
> -	PRE_EMPHASIS_LEVEL_1,
> -	PRE_EMPHASIS_LEVEL_2,
> -	PRE_EMPHASIS_LEVEL_3,
> -};
> -
> -enum pattern_set {
> -	PRBS7,
> -	D10_2,
> -	TRAINING_PTN1,
> -	TRAINING_PTN2,
> -	DP_NONE
> -};
> -
> -enum color_space {
> -	COLOR_RGB,
> -	COLOR_YCBCR422,
> -	COLOR_YCBCR444
> -};
> -
> -enum color_depth {
> -	COLOR_6,
> -	COLOR_8,
> -	COLOR_10,
> -	COLOR_12
> -};
> -
> -enum color_coefficient {
> -	COLOR_YCBCR601,
> -	COLOR_YCBCR709
> -};
> -
> -enum dynamic_range {
> -	VESA,
> -	CEA
> -};
> -
> -enum pll_status {
> -	PLL_UNLOCKED,
> -	PLL_LOCKED
> -};
> -
> -enum clock_recovery_m_value_type {
> -	CALCULATED_M,
> -	REGISTER_M
> -};
> -
> -enum video_timing_recognition_type {
> -	VIDEO_TIMING_FROM_CAPTURE,
> -	VIDEO_TIMING_FROM_REGISTER
> -};
> -
> -enum analog_power_block {
> -	AUX_BLOCK,
> -	CH0_BLOCK,
> -	CH1_BLOCK,
> -	CH2_BLOCK,
> -	CH3_BLOCK,
> -	ANALOG_TOTAL,
> -	POWER_ALL
> -};
> -
> -enum dp_irq_type {
> -	DP_IRQ_TYPE_HP_CABLE_IN,
> -	DP_IRQ_TYPE_HP_CABLE_OUT,
> -	DP_IRQ_TYPE_HP_CHANGE,
> -	DP_IRQ_TYPE_UNKNOWN,
> -};
> -
> -struct video_info {
> -	char *name;
> -
> -	bool h_sync_polarity;
> -	bool v_sync_polarity;
> -	bool interlaced;
> -
> -	enum color_space color_space;
> -	enum dynamic_range dynamic_range;
> -	enum color_coefficient ycbcr_coeff;
> -	enum color_depth color_depth;
> -
> -	enum link_rate_type link_rate;
> -	enum link_lane_count_type lane_count;
> -};
> -
> -struct link_train {
> -	int eq_loop;
> -	int cr_loop[4];
> -
> -	u8 link_rate;
> -	u8 lane_count;
> -	u8 training_lane[4];
> -
> -	enum link_training_state lt_state;
> -};
> -
> -struct exynos_dp_device {
> -	struct drm_encoder	encoder;
> -	struct device		*dev;
> -	struct drm_device	*drm_dev;
> -	struct drm_connector	connector;
> -	struct drm_panel	*panel;
> -	struct drm_bridge	*bridge;
> -	struct drm_bridge	*ptn_bridge;
> -	struct clk		*clock;
> -	unsigned int		irq;
> -	void __iomem		*reg_base;
> -
> -	struct video_info	*video_info;
> -	struct link_train	link_train;
> -	struct work_struct	hotplug_work;
> -	struct phy		*phy;
> -	int			dpms_mode;
> -	int			hpd_gpio;
> -	struct videomode	vm;
> -};
> -
> -/* exynos_dp_reg.c */
> -void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
> -void exynos_dp_stop_video(struct exynos_dp_device *dp);
> -void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
> -void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
> -void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
> -void exynos_dp_reset(struct exynos_dp_device *dp);
> -void exynos_dp_swreset(struct exynos_dp_device *dp);
> -void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
> -enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
> -void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
> -void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
> -				enum analog_power_block block,
> -				bool enable);
> -void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
> -void exynos_dp_init_hpd(struct exynos_dp_device *dp);
> -enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
> -void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
> -void exynos_dp_reset_aux(struct exynos_dp_device *dp);
> -void exynos_dp_init_aux(struct exynos_dp_device *dp);
> -int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
> -void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
> -int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
> -int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned char data);
> -int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned char *data);
> -int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char data[]);
> -int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char data[]);
> -int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr);
> -int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr,
> -				unsigned int *data);
> -int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char edid[]);
> -void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
> -void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
> -void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
> -void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
> -void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
> -void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
> -				 enum pattern_set pattern);
> -void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
> -void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
> -void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
> -void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
> -void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
> -				u32 training_lane);
> -void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
> -				u32 training_lane);
> -void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
> -				u32 training_lane);
> -void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
> -				u32 training_lane);
> -u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
> -u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
> -u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
> -u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
> -void exynos_dp_reset_macro(struct exynos_dp_device *dp);
> -void exynos_dp_init_video(struct exynos_dp_device *dp);
> -
> -void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
> -int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
> -void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
> -			enum clock_recovery_m_value_type type,
> -			u32 m_value,
> -			u32 n_value);
> -void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
> -void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
> -void exynos_dp_start_video(struct exynos_dp_device *dp);
> -int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
> -void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
> -void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
> -void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
> -
> -/* I2C EDID Chip ID, Slave Address */
> -#define I2C_EDID_DEVICE_ADDR			0x50
> -#define I2C_E_EDID_DEVICE_ADDR			0x30
> -
> -#define EDID_BLOCK_LENGTH			0x80
> -#define EDID_HEADER_PATTERN			0x00
> -#define EDID_EXTENSION_FLAG			0x7e
> -#define EDID_CHECKSUM				0x7f
> -
> -/* DP_MAX_LANE_COUNT */
> -#define DPCD_ENHANCED_FRAME_CAP(x)		(((x) >> 7) & 0x1)
> -#define DPCD_MAX_LANE_COUNT(x)			((x) & 0x1f)
> -
> -/* DP_LANE_COUNT_SET */
> -#define DPCD_LANE_COUNT_SET(x)			((x) & 0x1f)
> -
> -/* DP_TRAINING_LANE0_SET */
> -#define DPCD_PRE_EMPHASIS_SET(x)		(((x) & 0x3) << 3)
> -#define DPCD_PRE_EMPHASIS_GET(x)		(((x) >> 3) & 0x3)
> -#define DPCD_VOLTAGE_SWING_SET(x)		(((x) & 0x3) << 0)
> -#define DPCD_VOLTAGE_SWING_GET(x)		(((x) >> 0) & 0x3)
> -
> -#endif /* _EXYNOS_DP_CORE_H */
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.c b/drivers/gpu/drm/exynos/exynos_dp_reg.c
> deleted file mode 100644
> index c1f87a2..0000000
> --- a/drivers/gpu/drm/exynos/exynos_dp_reg.c
> +++ /dev/null
> @@ -1,1263 +0,0 @@
> -/*
> - * Samsung DP (Display port) register interface driver.
> - *
> - * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> - * Author: Jingoo Han <jg1.han@samsung.com>
> - *
> - * This program is free software; you can redistribute it and/or modify it
> - * under the terms of the GNU General Public License as published by the
> - * Free Software Foundation; either version 2 of the License, or (at your
> - * option) any later version.
> - */
> -
> -#include <linux/device.h>
> -#include <linux/io.h>
> -#include <linux/delay.h>
> -#include <linux/gpio.h>
> -
> -#include "exynos_dp_core.h"
> -#include "exynos_dp_reg.h"
> -
> -#define COMMON_INT_MASK_1	0
> -#define COMMON_INT_MASK_2	0
> -#define COMMON_INT_MASK_3	0
> -#define COMMON_INT_MASK_4	(HOTPLUG_CHG | HPD_LOST | PLUG)
> -#define INT_STA_MASK		INT_HPD
> -
> -void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
> -{
> -	u32 reg;
> -
> -	if (enable) {
> -		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> -		reg |= HDCP_VIDEO_MUTE;
> -		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> -	} else {
> -		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> -		reg &= ~HDCP_VIDEO_MUTE;
> -		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> -	}
> -}
> -
> -void exynos_dp_stop_video(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> -	reg &= ~VIDEO_EN;
> -	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> -}
> -
> -void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
> -{
> -	u32 reg;
> -
> -	if (enable)
> -		reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
> -			LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
> -	else
> -		reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
> -			LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
> -
> -	writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
> -}
> -
> -void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = TX_TERMINAL_CTRL_50_OHM;
> -	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
> -
> -	reg = SEL_24M | TX_DVDD_BIT_1_0625V;
> -	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
> -
> -	reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
> -	writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
> -
> -	reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
> -		TX_CUR1_2X | TX_CUR_16_MA;
> -	writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
> -
> -	reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
> -		CH1_AMP_400_MV | CH0_AMP_400_MV;
> -	writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
> -}
> -
> -void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
> -{
> -	/* Set interrupt pin assertion polarity as high */
> -	writel(INT_POL1 | INT_POL0, dp->reg_base + EXYNOS_DP_INT_CTL);
> -
> -	/* Clear pending regisers */
> -	writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
> -	writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
> -	writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
> -	writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
> -	writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
> -
> -	/* 0:mask,1: unmask */
> -	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
> -	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
> -	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
> -	writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
> -	writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
> -}
> -
> -void exynos_dp_reset(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	exynos_dp_stop_video(dp);
> -	exynos_dp_enable_video_mute(dp, 0);
> -
> -	reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
> -		AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
> -		HDCP_FUNC_EN_N | SW_FUNC_EN_N;
> -	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
> -
> -	reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
> -		SERDES_FIFO_FUNC_EN_N |
> -		LS_CLK_DOMAIN_FUNC_EN_N;
> -	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> -
> -	usleep_range(20, 30);
> -
> -	exynos_dp_lane_swap(dp, 0);
> -
> -	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
> -	writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
> -	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> -	writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> -
> -	writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
> -	writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
> -
> -	writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
> -	writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
> -
> -	writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
> -
> -	writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
> -
> -	writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
> -	writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
> -
> -	writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
> -	writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
> -
> -	writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
> -}
> -
> -void exynos_dp_swreset(struct exynos_dp_device *dp)
> -{
> -	writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
> -}
> -
> -void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	/* 0: mask, 1: unmask */
> -	reg = COMMON_INT_MASK_1;
> -	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
> -
> -	reg = COMMON_INT_MASK_2;
> -	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
> -
> -	reg = COMMON_INT_MASK_3;
> -	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
> -
> -	reg = COMMON_INT_MASK_4;
> -	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
> -
> -	reg = INT_STA_MASK;
> -	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
> -}
> -
> -enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
> -	if (reg & PLL_LOCK)
> -		return PLL_LOCKED;
> -	else
> -		return PLL_UNLOCKED;
> -}
> -
> -void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
> -{
> -	u32 reg;
> -
> -	if (enable) {
> -		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
> -		reg |= DP_PLL_PD;
> -		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
> -	} else {
> -		reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
> -		reg &= ~DP_PLL_PD;
> -		writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
> -	}
> -}
> -
> -void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
> -				enum analog_power_block block,
> -				bool enable)
> -{
> -	u32 reg;
> -
> -	switch (block) {
> -	case AUX_BLOCK:
> -		if (enable) {
> -			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> -			reg |= AUX_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		} else {
> -			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> -			reg &= ~AUX_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		}
> -		break;
> -	case CH0_BLOCK:
> -		if (enable) {
> -			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> -			reg |= CH0_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		} else {
> -			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> -			reg &= ~CH0_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		}
> -		break;
> -	case CH1_BLOCK:
> -		if (enable) {
> -			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> -			reg |= CH1_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		} else {
> -			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> -			reg &= ~CH1_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		}
> -		break;
> -	case CH2_BLOCK:
> -		if (enable) {
> -			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> -			reg |= CH2_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		} else {
> -			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> -			reg &= ~CH2_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		}
> -		break;
> -	case CH3_BLOCK:
> -		if (enable) {
> -			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> -			reg |= CH3_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		} else {
> -			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> -			reg &= ~CH3_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		}
> -		break;
> -	case ANALOG_TOTAL:
> -		if (enable) {
> -			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> -			reg |= DP_PHY_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		} else {
> -			reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
> -			reg &= ~DP_PHY_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		}
> -		break;
> -	case POWER_ALL:
> -		if (enable) {
> -			reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
> -				CH1_PD | CH0_PD;
> -			writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		} else {
> -			writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
> -		}
> -		break;
> -	default:
> -		break;
> -	}
> -}
> -
> -void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -	int timeout_loop = 0;
> -
> -	exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
> -
> -	reg = PLL_LOCK_CHG;
> -	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
> -	reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
> -	writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
> -
> -	/* Power up PLL */
> -	if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
> -		exynos_dp_set_pll_power_down(dp, 0);
> -
> -		while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
> -			timeout_loop++;
> -			if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> -				dev_err(dp->dev, "failed to get pll lock status\n");
> -				return;
> -			}
> -			usleep_range(10, 20);
> -		}
> -	}
> -
> -	/* Enable Serdes FIFO function and Link symbol clock domain module */
> -	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> -	reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
> -		| AUX_FUNC_EN_N);
> -	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> -}
> -
> -void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	if (gpio_is_valid(dp->hpd_gpio))
> -		return;
> -
> -	reg = HOTPLUG_CHG | HPD_LOST | PLUG;
> -	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
> -
> -	reg = INT_HPD;
> -	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
> -}
> -
> -void exynos_dp_init_hpd(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	if (gpio_is_valid(dp->hpd_gpio))
> -		return;
> -
> -	exynos_dp_clear_hotplug_interrupts(dp);
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> -	reg &= ~(F_HPD | HPD_CTRL);
> -	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> -}
> -
> -enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	if (gpio_is_valid(dp->hpd_gpio)) {
> -		reg = gpio_get_value(dp->hpd_gpio);
> -		if (reg)
> -			return DP_IRQ_TYPE_HP_CABLE_IN;
> -		else
> -			return DP_IRQ_TYPE_HP_CABLE_OUT;
> -	} else {
> -		/* Parse hotplug interrupt status register */
> -		reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
> -
> -		if (reg & PLUG)
> -			return DP_IRQ_TYPE_HP_CABLE_IN;
> -
> -		if (reg & HPD_LOST)
> -			return DP_IRQ_TYPE_HP_CABLE_OUT;
> -
> -		if (reg & HOTPLUG_CHG)
> -			return DP_IRQ_TYPE_HP_CHANGE;
> -
> -		return DP_IRQ_TYPE_UNKNOWN;
> -	}
> -}
> -
> -void exynos_dp_reset_aux(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	/* Disable AUX channel module */
> -	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> -	reg |= AUX_FUNC_EN_N;
> -	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> -}
> -
> -void exynos_dp_init_aux(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	/* Clear inerrupts related to AUX channel */
> -	reg = RPLY_RECEIV | AUX_ERR;
> -	writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
> -
> -	exynos_dp_reset_aux(dp);
> -
> -	/* Disable AUX transaction H/W retry */
> -	reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
> -		AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
> -	writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL);
> -
> -	/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
> -	reg = DEFER_CTRL_EN | DEFER_COUNT(1);
> -	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
> -
> -	/* Enable AUX channel module */
> -	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> -	reg &= ~AUX_FUNC_EN_N;
> -	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
> -}
> -
> -int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	if (gpio_is_valid(dp->hpd_gpio)) {
> -		if (gpio_get_value(dp->hpd_gpio))
> -			return 0;
> -	} else {
> -		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> -		if (reg & HPD_STATUS)
> -			return 0;
> -	}
> -
> -	return -EINVAL;
> -}
> -
> -void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
> -	reg &= ~SW_FUNC_EN_N;
> -	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
> -}
> -
> -int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
> -{
> -	int reg;
> -	int retval = 0;
> -	int timeout_loop = 0;
> -
> -	/* Enable AUX CH operation */
> -	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
> -	reg |= AUX_EN;
> -	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
> -
> -	/* Is AUX CH command reply received? */
> -	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
> -	while (!(reg & RPLY_RECEIV)) {
> -		timeout_loop++;
> -		if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
> -			dev_err(dp->dev, "AUX CH command reply failed!\n");
> -			return -ETIMEDOUT;
> -		}
> -		reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
> -		usleep_range(10, 11);
> -	}
> -
> -	/* Clear interrupt source for AUX CH command reply */
> -	writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
> -
> -	/* Clear interrupt source for AUX CH access error */
> -	reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
> -	if (reg & AUX_ERR) {
> -		writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
> -		return -EREMOTEIO;
> -	}
> -
> -	/* Check AUX CH error access status */
> -	reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
> -	if ((reg & AUX_STATUS_MASK) != 0) {
> -		dev_err(dp->dev, "AUX CH error happens: %d\n\n",
> -			reg & AUX_STATUS_MASK);
> -		return -EREMOTEIO;
> -	}
> -
> -	return retval;
> -}
> -
> -int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned char data)
> -{
> -	u32 reg;
> -	int i;
> -	int retval;
> -
> -	for (i = 0; i < 3; i++) {
> -		/* Clear AUX CH data buffer */
> -		reg = BUF_CLR;
> -		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
> -
> -		/* Select DPCD device address */
> -		reg = AUX_ADDR_7_0(reg_addr);
> -		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
> -		reg = AUX_ADDR_15_8(reg_addr);
> -		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
> -		reg = AUX_ADDR_19_16(reg_addr);
> -		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
> -
> -		/* Write data buffer */
> -		reg = (unsigned int)data;
> -		writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
> -
> -		/*
> -		 * Set DisplayPort transaction and write 1 byte
> -		 * If bit 3 is 1, DisplayPort transaction.
> -		 * If Bit 3 is 0, I2C transaction.
> -		 */
> -		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
> -		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
> -
> -		/* Start AUX transaction */
> -		retval = exynos_dp_start_aux_transaction(dp);
> -		if (retval == 0)
> -			break;
> -		else
> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -				__func__);
> -	}
> -
> -	return retval;
> -}
> -
> -int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned char *data)
> -{
> -	u32 reg;
> -	int i;
> -	int retval;
> -
> -	for (i = 0; i < 3; i++) {
> -		/* Clear AUX CH data buffer */
> -		reg = BUF_CLR;
> -		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
> -
> -		/* Select DPCD device address */
> -		reg = AUX_ADDR_7_0(reg_addr);
> -		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
> -		reg = AUX_ADDR_15_8(reg_addr);
> -		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
> -		reg = AUX_ADDR_19_16(reg_addr);
> -		writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
> -
> -		/*
> -		 * Set DisplayPort transaction and read 1 byte
> -		 * If bit 3 is 1, DisplayPort transaction.
> -		 * If Bit 3 is 0, I2C transaction.
> -		 */
> -		reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
> -		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
> -
> -		/* Start AUX transaction */
> -		retval = exynos_dp_start_aux_transaction(dp);
> -		if (retval == 0)
> -			break;
> -		else
> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -				__func__);
> -	}
> -
> -	/* Read data buffer */
> -	reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
> -	*data = (unsigned char)(reg & 0xff);
> -
> -	return retval;
> -}
> -
> -int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char data[])
> -{
> -	u32 reg;
> -	unsigned int start_offset;
> -	unsigned int cur_data_count;
> -	unsigned int cur_data_idx;
> -	int i;
> -	int retval = 0;
> -
> -	/* Clear AUX CH data buffer */
> -	reg = BUF_CLR;
> -	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
> -
> -	start_offset = 0;
> -	while (start_offset < count) {
> -		/* Buffer size of AUX CH is 16 * 4bytes */
> -		if ((count - start_offset) > 16)
> -			cur_data_count = 16;
> -		else
> -			cur_data_count = count - start_offset;
> -
> -		for (i = 0; i < 3; i++) {
> -			/* Select DPCD device address */
> -			reg = AUX_ADDR_7_0(reg_addr + start_offset);
> -			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
> -			reg = AUX_ADDR_15_8(reg_addr + start_offset);
> -			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
> -			reg = AUX_ADDR_19_16(reg_addr + start_offset);
> -			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
> -
> -			for (cur_data_idx = 0; cur_data_idx < cur_data_count;
> -			     cur_data_idx++) {
> -				reg = data[start_offset + cur_data_idx];
> -				writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
> -							  + 4 * cur_data_idx);
> -			}
> -
> -			/*
> -			 * Set DisplayPort transaction and write
> -			 * If bit 3 is 1, DisplayPort transaction.
> -			 * If Bit 3 is 0, I2C transaction.
> -			 */
> -			reg = AUX_LENGTH(cur_data_count) |
> -				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
> -			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
> -
> -			/* Start AUX transaction */
> -			retval = exynos_dp_start_aux_transaction(dp);
> -			if (retval == 0)
> -				break;
> -			else
> -				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -					__func__);
> -		}
> -
> -		start_offset += cur_data_count;
> -	}
> -
> -	return retval;
> -}
> -
> -int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char data[])
> -{
> -	u32 reg;
> -	unsigned int start_offset;
> -	unsigned int cur_data_count;
> -	unsigned int cur_data_idx;
> -	int i;
> -	int retval = 0;
> -
> -	/* Clear AUX CH data buffer */
> -	reg = BUF_CLR;
> -	writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
> -
> -	start_offset = 0;
> -	while (start_offset < count) {
> -		/* Buffer size of AUX CH is 16 * 4bytes */
> -		if ((count - start_offset) > 16)
> -			cur_data_count = 16;
> -		else
> -			cur_data_count = count - start_offset;
> -
> -		/* AUX CH Request Transaction process */
> -		for (i = 0; i < 3; i++) {
> -			/* Select DPCD device address */
> -			reg = AUX_ADDR_7_0(reg_addr + start_offset);
> -			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
> -			reg = AUX_ADDR_15_8(reg_addr + start_offset);
> -			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
> -			reg = AUX_ADDR_19_16(reg_addr + start_offset);
> -			writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
> -
> -			/*
> -			 * Set DisplayPort transaction and read
> -			 * If bit 3 is 1, DisplayPort transaction.
> -			 * If Bit 3 is 0, I2C transaction.
> -			 */
> -			reg = AUX_LENGTH(cur_data_count) |
> -				AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
> -			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
> -
> -			/* Start AUX transaction */
> -			retval = exynos_dp_start_aux_transaction(dp);
> -			if (retval == 0)
> -				break;
> -			else
> -				dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -					__func__);
> -		}
> -
> -		for (cur_data_idx = 0; cur_data_idx < cur_data_count;
> -		    cur_data_idx++) {
> -			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
> -						 + 4 * cur_data_idx);
> -			data[start_offset + cur_data_idx] =
> -				(unsigned char)reg;
> -		}
> -
> -		start_offset += cur_data_count;
> -	}
> -
> -	return retval;
> -}
> -
> -int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr)
> -{
> -	u32 reg;
> -	int retval;
> -
> -	/* Set EDID device address */
> -	reg = device_addr;
> -	writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
> -	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
> -	writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
> -
> -	/* Set offset from base address of EDID device */
> -	writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
> -
> -	/*
> -	 * Set I2C transaction and write address
> -	 * If bit 3 is 1, DisplayPort transaction.
> -	 * If Bit 3 is 0, I2C transaction.
> -	 */
> -	reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
> -		AUX_TX_COMM_WRITE;
> -	writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
> -
> -	/* Start AUX transaction */
> -	retval = exynos_dp_start_aux_transaction(dp);
> -	if (retval != 0)
> -		dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
> -
> -	return retval;
> -}
> -
> -int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr,
> -				unsigned int *data)
> -{
> -	u32 reg;
> -	int i;
> -	int retval;
> -
> -	for (i = 0; i < 3; i++) {
> -		/* Clear AUX CH data buffer */
> -		reg = BUF_CLR;
> -		writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
> -
> -		/* Select EDID device */
> -		retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
> -		if (retval != 0)
> -			continue;
> -
> -		/*
> -		 * Set I2C transaction and read data
> -		 * If bit 3 is 1, DisplayPort transaction.
> -		 * If Bit 3 is 0, I2C transaction.
> -		 */
> -		reg = AUX_TX_COMM_I2C_TRANSACTION |
> -			AUX_TX_COMM_READ;
> -		writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
> -
> -		/* Start AUX transaction */
> -		retval = exynos_dp_start_aux_transaction(dp);
> -		if (retval == 0)
> -			break;
> -		else
> -			dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
> -				__func__);
> -	}
> -
> -	/* Read data */
> -	if (retval == 0)
> -		*data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
> -
> -	return retval;
> -}
> -
> -int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
> -				unsigned int device_addr,
> -				unsigned int reg_addr,
> -				unsigned int count,
> -				unsigned char edid[])
> -{
> -	u32 reg;
> -	unsigned int i, j;
> -	unsigned int cur_data_idx;
> -	unsigned int defer = 0;
> -	int retval = 0;
> -
> -	for (i = 0; i < count; i += 16) {
> -		for (j = 0; j < 3; j++) {
> -			/* Clear AUX CH data buffer */
> -			reg = BUF_CLR;
> -			writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
> -
> -			/* Set normal AUX CH command */
> -			reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
> -			reg &= ~ADDR_ONLY;
> -			writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
> -
> -			/*
> -			 * If Rx sends defer, Tx sends only reads
> -			 * request without sending address
> -			 */
> -			if (!defer)
> -				retval = exynos_dp_select_i2c_device(dp,
> -						device_addr, reg_addr + i);
> -			else
> -				defer = 0;
> -
> -			if (retval == 0) {
> -				/*
> -				 * Set I2C transaction and write data
> -				 * If bit 3 is 1, DisplayPort transaction.
> -				 * If Bit 3 is 0, I2C transaction.
> -				 */
> -				reg = AUX_LENGTH(16) |
> -					AUX_TX_COMM_I2C_TRANSACTION |
> -					AUX_TX_COMM_READ;
> -				writel(reg, dp->reg_base +
> -					EXYNOS_DP_AUX_CH_CTL_1);
> -
> -				/* Start AUX transaction */
> -				retval = exynos_dp_start_aux_transaction(dp);
> -				if (retval == 0)
> -					break;
> -				else
> -					dev_dbg(dp->dev,
> -						"%s: Aux Transaction fail!\n",
> -						__func__);
> -			}
> -			/* Check if Rx sends defer */
> -			reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
> -			if (reg == AUX_RX_COMM_AUX_DEFER ||
> -				reg == AUX_RX_COMM_I2C_DEFER) {
> -				dev_err(dp->dev, "Defer: %d\n\n", reg);
> -				defer = 1;
> -			}
> -		}
> -
> -		for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
> -			reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
> -						 + 4 * cur_data_idx);
> -			edid[i + cur_data_idx] = (unsigned char)reg;
> -		}
> -	}
> -
> -	return retval;
> -}
> -
> -void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
> -{
> -	u32 reg;
> -
> -	reg = bwtype;
> -	if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
> -		writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
> -}
> -
> -void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
> -	*bwtype = reg;
> -}
> -
> -void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
> -{
> -	u32 reg;
> -
> -	reg = count;
> -	writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
> -}
> -
> -void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
> -	*count = reg;
> -}
> -
> -void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
> -{
> -	u32 reg;
> -
> -	if (enable) {
> -		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> -		reg |= ENHANCED;
> -		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> -	} else {
> -		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> -		reg &= ~ENHANCED;
> -		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> -	}
> -}
> -
> -void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
> -				 enum pattern_set pattern)
> -{
> -	u32 reg;
> -
> -	switch (pattern) {
> -	case PRBS7:
> -		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
> -		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> -		break;
> -	case D10_2:
> -		reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
> -		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> -		break;
> -	case TRAINING_PTN1:
> -		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
> -		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> -		break;
> -	case TRAINING_PTN2:
> -		reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
> -		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> -		break;
> -	case DP_NONE:
> -		reg = SCRAMBLING_ENABLE |
> -			LINK_QUAL_PATTERN_SET_DISABLE |
> -			SW_TRAINING_PATTERN_SET_NORMAL;
> -		writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> -		break;
> -	default:
> -		break;
> -	}
> -}
> -
> -void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
> -	reg &= ~PRE_EMPHASIS_SET_MASK;
> -	reg |= level << PRE_EMPHASIS_SET_SHIFT;
> -	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
> -}
> -
> -void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
> -	reg &= ~PRE_EMPHASIS_SET_MASK;
> -	reg |= level << PRE_EMPHASIS_SET_SHIFT;
> -	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
> -}
> -
> -void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
> -	reg &= ~PRE_EMPHASIS_SET_MASK;
> -	reg |= level << PRE_EMPHASIS_SET_SHIFT;
> -	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
> -}
> -
> -void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
> -	reg &= ~PRE_EMPHASIS_SET_MASK;
> -	reg |= level << PRE_EMPHASIS_SET_SHIFT;
> -	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
> -}
> -
> -void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
> -					u32 training_lane)
> -{
> -	u32 reg;
> -
> -	reg = training_lane;
> -	writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
> -}
> -
> -void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
> -					u32 training_lane)
> -{
> -	u32 reg;
> -
> -	reg = training_lane;
> -	writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
> -}
> -
> -void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
> -					u32 training_lane)
> -{
> -	u32 reg;
> -
> -	reg = training_lane;
> -	writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
> -}
> -
> -void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
> -					u32 training_lane)
> -{
> -	u32 reg;
> -
> -	reg = training_lane;
> -	writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
> -}
> -
> -u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
> -	return reg;
> -}
> -
> -u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
> -	return reg;
> -}
> -
> -u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
> -	return reg;
> -}
> -
> -u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
> -	return reg;
> -}
> -
> -void exynos_dp_reset_macro(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
> -	reg |= MACRO_RST;
> -	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
> -
> -	/* 10 us is the minimum reset time. */
> -	usleep_range(10, 20);
> -
> -	reg &= ~MACRO_RST;
> -	writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
> -}
> -
> -void exynos_dp_init_video(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
> -	writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
> -
> -	reg = 0x0;
> -	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
> -
> -	reg = CHA_CRI(4) | CHA_CTRL;
> -	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
> -
> -	reg = 0x0;
> -	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> -
> -	reg = VID_HRES_TH(2) | VID_VRES_TH(0);
> -	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
> -}
> -
> -void exynos_dp_set_video_color_format(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	/* Configure the input color depth, color space, dynamic range */
> -	reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
> -		(dp->video_info->color_depth << IN_BPC_SHIFT) |
> -		(dp->video_info->color_space << IN_COLOR_F_SHIFT);
> -	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
> -
> -	/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
> -	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
> -	reg &= ~IN_YC_COEFFI_MASK;
> -	if (dp->video_info->ycbcr_coeff)
> -		reg |= IN_YC_COEFFI_ITU709;
> -	else
> -		reg |= IN_YC_COEFFI_ITU601;
> -	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
> -}
> -
> -int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
> -	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
> -
> -	if (!(reg & DET_STA)) {
> -		dev_dbg(dp->dev, "Input stream clock not detected.\n");
> -		return -EINVAL;
> -	}
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
> -	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
> -	dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
> -
> -	if (reg & CHA_STA) {
> -		dev_dbg(dp->dev, "Input stream clk is changing\n");
> -		return -EINVAL;
> -	}
> -
> -	return 0;
> -}
> -
> -void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
> -		enum clock_recovery_m_value_type type,
> -		u32 m_value,
> -		u32 n_value)
> -{
> -	u32 reg;
> -
> -	if (type == REGISTER_M) {
> -		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> -		reg |= FIX_M_VID;
> -		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> -		reg = m_value & 0xff;
> -		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
> -		reg = (m_value >> 8) & 0xff;
> -		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
> -		reg = (m_value >> 16) & 0xff;
> -		writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
> -
> -		reg = n_value & 0xff;
> -		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
> -		reg = (n_value >> 8) & 0xff;
> -		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
> -		reg = (n_value >> 16) & 0xff;
> -		writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
> -	} else  {
> -		reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> -		reg &= ~FIX_M_VID;
> -		writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
> -
> -		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
> -		writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
> -		writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
> -	}
> -}
> -
> -void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
> -{
> -	u32 reg;
> -
> -	if (type == VIDEO_TIMING_FROM_CAPTURE) {
> -		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> -		reg &= ~FORMAT_SEL;
> -		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> -	} else {
> -		reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> -		reg |= FORMAT_SEL;
> -		writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> -	}
> -}
> -
> -void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
> -{
> -	u32 reg;
> -
> -	if (enable) {
> -		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
> -		reg &= ~VIDEO_MODE_MASK;
> -		reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
> -		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
> -	} else {
> -		reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
> -		reg &= ~VIDEO_MODE_MASK;
> -		reg |= VIDEO_MODE_SLAVE_MODE;
> -		writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
> -	}
> -}
> -
> -void exynos_dp_start_video(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> -	reg |= VIDEO_EN;
> -	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
> -}
> -
> -int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> -	writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
> -	if (!(reg & STRM_VALID)) {
> -		dev_dbg(dp->dev, "Input video stream is not detected.\n");
> -		return -EINVAL;
> -	}
> -
> -	return 0;
> -}
> -
> -void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
> -	reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
> -	reg |= MASTER_VID_FUNC_EN_N;
> -	writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> -	reg &= ~INTERACE_SCAN_CFG;
> -	reg |= (dp->video_info->interlaced << 2);
> -	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> -	reg &= ~VSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->v_sync_polarity << 1);
> -	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> -	reg &= ~HSYNC_POLARITY_CFG;
> -	reg |= (dp->video_info->h_sync_polarity << 0);
> -	writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
> -
> -	reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
> -	writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
> -}
> -
> -void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> -	reg &= ~SCRAMBLING_DISABLE;
> -	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> -}
> -
> -void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
> -{
> -	u32 reg;
> -
> -	reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> -	reg |= SCRAMBLING_DISABLE;
> -	writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
> -}
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_reg.h b/drivers/gpu/drm/exynos/exynos_dp_reg.h
> deleted file mode 100644
> index 2e9bd0e..0000000
> --- a/drivers/gpu/drm/exynos/exynos_dp_reg.h
> +++ /dev/null
> @@ -1,366 +0,0 @@
> -/*
> - * Register definition file for Samsung DP driver
> - *
> - * Copyright (C) 2012 Samsung Electronics Co., Ltd.
> - * Author: Jingoo Han <jg1.han@samsung.com>
> - *
> - * This program is free software; you can redistribute it and/or modify
> - * it under the terms of the GNU General Public License version 2 as
> - * published by the Free Software Foundation.
> - */
> -
> -#ifndef _EXYNOS_DP_REG_H
> -#define _EXYNOS_DP_REG_H
> -
> -#define EXYNOS_DP_TX_SW_RESET			0x14
> -#define EXYNOS_DP_FUNC_EN_1			0x18
> -#define EXYNOS_DP_FUNC_EN_2			0x1C
> -#define EXYNOS_DP_VIDEO_CTL_1			0x20
> -#define EXYNOS_DP_VIDEO_CTL_2			0x24
> -#define EXYNOS_DP_VIDEO_CTL_3			0x28
> -
> -#define EXYNOS_DP_VIDEO_CTL_8			0x3C
> -#define EXYNOS_DP_VIDEO_CTL_10			0x44
> -
> -#define EXYNOS_DP_LANE_MAP			0x35C
> -
> -#define EXYNOS_DP_ANALOG_CTL_1			0x370
> -#define EXYNOS_DP_ANALOG_CTL_2			0x374
> -#define EXYNOS_DP_ANALOG_CTL_3			0x378
> -#define EXYNOS_DP_PLL_FILTER_CTL_1		0x37C
> -#define EXYNOS_DP_TX_AMP_TUNING_CTL		0x380
> -
> -#define EXYNOS_DP_AUX_HW_RETRY_CTL		0x390
> -
> -#define EXYNOS_DP_COMMON_INT_STA_1		0x3C4
> -#define EXYNOS_DP_COMMON_INT_STA_2		0x3C8
> -#define EXYNOS_DP_COMMON_INT_STA_3		0x3CC
> -#define EXYNOS_DP_COMMON_INT_STA_4		0x3D0
> -#define EXYNOS_DP_INT_STA			0x3DC
> -#define EXYNOS_DP_COMMON_INT_MASK_1		0x3E0
> -#define EXYNOS_DP_COMMON_INT_MASK_2		0x3E4
> -#define EXYNOS_DP_COMMON_INT_MASK_3		0x3E8
> -#define EXYNOS_DP_COMMON_INT_MASK_4		0x3EC
> -#define EXYNOS_DP_INT_STA_MASK			0x3F8
> -#define EXYNOS_DP_INT_CTL			0x3FC
> -
> -#define EXYNOS_DP_SYS_CTL_1			0x600
> -#define EXYNOS_DP_SYS_CTL_2			0x604
> -#define EXYNOS_DP_SYS_CTL_3			0x608
> -#define EXYNOS_DP_SYS_CTL_4			0x60C
> -
> -#define EXYNOS_DP_PKT_SEND_CTL			0x640
> -#define EXYNOS_DP_HDCP_CTL			0x648
> -
> -#define EXYNOS_DP_LINK_BW_SET			0x680
> -#define EXYNOS_DP_LANE_COUNT_SET		0x684
> -#define EXYNOS_DP_TRAINING_PTN_SET		0x688
> -#define EXYNOS_DP_LN0_LINK_TRAINING_CTL		0x68C
> -#define EXYNOS_DP_LN1_LINK_TRAINING_CTL		0x690
> -#define EXYNOS_DP_LN2_LINK_TRAINING_CTL		0x694
> -#define EXYNOS_DP_LN3_LINK_TRAINING_CTL		0x698
> -
> -#define EXYNOS_DP_DEBUG_CTL			0x6C0
> -#define EXYNOS_DP_HPD_DEGLITCH_L		0x6C4
> -#define EXYNOS_DP_HPD_DEGLITCH_H		0x6C8
> -#define EXYNOS_DP_LINK_DEBUG_CTL		0x6E0
> -
> -#define EXYNOS_DP_M_VID_0			0x700
> -#define EXYNOS_DP_M_VID_1			0x704
> -#define EXYNOS_DP_M_VID_2			0x708
> -#define EXYNOS_DP_N_VID_0			0x70C
> -#define EXYNOS_DP_N_VID_1			0x710
> -#define EXYNOS_DP_N_VID_2			0x714
> -
> -#define EXYNOS_DP_PLL_CTL			0x71C
> -#define EXYNOS_DP_PHY_PD			0x720
> -#define EXYNOS_DP_PHY_TEST			0x724
> -
> -#define EXYNOS_DP_VIDEO_FIFO_THRD		0x730
> -#define EXYNOS_DP_AUDIO_MARGIN			0x73C
> -
> -#define EXYNOS_DP_M_VID_GEN_FILTER_TH		0x764
> -#define EXYNOS_DP_M_AUD_GEN_FILTER_TH		0x778
> -#define EXYNOS_DP_AUX_CH_STA			0x780
> -#define EXYNOS_DP_AUX_CH_DEFER_CTL		0x788
> -#define EXYNOS_DP_AUX_RX_COMM			0x78C
> -#define EXYNOS_DP_BUFFER_DATA_CTL		0x790
> -#define EXYNOS_DP_AUX_CH_CTL_1			0x794
> -#define EXYNOS_DP_AUX_ADDR_7_0			0x798
> -#define EXYNOS_DP_AUX_ADDR_15_8			0x79C
> -#define EXYNOS_DP_AUX_ADDR_19_16		0x7A0
> -#define EXYNOS_DP_AUX_CH_CTL_2			0x7A4
> -
> -#define EXYNOS_DP_BUF_DATA_0			0x7C0
> -
> -#define EXYNOS_DP_SOC_GENERAL_CTL		0x800
> -
> -/* EXYNOS_DP_TX_SW_RESET */
> -#define RESET_DP_TX				(0x1 << 0)
> -
> -/* EXYNOS_DP_FUNC_EN_1 */
> -#define MASTER_VID_FUNC_EN_N			(0x1 << 7)
> -#define SLAVE_VID_FUNC_EN_N			(0x1 << 5)
> -#define AUD_FIFO_FUNC_EN_N			(0x1 << 4)
> -#define AUD_FUNC_EN_N				(0x1 << 3)
> -#define HDCP_FUNC_EN_N				(0x1 << 2)
> -#define CRC_FUNC_EN_N				(0x1 << 1)
> -#define SW_FUNC_EN_N				(0x1 << 0)
> -
> -/* EXYNOS_DP_FUNC_EN_2 */
> -#define SSC_FUNC_EN_N				(0x1 << 7)
> -#define AUX_FUNC_EN_N				(0x1 << 2)
> -#define SERDES_FIFO_FUNC_EN_N			(0x1 << 1)
> -#define LS_CLK_DOMAIN_FUNC_EN_N			(0x1 << 0)
> -
> -/* EXYNOS_DP_VIDEO_CTL_1 */
> -#define VIDEO_EN				(0x1 << 7)
> -#define HDCP_VIDEO_MUTE				(0x1 << 6)
> -
> -/* EXYNOS_DP_VIDEO_CTL_1 */
> -#define IN_D_RANGE_MASK				(0x1 << 7)
> -#define IN_D_RANGE_SHIFT			(7)
> -#define IN_D_RANGE_CEA				(0x1 << 7)
> -#define IN_D_RANGE_VESA				(0x0 << 7)
> -#define IN_BPC_MASK				(0x7 << 4)
> -#define IN_BPC_SHIFT				(4)
> -#define IN_BPC_12_BITS				(0x3 << 4)
> -#define IN_BPC_10_BITS				(0x2 << 4)
> -#define IN_BPC_8_BITS				(0x1 << 4)
> -#define IN_BPC_6_BITS				(0x0 << 4)
> -#define IN_COLOR_F_MASK				(0x3 << 0)
> -#define IN_COLOR_F_SHIFT			(0)
> -#define IN_COLOR_F_YCBCR444			(0x2 << 0)
> -#define IN_COLOR_F_YCBCR422			(0x1 << 0)
> -#define IN_COLOR_F_RGB				(0x0 << 0)
> -
> -/* EXYNOS_DP_VIDEO_CTL_3 */
> -#define IN_YC_COEFFI_MASK			(0x1 << 7)
> -#define IN_YC_COEFFI_SHIFT			(7)
> -#define IN_YC_COEFFI_ITU709			(0x1 << 7)
> -#define IN_YC_COEFFI_ITU601			(0x0 << 7)
> -#define VID_CHK_UPDATE_TYPE_MASK		(0x1 << 4)
> -#define VID_CHK_UPDATE_TYPE_SHIFT		(4)
> -#define VID_CHK_UPDATE_TYPE_1			(0x1 << 4)
> -#define VID_CHK_UPDATE_TYPE_0			(0x0 << 4)
> -
> -/* EXYNOS_DP_VIDEO_CTL_8 */
> -#define VID_HRES_TH(x)				(((x) & 0xf) << 4)
> -#define VID_VRES_TH(x)				(((x) & 0xf) << 0)
> -
> -/* EXYNOS_DP_VIDEO_CTL_10 */
> -#define FORMAT_SEL				(0x1 << 4)
> -#define INTERACE_SCAN_CFG			(0x1 << 2)
> -#define VSYNC_POLARITY_CFG			(0x1 << 1)
> -#define HSYNC_POLARITY_CFG			(0x1 << 0)
> -
> -/* EXYNOS_DP_LANE_MAP */
> -#define LANE3_MAP_LOGIC_LANE_0			(0x0 << 6)
> -#define LANE3_MAP_LOGIC_LANE_1			(0x1 << 6)
> -#define LANE3_MAP_LOGIC_LANE_2			(0x2 << 6)
> -#define LANE3_MAP_LOGIC_LANE_3			(0x3 << 6)
> -#define LANE2_MAP_LOGIC_LANE_0			(0x0 << 4)
> -#define LANE2_MAP_LOGIC_LANE_1			(0x1 << 4)
> -#define LANE2_MAP_LOGIC_LANE_2			(0x2 << 4)
> -#define LANE2_MAP_LOGIC_LANE_3			(0x3 << 4)
> -#define LANE1_MAP_LOGIC_LANE_0			(0x0 << 2)
> -#define LANE1_MAP_LOGIC_LANE_1			(0x1 << 2)
> -#define LANE1_MAP_LOGIC_LANE_2			(0x2 << 2)
> -#define LANE1_MAP_LOGIC_LANE_3			(0x3 << 2)
> -#define LANE0_MAP_LOGIC_LANE_0			(0x0 << 0)
> -#define LANE0_MAP_LOGIC_LANE_1			(0x1 << 0)
> -#define LANE0_MAP_LOGIC_LANE_2			(0x2 << 0)
> -#define LANE0_MAP_LOGIC_LANE_3			(0x3 << 0)
> -
> -/* EXYNOS_DP_ANALOG_CTL_1 */
> -#define TX_TERMINAL_CTRL_50_OHM			(0x1 << 4)
> -
> -/* EXYNOS_DP_ANALOG_CTL_2 */
> -#define SEL_24M					(0x1 << 3)
> -#define TX_DVDD_BIT_1_0625V			(0x4 << 0)
> -
> -/* EXYNOS_DP_ANALOG_CTL_3 */
> -#define DRIVE_DVDD_BIT_1_0625V			(0x4 << 5)
> -#define VCO_BIT_600_MICRO			(0x5 << 0)
> -
> -/* EXYNOS_DP_PLL_FILTER_CTL_1 */
> -#define PD_RING_OSC				(0x1 << 6)
> -#define AUX_TERMINAL_CTRL_50_OHM		(0x2 << 4)
> -#define TX_CUR1_2X				(0x1 << 2)
> -#define TX_CUR_16_MA				(0x3 << 0)
> -
> -/* EXYNOS_DP_TX_AMP_TUNING_CTL */
> -#define CH3_AMP_400_MV				(0x0 << 24)
> -#define CH2_AMP_400_MV				(0x0 << 16)
> -#define CH1_AMP_400_MV				(0x0 << 8)
> -#define CH0_AMP_400_MV				(0x0 << 0)
> -
> -/* EXYNOS_DP_AUX_HW_RETRY_CTL */
> -#define AUX_BIT_PERIOD_EXPECTED_DELAY(x)	(((x) & 0x7) << 8)
> -#define AUX_HW_RETRY_INTERVAL_MASK		(0x3 << 3)
> -#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS	(0x0 << 3)
> -#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS	(0x1 << 3)
> -#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS	(0x2 << 3)
> -#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS	(0x3 << 3)
> -#define AUX_HW_RETRY_COUNT_SEL(x)		(((x) & 0x7) << 0)
> -
> -/* EXYNOS_DP_COMMON_INT_STA_1 */
> -#define VSYNC_DET				(0x1 << 7)
> -#define PLL_LOCK_CHG				(0x1 << 6)
> -#define SPDIF_ERR				(0x1 << 5)
> -#define SPDIF_UNSTBL				(0x1 << 4)
> -#define VID_FORMAT_CHG				(0x1 << 3)
> -#define AUD_CLK_CHG				(0x1 << 2)
> -#define VID_CLK_CHG				(0x1 << 1)
> -#define SW_INT					(0x1 << 0)
> -
> -/* EXYNOS_DP_COMMON_INT_STA_2 */
> -#define ENC_EN_CHG				(0x1 << 6)
> -#define HW_BKSV_RDY				(0x1 << 3)
> -#define HW_SHA_DONE				(0x1 << 2)
> -#define HW_AUTH_STATE_CHG			(0x1 << 1)
> -#define HW_AUTH_DONE				(0x1 << 0)
> -
> -/* EXYNOS_DP_COMMON_INT_STA_3 */
> -#define AFIFO_UNDER				(0x1 << 7)
> -#define AFIFO_OVER				(0x1 << 6)
> -#define R0_CHK_FLAG				(0x1 << 5)
> -
> -/* EXYNOS_DP_COMMON_INT_STA_4 */
> -#define PSR_ACTIVE				(0x1 << 7)
> -#define PSR_INACTIVE				(0x1 << 6)
> -#define SPDIF_BI_PHASE_ERR			(0x1 << 5)
> -#define HOTPLUG_CHG				(0x1 << 2)
> -#define HPD_LOST				(0x1 << 1)
> -#define PLUG					(0x1 << 0)
> -
> -/* EXYNOS_DP_INT_STA */
> -#define INT_HPD					(0x1 << 6)
> -#define HW_TRAINING_FINISH			(0x1 << 5)
> -#define RPLY_RECEIV				(0x1 << 1)
> -#define AUX_ERR					(0x1 << 0)
> -
> -/* EXYNOS_DP_INT_CTL */
> -#define SOFT_INT_CTRL				(0x1 << 2)
> -#define INT_POL1				(0x1 << 1)
> -#define INT_POL0				(0x1 << 0)
> -
> -/* EXYNOS_DP_SYS_CTL_1 */
> -#define DET_STA					(0x1 << 2)
> -#define FORCE_DET				(0x1 << 1)
> -#define DET_CTRL				(0x1 << 0)
> -
> -/* EXYNOS_DP_SYS_CTL_2 */
> -#define CHA_CRI(x)				(((x) & 0xf) << 4)
> -#define CHA_STA					(0x1 << 2)
> -#define FORCE_CHA				(0x1 << 1)
> -#define CHA_CTRL				(0x1 << 0)
> -
> -/* EXYNOS_DP_SYS_CTL_3 */
> -#define HPD_STATUS				(0x1 << 6)
> -#define F_HPD					(0x1 << 5)
> -#define HPD_CTRL				(0x1 << 4)
> -#define HDCP_RDY				(0x1 << 3)
> -#define STRM_VALID				(0x1 << 2)
> -#define F_VALID					(0x1 << 1)
> -#define VALID_CTRL				(0x1 << 0)
> -
> -/* EXYNOS_DP_SYS_CTL_4 */
> -#define FIX_M_AUD				(0x1 << 4)
> -#define ENHANCED				(0x1 << 3)
> -#define FIX_M_VID				(0x1 << 2)
> -#define M_VID_UPDATE_CTRL			(0x3 << 0)
> -
> -/* EXYNOS_DP_TRAINING_PTN_SET */
> -#define SCRAMBLER_TYPE				(0x1 << 9)
> -#define HW_LINK_TRAINING_PATTERN		(0x1 << 8)
> -#define SCRAMBLING_DISABLE			(0x1 << 5)
> -#define SCRAMBLING_ENABLE			(0x0 << 5)
> -#define LINK_QUAL_PATTERN_SET_MASK		(0x3 << 2)
> -#define LINK_QUAL_PATTERN_SET_PRBS7		(0x3 << 2)
> -#define LINK_QUAL_PATTERN_SET_D10_2		(0x1 << 2)
> -#define LINK_QUAL_PATTERN_SET_DISABLE		(0x0 << 2)
> -#define SW_TRAINING_PATTERN_SET_MASK		(0x3 << 0)
> -#define SW_TRAINING_PATTERN_SET_PTN2		(0x2 << 0)
> -#define SW_TRAINING_PATTERN_SET_PTN1		(0x1 << 0)
> -#define SW_TRAINING_PATTERN_SET_NORMAL		(0x0 << 0)
> -
> -/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */
> -#define PRE_EMPHASIS_SET_MASK			(0x3 << 3)
> -#define PRE_EMPHASIS_SET_SHIFT			(3)
> -
> -/* EXYNOS_DP_DEBUG_CTL */
> -#define PLL_LOCK				(0x1 << 4)
> -#define F_PLL_LOCK				(0x1 << 3)
> -#define PLL_LOCK_CTRL				(0x1 << 2)
> -#define PN_INV					(0x1 << 0)
> -
> -/* EXYNOS_DP_PLL_CTL */
> -#define DP_PLL_PD				(0x1 << 7)
> -#define DP_PLL_RESET				(0x1 << 6)
> -#define DP_PLL_LOOP_BIT_DEFAULT			(0x1 << 4)
> -#define DP_PLL_REF_BIT_1_1250V			(0x5 << 0)
> -#define DP_PLL_REF_BIT_1_2500V			(0x7 << 0)
> -
> -/* EXYNOS_DP_PHY_PD */
> -#define DP_PHY_PD				(0x1 << 5)
> -#define AUX_PD					(0x1 << 4)
> -#define CH3_PD					(0x1 << 3)
> -#define CH2_PD					(0x1 << 2)
> -#define CH1_PD					(0x1 << 1)
> -#define CH0_PD					(0x1 << 0)
> -
> -/* EXYNOS_DP_PHY_TEST */
> -#define MACRO_RST				(0x1 << 5)
> -#define CH1_TEST				(0x1 << 1)
> -#define CH0_TEST				(0x1 << 0)
> -
> -/* EXYNOS_DP_AUX_CH_STA */
> -#define AUX_BUSY				(0x1 << 4)
> -#define AUX_STATUS_MASK				(0xf << 0)
> -
> -/* EXYNOS_DP_AUX_CH_DEFER_CTL */
> -#define DEFER_CTRL_EN				(0x1 << 7)
> -#define DEFER_COUNT(x)				(((x) & 0x7f) << 0)
> -
> -/* EXYNOS_DP_AUX_RX_COMM */
> -#define AUX_RX_COMM_I2C_DEFER			(0x2 << 2)
> -#define AUX_RX_COMM_AUX_DEFER			(0x2 << 0)
> -
> -/* EXYNOS_DP_BUFFER_DATA_CTL */
> -#define BUF_CLR					(0x1 << 7)
> -#define BUF_DATA_COUNT(x)			(((x) & 0x1f) << 0)
> -
> -/* EXYNOS_DP_AUX_CH_CTL_1 */
> -#define AUX_LENGTH(x)				(((x - 1) & 0xf) << 4)
> -#define AUX_TX_COMM_MASK			(0xf << 0)
> -#define AUX_TX_COMM_DP_TRANSACTION		(0x1 << 3)
> -#define AUX_TX_COMM_I2C_TRANSACTION		(0x0 << 3)
> -#define AUX_TX_COMM_MOT				(0x1 << 2)
> -#define AUX_TX_COMM_WRITE			(0x0 << 0)
> -#define AUX_TX_COMM_READ			(0x1 << 0)
> -
> -/* EXYNOS_DP_AUX_ADDR_7_0 */
> -#define AUX_ADDR_7_0(x)				(((x) >> 0) & 0xff)
> -
> -/* EXYNOS_DP_AUX_ADDR_15_8 */
> -#define AUX_ADDR_15_8(x)			(((x) >> 8) & 0xff)
> -
> -/* EXYNOS_DP_AUX_ADDR_19_16 */
> -#define AUX_ADDR_19_16(x)			(((x) >> 16) & 0x0f)
> -
> -/* EXYNOS_DP_AUX_CH_CTL_2 */
> -#define ADDR_ONLY				(0x1 << 1)
> -#define AUX_EN					(0x1 << 0)
> -
> -/* EXYNOS_DP_SOC_GENERAL_CTL */
> -#define AUDIO_MODE_SPDIF_MODE			(0x1 << 8)
> -#define AUDIO_MODE_MASTER_MODE			(0x0 << 8)
> -#define MASTER_VIDEO_INTERLACE_EN		(0x1 << 4)
> -#define VIDEO_MASTER_CLK_SEL			(0x1 << 2)
> -#define VIDEO_MASTER_MODE_EN			(0x1 << 1)
> -#define VIDEO_MODE_MASK				(0x1 << 0)
> -#define VIDEO_MODE_SLAVE_MODE			(0x1 << 0)
> -#define VIDEO_MODE_MASTER_MODE			(0x0 << 0)
> -
> -#endif /* _EXYNOS_DP_REG_H */
> diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
> new file mode 100644
> index 0000000..d1188db
> --- /dev/null
> +++ b/include/drm/bridge/analogix_dp.h
> @@ -0,0 +1,40 @@
> +/*
> + * Analogix DP (Display Port) Core interface driver.
> + *
> + * Copyright (C) 2015 Rockchip Electronics Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +#ifndef _ANALOGIX_DP_H_
> +#define _ANALOGIX_DP_H_
> +
> +#include <drm/drm_crtc.h>
> +
> +enum analogix_dp_devtype {
> +	EXYNOS_DP,
> +};
> +
> +struct analogix_dp_plat_data {
> +	enum analogix_dp_devtype dev_type;
> +	struct drm_panel *panel;
> +	struct drm_encoder *encoder;
> +	struct drm_connector *connector;
> +
> +	int (*power_on)(struct analogix_dp_plat_data *);
> +	int (*power_off)(struct analogix_dp_plat_data *);
> +	int (*attach)(struct analogix_dp_plat_data *, struct drm_bridge *,
> +		      struct drm_connector *);
> +	int (*get_modes)(struct analogix_dp_plat_data *);
> +};
> +
> +int analogix_dp_resume(struct device *dev);
> +int analogix_dp_suspend(struct device *dev);
> +
> +int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
> +		     struct analogix_dp_plat_data *plat_data);
> +void analogix_dp_unbind(struct device *dev, struct device *master, void *data);
> +
> +#endif /* _ANALOGIX_DP_H_ */


-- 
Thanks,
Caesar

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [PATCH v14 0/17] Add Analogix Core Display Port Driver
  2016-03-18  6:41 ` [PATCH v14 0/17] Add Analogix Core Display Port Driver Caesar Wang
@ 2016-03-18 22:53   ` Doug Anderson
  2016-03-22 19:19     ` Javier Martinez Canillas
  0 siblings, 1 reply; 57+ messages in thread
From: Doug Anderson @ 2016-03-18 22:53 UTC (permalink / raw)
  To: Inki Dae, Jingoo Han, David Airlie
  Cc: Yakir Yang, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Thierry Reding, Krzysztof Kozlowski, Rob Herring,
	Heiko Stuebner, Mark Yao, devicetree, linux-samsung-soc,
	Russell King, Pawel Moll, Ian Campbell,
	open list:ARM/Rockchip SoC...,
	emil.l.velikov, linux-kernel, Daniel Kurtz,
	Kishon Vijay Abraham I, Kukjin Kim, Sean Paul, dri-devel,
	Kumar Gala, Ajay kumar, Rob Herring, Andy Yan, Gustavo Padovan,
	Caesar Wang, linux-arm-kernel, Javier Martinez Canillas

Hi,

On Thu, Mar 17, 2016 at 11:41 PM, Caesar Wang <caesar.upstream@gmail.com> wrote:
> Hi all,
>
> I pick this series up and test on C101PA chromebook, after Heiko update the
> 3 patches.
>
> [v14.1,09/17] drm: rockchip: dp: add rockchip platform dp driver
> [v14.1,04/17] drm: bridge: analogix/dp: fix some obvious code style
> [v14.1,01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge
> directory
>
> C101PA chromebook:
> http://www.amazon.co.uk/10-1-Inch-Chromebook-Rockchip-Integrated-Graphics/dp/B0107N7WT6/ref=lp_758129031_1_4?s=computers&ie=UTF8&qid=1458282912&sr=1-4
>
> So, verified for the rockchip eDp contrller on my github.
> https://github.com/Caesar-github/rockchip/tree/veyron/next-stable-chromeos

I did similar to Caesar but I tested on veyron-jerry instead of
veyron-mickey.  Like Caesar, I picked these together Heiko's v14.1
patches to resolve merge conflicts.  I also picked into a slightly
different tree (mine was a 4.4-based tree with backports, including
Heiko's latest eDP device tree patches).

Tough I haven't reviewed the code and am not a graphics expert, I'd
very much love to see this landed, presumably right after the merge
window closes.  Yakir's first patch
<https://patchwork.kernel.org/patch/6959211/> is nearly 1 year old and
it really seems like if there were any major objections left they'd
have been stated by now.  v14 appears to be about 1 month old with no
major comments.

Tested-by: Douglas Anderson <dianders@chromium.org>


-Doug

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: [PATCH v14 0/17] Add Analogix Core Display Port Driver
  2016-03-18 22:53   ` Doug Anderson
@ 2016-03-22 19:19     ` Javier Martinez Canillas
  2016-03-22 22:12       ` Who is going to merge it [Was: Re: [PATCH v14 0/17] Add Analogix Core Display Port Driver] Heiko Stübner
  0 siblings, 1 reply; 57+ messages in thread
From: Javier Martinez Canillas @ 2016-03-22 19:19 UTC (permalink / raw)
  To: Doug Anderson, Inki Dae, Jingoo Han, David Airlie
  Cc: Yakir Yang, Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim,
	Kyungmin Park, Thierry Reding, Krzysztof Kozlowski, Rob Herring,
	Heiko Stuebner, Mark Yao, devicetree, linux-samsung-soc,
	Russell King, Pawel Moll, Ian Campbell,
	open list:ARM/Rockchip SoC...,
	emil.l.velikov, linux-kernel, Daniel Kurtz,
	Kishon Vijay Abraham I, Kukjin Kim, Sean Paul, dri-devel,
	Kumar Gala, Ajay kumar, Rob Herring, Andy Yan, Gustavo Padovan,
	Caesar Wang, linux-arm-kernel

Hello,

On 03/18/2016 07:53 PM, Doug Anderson wrote:
> Hi,
> 
> On Thu, Mar 17, 2016 at 11:41 PM, Caesar Wang <caesar.upstream@gmail.com> wrote:
>> Hi all,
>>
>> I pick this series up and test on C101PA chromebook, after Heiko update the
>> 3 patches.
>>
>> [v14.1,09/17] drm: rockchip: dp: add rockchip platform dp driver
>> [v14.1,04/17] drm: bridge: analogix/dp: fix some obvious code style
>> [v14.1,01/17] drm: bridge: analogix/dp: split exynos dp driver to bridge
>> directory
>>
>> C101PA chromebook:
>> http://www.amazon.co.uk/10-1-Inch-Chromebook-Rockchip-Integrated-Graphics/dp/B0107N7WT6/ref=lp_758129031_1_4?s=computers&ie=UTF8&qid=1458282912&sr=1-4
>>
>> So, verified for the rockchip eDp contrller on my github.
>> https://github.com/Caesar-github/rockchip/tree/veyron/next-stable-chromeos
> 
> I did similar to Caesar but I tested on veyron-jerry instead of
> veyron-mickey.  Like Caesar, I picked these together Heiko's v14.1
> patches to resolve merge conflicts.  I also picked into a slightly
> different tree (mine was a 4.4-based tree with backports, including
> Heiko's latest eDP device tree patches).
>

I also tested this series on an Exynos5800 Peach Pi Chromebook, using
Heiko's branch [0] that is based on today's mainline (968f3e374fa).

I've seen no regressions with these patches, DP is working fine and
also comes up after a S2R and DPMS on/off using the exynos-drm sysfs.

NOTE: I had to cherry-pick a SPI core fix [1] in order to make the Pi
to boot. Not related to this series of course but I just mention it in
case someone else wants to do the same test on this machine.
 
> Tough I haven't reviewed the code and am not a graphics expert, I'd
> very much love to see this landed, presumably right after the merge
> window closes.  Yakir's first patch
> <https://patchwork.kernel.org/patch/6959211/> is nearly 1 year old and
> it really seems like if there were any major objections left they'd
> have been stated by now.  v14 appears to be about 1 month old with no
> major comments.
>

Same here, this is the second time I tested this series (first time was
v6 on October 25 [2]) and I think that has been out there for too long.
 
> Tested-by: Douglas Anderson <dianders@chromium.org>
> 

Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>

> 
> -Doug
> 

[0]: git://github.com/mmind/linux-rockchip.git tmp/analogix-dp-clean
[1]: http://comments.gmane.org/gmane.linux.kernel.spi.devel/23563
[2]: http://lists.infradead.org/pipermail/linux-rockchip/2015-October/004884.html

Best regards,
-- 
Javier Martinez Canillas
Open Source Group
Samsung Research America

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Who is going to merge it [Was: Re: [PATCH v14 0/17] Add Analogix Core Display Port Driver]
  2016-03-22 19:19     ` Javier Martinez Canillas
@ 2016-03-22 22:12       ` Heiko Stübner
  2016-03-22 22:44         ` Inki Dae
  0 siblings, 1 reply; 57+ messages in thread
From: Heiko Stübner @ 2016-03-22 22:12 UTC (permalink / raw)
  To: Inki Dae, David Airlie, Mark Yao
  Cc: Javier Martinez Canillas, Doug Anderson, Jingoo Han, Yakir Yang,
	Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim, Kyungmin Park,
	Thierry Reding, Krzysztof Kozlowski, Rob Herring, devicetree,
	linux-samsung-soc, Russell King, Pawel Moll, Ian Campbell,
	open list:ARM/Rockchip SoC...,
	emil.l.velikov, linux-kernel, Daniel Kurtz,
	Kishon Vijay Abraham I, Kukjin Kim, Sean Paul, dri-devel,
	Kumar Gala, Ajay kumar, Rob Herring, Andy Yan, Gustavo Padovan,
	Caesar Wang, linux-arm-kernel

Hi,

Am Dienstag, 22. März 2016, 16:19:37 schrieb Javier Martinez Canillas:
> On 03/18/2016 07:53 PM, Doug Anderson wrote:
> > On Thu, Mar 17, 2016 at 11:41 PM, Caesar Wang <caesar.upstream@gmail.com> 
wrote:
> Same here, this is the second time I tested this series (first time was
> v6 on October 25 [2]) and I think that has been out there for too long.
> 
> > Tested-by: Douglas Anderson <dianders@chromium.org>
> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>

So we have 3 tests (Doug, Caesar and me) for the Rockchip side as well as 
Javier for the Exynos side based on the most recent drm state.

As said by a lot of people it would be cool to get this merged soon - 
hopefully directly after -rc1. The only remaining question is through which 
tree it should go.

I guess there are two basic options:
- Inki takes the series - we could see the Rockchip-Ack being implied but 
maybe Mark can provide an explicit one
- Mark takes the series with an Ack from Inki for the shared parts

Inki, Mark do you have a preference?


Thanks
Heiko

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: Who is going to merge it [Was: Re: [PATCH v14 0/17] Add Analogix Core Display Port Driver]
  2016-03-22 22:12       ` Who is going to merge it [Was: Re: [PATCH v14 0/17] Add Analogix Core Display Port Driver] Heiko Stübner
@ 2016-03-22 22:44         ` Inki Dae
  2016-03-22 22:52           ` Heiko Stübner
  0 siblings, 1 reply; 57+ messages in thread
From: Inki Dae @ 2016-03-22 22:44 UTC (permalink / raw)
  To: Heiko Stübner, David Airlie, Mark Yao, Ajay Kumar
  Cc: Javier Martinez Canillas, Doug Anderson, Jingoo Han, Yakir Yang,
	Andrzej Hajda, Joonyoung Shim, Seung-Woo Kim, Kyungmin Park,
	Thierry Reding, Krzysztof Kozlowski, Rob Herring, devicetree,
	linux-samsung-soc, Russell King, Pawel Moll, Ian Campbell,
	open list:ARM/Rockchip SoC...,
	emil.l.velikov, linux-kernel, Daniel Kurtz,
	Kishon Vijay Abraham I, Kukjin Kim, Sean Paul,
	dri-devel@lists.freed esktop.org, Kumar Gala, Ajay kumar,
	Rob Herring, Andy Yan, Gustavo Padovan, Caesar Wang,
	linux-arm-kernel

+ Ajay kumar with Samsung email

Hi,

2016년 03월 23일 07:12에 Heiko Stübner 이(가) 쓴 글:
> Hi,
> 
> Am Dienstag, 22. März 2016, 16:19:37 schrieb Javier Martinez Canillas:
>> On 03/18/2016 07:53 PM, Doug Anderson wrote:
>>> On Thu, Mar 17, 2016 at 11:41 PM, Caesar Wang <caesar.upstream@gmail.com> 
> wrote:
>> Same here, this is the second time I tested this series (first time was
>> v6 on October 25 [2]) and I think that has been out there for too long.
>>
>>> Tested-by: Douglas Anderson <dianders@chromium.org>
>> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
> 
> So we have 3 tests (Doug, Caesar and me) for the Rockchip side as well as 
> Javier for the Exynos side based on the most recent drm state.
> 
> As said by a lot of people it would be cool to get this merged soon - 
> hopefully directly after -rc1. The only remaining question is through which 
> tree it should go.
> 
> I guess there are two basic options:
> - Inki takes the series - we could see the Rockchip-Ack being implied but 
> maybe Mark can provide an explicit one
> - Mark takes the series with an Ack from Inki for the shared parts
> 
> Inki, Mark do you have a preference?

The problem would be that there is no drm bridge maintainer. I think the most suitable person as the maintainer would be Ajay Kumar who is an author of drm bridge framework.
Of course, I could take them and have pull-request again. But it seems a little late. Dave had already pull-request.

To Ajay,
How about adding you as a drm bridge maintainer? DRM SoC driver maintainers would need a person who can manage the drm bridge relevant pathes.

Thanks,
Inki Dae
 
> 
> Thanks
> Heiko
> 
> 

^ permalink raw reply	[flat|nested] 57+ messages in thread

* Re: Who is going to merge it [Was: Re: [PATCH v14 0/17] Add Analogix Core Display Port Driver]
  2016-03-22 22:44         ` Inki Dae
@ 2016-03-22 22:52           ` Heiko Stübner
  2016-03-22 23:09             ` Inki Dae
  0 siblings, 1 reply; 57+ messages in thread
From: Heiko Stübner @ 2016-03-22 22:52 UTC (permalink / raw)
  To: Inki Dae
  Cc: David Airlie, Mark Yao, Ajay Kumar, Javier Martinez Canillas,
	Doug Anderson, Jingoo Han, Yakir Yang, Andrzej Hajda,
	Joonyoung Shim, Seung-Woo Kim, Kyungmin Park, Thierry Reding,
	Krzysztof Kozlowski, Rob Herring, devicetree, linux-samsung-soc,
	Russell King, Pawel Moll, Ian Campbell,
	open list:ARM/Rockchip SoC...,
	emil.l.velikov, linux-kernel, Daniel Kurtz,
	Kishon Vijay Abraham I, Kukjin Kim, Sean Paul, dri-devel,
	Kumar Gala, Ajay kumar, Rob Herring, Andy Yan, Gustavo Padovan,
	Caesar Wang, linux-arm-kernel

Am Mittwoch, 23. März 2016, 07:44:59 schrieb Inki Dae:
> + Ajay kumar with Samsung email
> 
> Hi,
> 
> 2016년 03월 23일 07:12에 Heiko Stübner 이(가) 쓴 글:
> > Hi,
> > 
> > Am Dienstag, 22. März 2016, 16:19:37 schrieb Javier Martinez Canillas:
> >> On 03/18/2016 07:53 PM, Doug Anderson wrote:
> >>> On Thu, Mar 17, 2016 at 11:41 PM, Caesar Wang
> >>> <caesar.upstream@gmail.com>
> > 
> > wrote:
> >> Same her