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From: Jaehoon Chung <jh80.chung@samsung.com>
To: linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, bhelgaas@google.com,
	robh+dt@kernel.org, mark.rutland@arm.com, kgene@kernel.org,
	krzk@kernel.org, kishon@ti.com, jingoohan1@gmail.com,
	vivek.gautam@codeaurora.org, pankaj.dubey@samsung.com,
	alim.akhtar@samsung.com, cpgs@samsung.com,
	Jaehoon Chung <jh80.chung@samsung.com>
Subject: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework
Date: Wed, 04 Jan 2017 21:34:34 +0900	[thread overview]
Message-ID: <20170104123435.30740-5-jh80.chung@samsung.com> (raw)
In-Reply-To: <20170104123435.30740-1-jh80.chung@samsung.com>

This patch is for using PHY generic framework.
To maintain backward compatibility, check whether phy is supported or
not with 'using_phy'.

And if someone use the old dt-file, display the "deprecated" message.
But it's still working fine with it.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
Changelog on V2:
- This patch is split from previous PATCH[1/4]
- Maintain the backward compatibility
- Adds 'using_phy' for cheching whether phy framework is used or not
- Adds 'DEPRECATED' message for old dt-binding way

 drivers/pci/host/pci-exynos.c | 61 +++++++++++++++++++++++++++++++++++--------
 1 file changed, 50 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index feed0fd..34f2eed 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -21,6 +21,7 @@
 #include <linux/of_gpio.h>
 #include <linux/pci.h>
 #include <linux/platform_device.h>
+#include <linux/phy/phy.h>
 #include <linux/resource.h>
 #include <linux/signal.h>
 #include <linux/types.h>
@@ -110,6 +111,10 @@ struct exynos_pcie {
 	struct exynos_pcie_clk_res	*clk_res;
 	const struct exynos_pcie_ops	*ops;
 	int				reset_gpio;
+
+	/* For Generic PHY Framework */
+	bool				using_phy;
+	struct phy			*phy;
 };
 
 struct exynos_pcie_ops {
@@ -135,6 +140,10 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
 	if (IS_ERR(ep->mem_res->elbi_base))
 		return PTR_ERR(ep->mem_res->elbi_base);
 
+	/* If using the PHY framework, doesn't need to get other resource */
+	if (ep->using_phy)
+		return 0;
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 	ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
 	if (IS_ERR(ep->mem_res->phy_base))
@@ -396,17 +405,28 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
 	}
 
 	exynos_pcie_assert_core_reset(exynos_pcie);
-	exynos_pcie_assert_phy_reset(exynos_pcie);
-	exynos_pcie_deassert_phy_reset(exynos_pcie);
-	exynos_pcie_power_on_phy(exynos_pcie);
-	exynos_pcie_init_phy(exynos_pcie);
-
-	/* pulse for common reset */
-	exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
-				PCIE_PHY_COMMON_RESET);
-	udelay(500);
-	exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
-				PCIE_PHY_COMMON_RESET);
+
+	if (exynos_pcie->using_phy) {
+		phy_reset(exynos_pcie->phy);
+
+		exynos_pcie_writel(exynos_pcie->mem_res->elbi_base, 1,
+				PCIE_PWR_RESET);
+
+		phy_power_on(exynos_pcie->phy);
+		phy_init(exynos_pcie->phy);
+	} else {
+		exynos_pcie_assert_phy_reset(exynos_pcie);
+		exynos_pcie_deassert_phy_reset(exynos_pcie);
+		exynos_pcie_power_on_phy(exynos_pcie);
+		exynos_pcie_init_phy(exynos_pcie);
+
+		/* pulse for common reset */
+		exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
+					PCIE_PHY_COMMON_RESET);
+		udelay(500);
+		exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
+					PCIE_PHY_COMMON_RESET);
+	}
 
 	exynos_pcie_deassert_core_reset(exynos_pcie);
 	dw_pcie_setup_rc(pp);
@@ -420,6 +440,11 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
 	if (!dw_pcie_wait_for_link(pp))
 		return 0;
 
+	if (exynos_pcie->using_phy) {
+		phy_power_off(exynos_pcie->phy);
+		return -ETIMEDOUT;
+	}
+
 	while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base,
 				PCIE_PHY_PLL_LOCKED) == 0) {
 		val = exynos_pcie_readl(exynos_pcie->mem_res->block_base,
@@ -633,6 +658,17 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
 
 	exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
 
+	/* Assume that controller doesn't use the PHY framework */
+	exynos_pcie->using_phy = false;
+
+	exynos_pcie->phy = devm_of_phy_get(dev, np, NULL);
+	if (IS_ERR(exynos_pcie->phy)) {
+		if (PTR_ERR(exynos_pcie->phy) == -EPROBE_DEFER)
+			return PTR_ERR(exynos_pcie->phy);
+		dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n");
+	} else
+		exynos_pcie->using_phy = true;
+
 	if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) {
 		ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie);
 		if (ret)
@@ -657,6 +693,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
 	return 0;
 
 fail_probe:
+	if (exynos_pcie->using_phy)
+		phy_exit(exynos_pcie->phy);
+
 	if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
 		exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
 	return ret;
-- 
2.10.2

  parent reply	other threads:[~2017-01-04 12:36 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20170104123435epcas1p182b241236048160fb81ac473a74540da@epcas1p1.samsung.com>
2017-01-04 12:34 ` [PATCH V2 0/5] PCI: exynos: use the PHY generic framework Jaehoon Chung
     [not found]   ` <CGME20170104123436epcas1p1d3d840e4ade396a60ce690b09d486990@epcas1p1.samsung.com>
2017-01-04 12:34     ` [PATCH V2 1/5] Documetation: samsung-phy: add the exynos-pcie-phy binding Jaehoon Chung
2017-01-04 15:17       ` Rob Herring
2017-01-05  4:16       ` Alim Akhtar
2017-01-05  6:06         ` pankaj.dubey
     [not found]   ` <CGME20170104123436epcas1p1a729583c3c2307d8539a186f1050ea98@epcas1p1.samsung.com>
2017-01-04 12:34     ` [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy Jaehoon Chung
2017-01-04 17:52       ` Krzysztof Kozlowski
2017-01-05  2:22         ` Jaehoon Chung
2017-01-04 20:21       ` Jingoo Han
2017-01-05  6:18       ` pankaj.dubey
2017-01-09 13:34       ` Alim Akhtar
2017-01-10  6:07       ` Vivek Gautam
2017-01-10  6:10         ` Jaehoon Chung
2017-01-16  8:37       ` Kishon Vijay Abraham I
2017-01-16 11:00         ` Jaehoon Chung
     [not found]   ` <CGME20170104123436epcas1p1040f1e074748fabe58af52eb0b833713@epcas1p1.samsung.com>
2017-01-04 12:34     ` [PATCH V2 3/5] Documetation: binding: modify the exynos5440 pcie binding Jaehoon Chung
2017-01-04 15:18       ` Rob Herring
2017-01-05  6:21       ` pankaj.dubey
2017-01-09 13:36       ` Alim Akhtar
     [not found]   ` <CGME20170104123436epcas1p1651443c5fe13f67006864aed2f70fa9d@epcas1p1.samsung.com>
2017-01-04 12:34     ` Jaehoon Chung [this message]
2017-01-04 17:50       ` [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework Krzysztof Kozlowski
2017-01-05  2:21         ` Jaehoon Chung
2017-01-04 19:56       ` Jingoo Han
2017-01-05  9:01       ` pankaj.dubey
2017-01-09 13:39       ` Alim Akhtar
     [not found]   ` <CGME20170104123436epcas1p10b52f24e7d6c00edb44e4331a1870e4d@epcas1p1.samsung.com>
2017-01-04 12:34     ` [PATCH V2 5/5] ARM: dts: exynos5440: support the phy-pcie node for pcie Jaehoon Chung
2017-01-04 17:58       ` Krzysztof Kozlowski
2017-01-04 18:02         ` Jingoo Han
2017-01-05  2:24         ` Jaehoon Chung
2017-01-05  9:04       ` pankaj.dubey
2017-01-12 21:01   ` [PATCH V2 0/5] PCI: exynos: use the PHY generic framework Bjorn Helgaas

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