From: Jaehoon Chung <jh80.chung@samsung.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
bhelgaas@google.com, robh+dt@kernel.org, mark.rutland@arm.com,
kgene@kernel.org, kishon@ti.com, jingoohan1@gmail.com,
vivek.gautam@codeaurora.org, pankaj.dubey@samsung.com,
alim.akhtar@samsung.com, cpgs@samsung.com
Subject: Re: [PATCH V2 5/5] ARM: dts: exynos5440: support the phy-pcie node for pcie
Date: Thu, 05 Jan 2017 11:24:24 +0900 [thread overview]
Message-ID: <76739931-33f0-a457-fae1-7ea11ea0cfea@samsung.com> (raw)
In-Reply-To: <20170104175822.5zedyszx2phiehuv@kozik-lap>
On 01/05/2017 02:58 AM, Krzysztof Kozlowski wrote:
> On Wed, Jan 04, 2017 at 09:34:35PM +0900, Jaehoon Chung wrote:
>> Add phy-pcie node for using Exynos5440 pcie.
>> And use the reg-names as "elbi" and "config".
>
> 'and' is only for joining in compound sentences, don't start with it.
Got it.
>
>> Because the getting configuratioin space address from ranges is old way.
>
> Spell-check please.
Will do.
>
>> It also is helpful to distinguish more clearly.
>
> Distinguish what? Please work on the commit msg, I am not picking
Will update the commit-msg.
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> ---
>> Changelog on V2:
>> - Removes the child-node
>> - Fixes the typo
>> - Removes the unnecessary comments
>>
>> arch/arm/boot/dts/exynos5440.dtsi | 34 ++++++++++++++++++++++------------
>> 1 file changed, 22 insertions(+), 12 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
>> index 2a2e570..feb074d 100644
>> --- a/arch/arm/boot/dts/exynos5440.dtsi
>> +++ b/arch/arm/boot/dts/exynos5440.dtsi
>> @@ -290,11 +290,22 @@
>> clock-names = "usbhost";
>> };
>>
>> + pcie_phy0: pcie-phy@270000 {
>> + #phy-cells = <0>;
>> + compatible = "samsung,exynos5440-pcie-phy";
>> + reg = <0x270000 0x1000>, <0x271000 0x40>;
>> + };
>> +
>> + pcie_phy1: pcie-phy@272000 {
>> + #phy-cells = <0>;
>> + compatible = "samsung,exynos5440-pcie-phy";
>> + reg = <0x272000 0x1000>, <0x271040 0x40>;
>> + };
>> +
>> pcie_0: pcie@290000 {
>> compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
>> - reg = <0x290000 0x1000
>> - 0x270000 0x1000
>> - 0x271000 0x40>;
>> + reg = <0x290000 0x1000>, <0x40000000 0x1000>;
>> + reg-names = "elbi", "config";
>> interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -303,9 +314,9 @@
>> #address-cells = <3>;
>> #size-cells = <2>;
>> device_type = "pci";
>> - ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
>> - 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
>> - 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
>> + phys = <&pcie_phy0>;
>> + ranges = <0x81000000 0 0 0x40001000 0 0x00010000
>> + 0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>;
>
> I think the comments were useful. You can leave them.
Ok. will keep.
>
>> #interrupt-cells = <1>;
>> interrupt-map-mask = <0 0 0 0>;
>> interrupt-map = <0x0 0 &gic 53>;
>> @@ -315,9 +326,8 @@
>>
>> pcie_1: pcie@2a0000 {
>> compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
>> - reg = <0x2a0000 0x1000
>> - 0x272000 0x1000
>> - 0x271040 0x40>;
>> + reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
>> + reg-names = "elbi", "config";
>> interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
>> <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>> @@ -326,9 +336,9 @@
>> #address-cells = <3>;
>> #size-cells = <2>;
>> device_type = "pci";
>> - ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
>> - 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
>> - 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
>> + phys = <&pcie_phy1>;
>> + ranges = <0x81000000 0 0 0x60001000 0 0x00010000
>> + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
>
> I think the comments were useful. You can leave them.
>
> This looks like depending on the changes in the driver, so I will need a
> tag or stable branch from PCIe maintainers.
Right..
Best Regards,
Jaehoon Chung
>
> Best regards,
> Krzysztof
>
>
>
next prev parent reply other threads:[~2017-01-05 2:24 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20170104123435epcas1p182b241236048160fb81ac473a74540da@epcas1p1.samsung.com>
2017-01-04 12:34 ` [PATCH V2 0/5] PCI: exynos: use the PHY generic framework Jaehoon Chung
[not found] ` <CGME20170104123436epcas1p1d3d840e4ade396a60ce690b09d486990@epcas1p1.samsung.com>
2017-01-04 12:34 ` [PATCH V2 1/5] Documetation: samsung-phy: add the exynos-pcie-phy binding Jaehoon Chung
2017-01-04 15:17 ` Rob Herring
2017-01-05 4:16 ` Alim Akhtar
2017-01-05 6:06 ` pankaj.dubey
[not found] ` <CGME20170104123436epcas1p1a729583c3c2307d8539a186f1050ea98@epcas1p1.samsung.com>
2017-01-04 12:34 ` [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy Jaehoon Chung
2017-01-04 17:52 ` Krzysztof Kozlowski
2017-01-05 2:22 ` Jaehoon Chung
2017-01-04 20:21 ` Jingoo Han
2017-01-05 6:18 ` pankaj.dubey
2017-01-09 13:34 ` Alim Akhtar
2017-01-10 6:07 ` Vivek Gautam
2017-01-10 6:10 ` Jaehoon Chung
2017-01-16 8:37 ` Kishon Vijay Abraham I
2017-01-16 11:00 ` Jaehoon Chung
[not found] ` <CGME20170104123436epcas1p1040f1e074748fabe58af52eb0b833713@epcas1p1.samsung.com>
2017-01-04 12:34 ` [PATCH V2 3/5] Documetation: binding: modify the exynos5440 pcie binding Jaehoon Chung
2017-01-04 15:18 ` Rob Herring
2017-01-05 6:21 ` pankaj.dubey
2017-01-09 13:36 ` Alim Akhtar
[not found] ` <CGME20170104123436epcas1p1651443c5fe13f67006864aed2f70fa9d@epcas1p1.samsung.com>
2017-01-04 12:34 ` [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework Jaehoon Chung
2017-01-04 17:50 ` Krzysztof Kozlowski
2017-01-05 2:21 ` Jaehoon Chung
2017-01-04 19:56 ` Jingoo Han
2017-01-05 9:01 ` pankaj.dubey
2017-01-09 13:39 ` Alim Akhtar
[not found] ` <CGME20170104123436epcas1p10b52f24e7d6c00edb44e4331a1870e4d@epcas1p1.samsung.com>
2017-01-04 12:34 ` [PATCH V2 5/5] ARM: dts: exynos5440: support the phy-pcie node for pcie Jaehoon Chung
2017-01-04 17:58 ` Krzysztof Kozlowski
2017-01-04 18:02 ` Jingoo Han
2017-01-05 2:24 ` Jaehoon Chung [this message]
2017-01-05 9:04 ` pankaj.dubey
2017-01-12 21:01 ` [PATCH V2 0/5] PCI: exynos: use the PHY generic framework Bjorn Helgaas
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=76739931-33f0-a457-fae1-7ea11ea0cfea@samsung.com \
--to=jh80.chung@samsung.com \
--cc=alim.akhtar@samsung.com \
--cc=bhelgaas@google.com \
--cc=cpgs@samsung.com \
--cc=devicetree@vger.kernel.org \
--cc=jingoohan1@gmail.com \
--cc=kgene@kernel.org \
--cc=kishon@ti.com \
--cc=krzk@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=pankaj.dubey@samsung.com \
--cc=robh+dt@kernel.org \
--cc=vivek.gautam@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).