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From: "pankaj.dubey" <pankaj.dubey@samsung.com>
To: Alim Akhtar <alim.akhtar@samsung.com>,
	Jaehoon Chung <jh80.chung@samsung.com>,
	linux-pci@vger.kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-samsung-soc@vger.kernel.org, bhelgaas@google.com,
	robh+dt@kernel.org, mark.rutland@arm.com, kgene@kernel.org,
	krzk@kernel.org, kishon@ti.com, jingoohan1@gmail.com,
	vivek.gautam@codeaurora.org, cpgs@samsung.com
Subject: Re: [PATCH V2 1/5] Documetation: samsung-phy: add the exynos-pcie-phy binding
Date: Thu, 05 Jan 2017 11:36:32 +0530	[thread overview]
Message-ID: <d6a81e81-3ac2-5d83-15f3-9de07fb2d421@samsung.com> (raw)
In-Reply-To: <4110cfa2-bbe8-337e-5f2c-13d82cd23713@samsung.com>

Hi,

On Thursday 05 January 2017 09:46 AM, Alim Akhtar wrote:
> Hi Jaehoon,
> 
> On 01/04/2017 06:04 PM, Jaehoon Chung wrote:
>> Adds the exynos-pcie-phy binding for Exynos PCIe PHY.
>> This is for using generic PHY framework.
>>
>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>> ---
>> Changelog on V2:
>> - Remove the child node.
>> - Add 2nd address to the parent reg prop.
>>
>>  Documentation/devicetree/bindings/phy/samsung-phy.txt | 17
>> +++++++++++++++++
>>  1 file changed, 17 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> b/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> index 9872ba8..ab80bfe 100644
>> --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
>> @@ -191,3 +191,20 @@ Example:
>>          usbdrdphy0 = &usb3_phy0;
>>          usbdrdphy1 = &usb3_phy1;
>>      };
>> +
>> +Samsung Exynos SoC series PCIe PHY controller
>> +--------------------------------------------------
>> +Required properties:
>> +- compatible : Should be set to "samsung,exynos5440-pcie-phy"
>> +- #phy-cells : Must be zero
>> +- reg : a register used by phy driver.
>> +    - First is for phy register, second is for block register.
>> +- reg-names : Must be set to "phy" and "block".
>> +
> In general PHY uses a "reference clock" to work, if that is true for
> 5440 also, will you consider adding an (may be) optional clock
> properties as well?
> 

Yes, right, second clock, referred as "bus_clk" in pcie node should
actually refer to "phy" clock. From Exynos5433 DT patch also you are
mapping it to CLK_PCLK_PCIE_PHY which is a phy clk. This is same in
Exynos7 as well. So better we have clocks property defined in pcie-phy
binding. What do you say?

>From Exynos5440 UM, PCIe-Phy needs 250 MHz, clock and second clock used
as "bus_clk" is providing 250 MHz, so this can be moved in phy driver.


Thanks,
Pankaj Dubey

  reply	other threads:[~2017-01-05  6:06 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20170104123435epcas1p182b241236048160fb81ac473a74540da@epcas1p1.samsung.com>
2017-01-04 12:34 ` [PATCH V2 0/5] PCI: exynos: use the PHY generic framework Jaehoon Chung
     [not found]   ` <CGME20170104123436epcas1p1d3d840e4ade396a60ce690b09d486990@epcas1p1.samsung.com>
2017-01-04 12:34     ` [PATCH V2 1/5] Documetation: samsung-phy: add the exynos-pcie-phy binding Jaehoon Chung
2017-01-04 15:17       ` Rob Herring
2017-01-05  4:16       ` Alim Akhtar
2017-01-05  6:06         ` pankaj.dubey [this message]
     [not found]   ` <CGME20170104123436epcas1p1a729583c3c2307d8539a186f1050ea98@epcas1p1.samsung.com>
2017-01-04 12:34     ` [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy Jaehoon Chung
2017-01-04 17:52       ` Krzysztof Kozlowski
2017-01-05  2:22         ` Jaehoon Chung
2017-01-04 20:21       ` Jingoo Han
2017-01-05  6:18       ` pankaj.dubey
2017-01-09 13:34       ` Alim Akhtar
2017-01-10  6:07       ` Vivek Gautam
2017-01-10  6:10         ` Jaehoon Chung
2017-01-16  8:37       ` Kishon Vijay Abraham I
2017-01-16 11:00         ` Jaehoon Chung
     [not found]   ` <CGME20170104123436epcas1p1040f1e074748fabe58af52eb0b833713@epcas1p1.samsung.com>
2017-01-04 12:34     ` [PATCH V2 3/5] Documetation: binding: modify the exynos5440 pcie binding Jaehoon Chung
2017-01-04 15:18       ` Rob Herring
2017-01-05  6:21       ` pankaj.dubey
2017-01-09 13:36       ` Alim Akhtar
     [not found]   ` <CGME20170104123436epcas1p1651443c5fe13f67006864aed2f70fa9d@epcas1p1.samsung.com>
2017-01-04 12:34     ` [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework Jaehoon Chung
2017-01-04 17:50       ` Krzysztof Kozlowski
2017-01-05  2:21         ` Jaehoon Chung
2017-01-04 19:56       ` Jingoo Han
2017-01-05  9:01       ` pankaj.dubey
2017-01-09 13:39       ` Alim Akhtar
     [not found]   ` <CGME20170104123436epcas1p10b52f24e7d6c00edb44e4331a1870e4d@epcas1p1.samsung.com>
2017-01-04 12:34     ` [PATCH V2 5/5] ARM: dts: exynos5440: support the phy-pcie node for pcie Jaehoon Chung
2017-01-04 17:58       ` Krzysztof Kozlowski
2017-01-04 18:02         ` Jingoo Han
2017-01-05  2:24         ` Jaehoon Chung
2017-01-05  9:04       ` pankaj.dubey
2017-01-12 21:01   ` [PATCH V2 0/5] PCI: exynos: use the PHY generic framework Bjorn Helgaas

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