[PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill

[PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill

[Piotr Luc]

Intel Xeon Phi processors (KNL and KNM) do support PPIN as well, so we
add their CPUIDs to the whitelist of supported processors.
PPIN is a unique number that allows to determine origin of the CPU,
from now on will be logged when an mce error occur.

Signed-off-by: Piotr Luc <piotr.luc@intel.com>
---
 arch/x86/kernel/cpu/mcheck/mce_intel.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 190b3e6..f1c44c3 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -481,6 +481,8 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
 	case INTEL_FAM6_BROADWELL_XEON_D:
 	case INTEL_FAM6_BROADWELL_X:
 	case INTEL_FAM6_SKYLAKE_X:
+	case INTEL_FAM6_XEON_PHI_KNL:
+	case INTEL_FAM6_XEON_PHI_KNM:
 		if (rdmsrl_safe(MSR_PPIN_CTL, &val))
 			return;
 
-- 
2.10.1

Re: [PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill

[Borislav Petkov]

On Sat, Apr 08, 2017 at 07:20:04PM +0200, Piotr Luc wrote:
> Intel Xeon Phi processors (KNL and KNM) do support PPIN as well, so we
> add their CPUIDs to the whitelist of supported processors.
> PPIN is a unique number that allows to determine origin of the CPU,
> from now on will be logged when an mce error occur.
> 
> Signed-off-by: Piotr Luc <piotr.luc@intel.com>
> ---
>  arch/x86/kernel/cpu/mcheck/mce_intel.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
> index 190b3e6..f1c44c3 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
> @@ -481,6 +481,8 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
>  	case INTEL_FAM6_BROADWELL_XEON_D:
>  	case INTEL_FAM6_BROADWELL_X:
>  	case INTEL_FAM6_SKYLAKE_X:
> +	case INTEL_FAM6_XEON_PHI_KNL:
> +	case INTEL_FAM6_XEON_PHI_KNM:
>  		if (rdmsrl_safe(MSR_PPIN_CTL, &val))
>  			return;
>  
> -- 

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.

[PATCH] x86/mce: Enable PPIN for Knights Landing/Mill

[Borislav Petkov]

From: Piotr Luc <piotr.luc@intel.com>

Intel Xeon Phi processors (KNL and KNM) do support PPIN as well, so add
their CPUIDs to the whitelist of supported processors.

Signed-off-by: Piotr Luc <piotr.luc@intel.com>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Cc: x86-ml <x86@kernel.org>
Link: http://lkml.kernel.org/r/20170408172004.8463-1-piotr.luc@intel.com
Signed-off-by: Borislav Petkov <bp@suse.de>
---
 arch/x86/kernel/cpu/mcheck/mce_intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 190b3e6cef4d..e84db79ef272 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -481,6 +481,9 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
 	case INTEL_FAM6_BROADWELL_XEON_D:
 	case INTEL_FAM6_BROADWELL_X:
 	case INTEL_FAM6_SKYLAKE_X:
+	case INTEL_FAM6_XEON_PHI_KNL:
+	case INTEL_FAM6_XEON_PHI_KNM:
+
 		if (rdmsrl_safe(MSR_PPIN_CTL, &val))
 			return;
 
-- 
2.11.0

[tip:ras/core] x86/mce: Enable PPIN for Knights Landing/Mill

[tip-bot for Piotr Luc]

Commit-ID:  9ea74f7c70cd5e408f1cfbda0e6836929f820d49
Gitweb:     http://git.kernel.org/tip/9ea74f7c70cd5e408f1cfbda0e6836929f820d49
Author:     Piotr Luc <piotr.luc@intel.com>
AuthorDate: Thu, 13 Apr 2017 22:10:56 +0200
Committer:  Thomas Gleixner <tglx@linutronix.de>
CommitDate: Fri, 14 Apr 2017 10:46:12 +0200

x86/mce: Enable PPIN for Knights Landing/Mill

Intel Xeon Phi processors (KNL and KNM) support PPIN as well, so add their
CPUIDs to the whitelist of supported processors.

Signed-off-by: Piotr Luc <piotr.luc@intel.com>
Signed-off-by: Borislav Petkov <bp@suse.de>
Cc: Tony Luck <tony.luck@intel.com>
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/20170408172004.8463-1-piotr.luc@intel.com
Link: http://lkml.kernel.org/r/20170413201056.10525-1-bp@alien8.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

---
 arch/x86/kernel/cpu/mcheck/mce_intel.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
index 190b3e6..e84db79 100644
--- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
+++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
@@ -481,6 +481,9 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
 	case INTEL_FAM6_BROADWELL_XEON_D:
 	case INTEL_FAM6_BROADWELL_X:
 	case INTEL_FAM6_SKYLAKE_X:
+	case INTEL_FAM6_XEON_PHI_KNL:
+	case INTEL_FAM6_XEON_PHI_KNM:
+
 		if (rdmsrl_safe(MSR_PPIN_CTL, &val))
 			return;