* [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst
@ 2017-06-23 20:31 Palmer Dabbelt
2017-06-23 20:45 ` Paul E. McKenney
0 siblings, 1 reply; 6+ messages in thread
From: Palmer Dabbelt @ 2017-06-23 20:31 UTC (permalink / raw)
To: corbet, linux-doc, linux-kernel, paulmck; +Cc: Palmer Dabbelt
I was reading the memory barries documentation in order to make sure the
RISC-V barries were correct, and I found a broken link to the atomic
operations documentation.
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Acked-by: Will Deacon <will.deacon@arm.com>
---
Documentation/memory-barriers.txt | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index 732f10ea382e..f1c9eaa45a57 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -498,11 +498,11 @@ And a couple of implicit varieties:
This means that ACQUIRE acts as a minimal "acquire" operation and
RELEASE acts as a minimal "release" operation.
-A subset of the atomic operations described in atomic_ops.txt have ACQUIRE
-and RELEASE variants in addition to fully-ordered and relaxed (no barrier
-semantics) definitions. For compound atomics performing both a load and a
-store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
-only to the store portion of the operation.
+A subset of the atomic operations described in core-api/atomic_ops.rst have
+ACQUIRE and RELEASE variants in addition to fully-ordered and relaxed (no
+barrier semantics) definitions. For compound atomics performing both a load
+and a store, ACQUIRE semantics apply only to the load and RELEASE semantics
+apply only to the store portion of the operation.
Memory barriers are only required where there's a possibility of interaction
between two CPUs or between a CPU and a device. If it can be guaranteed that
--
2.13.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst
2017-06-23 20:31 [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst Palmer Dabbelt
@ 2017-06-23 20:45 ` Paul E. McKenney
2017-06-24 14:14 ` Jonathan Corbet
0 siblings, 1 reply; 6+ messages in thread
From: Paul E. McKenney @ 2017-06-23 20:45 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: corbet, linux-doc, linux-kernel
On Fri, Jun 23, 2017 at 01:31:39PM -0700, Palmer Dabbelt wrote:
> I was reading the memory barries documentation in order to make sure the
> RISC-V barries were correct, and I found a broken link to the atomic
> operations documentation.
>
> Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
> Acked-by: Will Deacon <will.deacon@arm.com>
Good catch!
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
> ---
> Documentation/memory-barriers.txt | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
> index 732f10ea382e..f1c9eaa45a57 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -498,11 +498,11 @@ And a couple of implicit varieties:
> This means that ACQUIRE acts as a minimal "acquire" operation and
> RELEASE acts as a minimal "release" operation.
>
> -A subset of the atomic operations described in atomic_ops.txt have ACQUIRE
> -and RELEASE variants in addition to fully-ordered and relaxed (no barrier
> -semantics) definitions. For compound atomics performing both a load and a
> -store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
> -only to the store portion of the operation.
> +A subset of the atomic operations described in core-api/atomic_ops.rst have
> +ACQUIRE and RELEASE variants in addition to fully-ordered and relaxed (no
> +barrier semantics) definitions. For compound atomics performing both a load
> +and a store, ACQUIRE semantics apply only to the load and RELEASE semantics
> +apply only to the store portion of the operation.
>
> Memory barriers are only required where there's a possibility of interaction
> between two CPUs or between a CPU and a device. If it can be guaranteed that
> --
> 2.13.0
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst
2017-06-23 20:45 ` Paul E. McKenney
@ 2017-06-24 14:14 ` Jonathan Corbet
0 siblings, 0 replies; 6+ messages in thread
From: Jonathan Corbet @ 2017-06-24 14:14 UTC (permalink / raw)
To: Paul E. McKenney; +Cc: Palmer Dabbelt, linux-doc, linux-kernel
On Fri, 23 Jun 2017 13:45:29 -0700
"Paul E. McKenney" <paulmck@linux.vnet.ibm.com> wrote:
> On Fri, Jun 23, 2017 at 01:31:39PM -0700, Palmer Dabbelt wrote:
> > I was reading the memory barries documentation in order to make sure the
> > RISC-V barries were correct, and I found a broken link to the atomic
> > operations documentation.
> >
> > Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
> > Acked-by: Will Deacon <will.deacon@arm.com>
>
> Good catch!
>
> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Applied to the docs tree, thanks.
jon
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst
2017-06-23 20:29 ` Jonathan Corbet
@ 2017-06-23 20:31 ` Palmer Dabbelt
0 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2017-06-23 20:31 UTC (permalink / raw)
To: corbet; +Cc: linux-doc, linux-kernel
On Fri, 23 Jun 2017 13:29:54 PDT (-0700), corbet@lwn.net wrote:
> On Fri, 23 Jun 2017 13:25:22 -0700
> Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
>> I was reading the memory barries documentation in order to make sure the
>> RISC-V barries were correct, and I found a broken link to the atomic
>> operations documentation.
>
> This looks good to me, but can you resend with Paul McKenney on the list?
>
> "Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
>
> He generally likes to handle memory-barriers.txt changes through his tree.
Done.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst
2017-06-23 20:25 Palmer Dabbelt
@ 2017-06-23 20:29 ` Jonathan Corbet
2017-06-23 20:31 ` Palmer Dabbelt
0 siblings, 1 reply; 6+ messages in thread
From: Jonathan Corbet @ 2017-06-23 20:29 UTC (permalink / raw)
To: Palmer Dabbelt; +Cc: linux-doc, linux-kernel
On Fri, 23 Jun 2017 13:25:22 -0700
Palmer Dabbelt <palmer@dabbelt.com> wrote:
> I was reading the memory barries documentation in order to make sure the
> RISC-V barries were correct, and I found a broken link to the atomic
> operations documentation.
This looks good to me, but can you resend with Paul McKenney on the list?
"Paul E. McKenney" <paulmck@linux.vnet.ibm.com>
He generally likes to handle memory-barriers.txt changes through his tree.
Thanks,
jon
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst
@ 2017-06-23 20:25 Palmer Dabbelt
2017-06-23 20:29 ` Jonathan Corbet
0 siblings, 1 reply; 6+ messages in thread
From: Palmer Dabbelt @ 2017-06-23 20:25 UTC (permalink / raw)
To: corbet, linux-doc, linux-kernel; +Cc: Palmer Dabbelt
I was reading the memory barries documentation in order to make sure the
RISC-V barries were correct, and I found a broken link to the atomic
operations documentation.
Signed-off-by: Palmer Dabbelt <palmer@dabbelt.com>
Acked-by: Will Deacon <will.deacon@arm.com>
---
Documentation/memory-barriers.txt | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
index 732f10ea382e..f1c9eaa45a57 100644
--- a/Documentation/memory-barriers.txt
+++ b/Documentation/memory-barriers.txt
@@ -498,11 +498,11 @@ And a couple of implicit varieties:
This means that ACQUIRE acts as a minimal "acquire" operation and
RELEASE acts as a minimal "release" operation.
-A subset of the atomic operations described in atomic_ops.txt have ACQUIRE
-and RELEASE variants in addition to fully-ordered and relaxed (no barrier
-semantics) definitions. For compound atomics performing both a load and a
-store, ACQUIRE semantics apply only to the load and RELEASE semantics apply
-only to the store portion of the operation.
+A subset of the atomic operations described in core-api/atomic_ops.rst have
+ACQUIRE and RELEASE variants in addition to fully-ordered and relaxed (no
+barrier semantics) definitions. For compound atomics performing both a load
+and a store, ACQUIRE semantics apply only to the load and RELEASE semantics
+apply only to the store portion of the operation.
Memory barriers are only required where there's a possibility of interaction
between two CPUs or between a CPU and a device. If it can be guaranteed that
--
2.13.0
^ permalink raw reply related [flat|nested] 6+ messages in thread
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2017-06-23 20:31 [PATCH] Documentation: atomic_ops.txt is core-api/atomic_ops.rst Palmer Dabbelt
2017-06-23 20:45 ` Paul E. McKenney
2017-06-24 14:14 ` Jonathan Corbet
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2017-06-23 20:29 ` Jonathan Corbet
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