From: Niklas Cassel <niklas.cassel@axis.com>
To: Niklas Cassel <niklass@axis.com>,
Jesper Nilsson <jespern@axis.com>,
Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-arm-kernel@axis.com, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v4 12/17] PCI: dwc: artpec6: Split artpec6_pcie_establish_link() into smaller functions
Date: Fri, 3 Nov 2017 14:47:16 +0100 [thread overview]
Message-ID: <20171103134722.5532-13-niklas.cassel@axis.com> (raw)
In-Reply-To: <20171103134722.5532-1-niklas.cassel@axis.com>
Split artpec6_pcie_establish_link() into smaller functions
to better match other drivers such as dra7xx and imx6.
This is also done to prepare for endpoint mode support.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
---
drivers/pci/dwc/pcie-artpec6.c | 53 +++++++++++++++++++++++-------------------
1 file changed, 29 insertions(+), 24 deletions(-)
diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 18075e0fab80..3b635e745d25 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -80,18 +80,23 @@ static u64 artpec6_pcie_cpu_addr_fixup(u64 pci_addr)
return pci_addr & ARTPEC6_CPU_TO_BUS_ADDR;
}
-static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
+static int artpec6_pcie_establish_link(struct dw_pcie *pci)
{
- struct dw_pcie *pci = artpec6_pcie->pci;
- struct pcie_port *pp = &pci->pp;
+ struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
u32 val;
- unsigned int retries;
- /* Hold DW core in reset */
val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
- val |= PCIECFG_CORE_RESET_REQ;
+ val |= PCIECFG_LTSSM_ENABLE;
artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
+ return 0;
+}
+
+static void artpec6_pcie_init_phy(struct artpec6_pcie *artpec6_pcie)
+{
+ u32 val;
+ unsigned int retries;
+
val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
val |= PCIECFG_RISRCREN | /* Receiver term. 50 Ohm */
PCIECFG_MODE_TX_DRV_EN |
@@ -131,30 +136,25 @@ static int artpec6_pcie_establish_link(struct artpec6_pcie *artpec6_pcie)
val = readl(artpec6_pcie->phy_base + PHY_STATUS);
retries--;
} while (retries && !(val & PHY_COSPLLLOCK));
+}
+
+static void artpec6_pcie_assert_core_reset(struct artpec6_pcie *artpec6_pcie)
+{
+ u32 val;
- /* Take DW core out of reset */
val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
- val &= ~PCIECFG_CORE_RESET_REQ;
+ val |= PCIECFG_CORE_RESET_REQ;
artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
- usleep_range(100, 200);
+}
- /* setup root complex */
- dw_pcie_setup_rc(pp);
+static void artpec6_pcie_deassert_core_reset(struct artpec6_pcie *artpec6_pcie)
+{
+ u32 val;
- /* assert LTSSM enable */
val = artpec6_pcie_readl(artpec6_pcie, PCIECFG);
- val |= PCIECFG_LTSSM_ENABLE;
+ val &= ~PCIECFG_CORE_RESET_REQ;
artpec6_pcie_writel(artpec6_pcie, PCIECFG, val);
-
- /* check if the link is up or not */
- if (!dw_pcie_wait_for_link(pci))
- return 0;
-
- dev_dbg(pci->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
- dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
- dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
-
- return -ETIMEDOUT;
+ usleep_range(100, 200);
}
static void artpec6_pcie_enable_interrupts(struct artpec6_pcie *artpec6_pcie)
@@ -171,7 +171,12 @@ static int artpec6_pcie_host_init(struct pcie_port *pp)
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
- artpec6_pcie_establish_link(artpec6_pcie);
+ artpec6_pcie_assert_core_reset(artpec6_pcie);
+ artpec6_pcie_init_phy(artpec6_pcie);
+ artpec6_pcie_deassert_core_reset(artpec6_pcie);
+ dw_pcie_setup_rc(pp);
+ artpec6_pcie_establish_link(pci);
+ dw_pcie_wait_for_link(pci);
artpec6_pcie_enable_interrupts(artpec6_pcie);
return 0;
--
2.14.2
next prev parent reply other threads:[~2017-11-03 13:48 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-03 13:47 [PATCH v4 00/17] dwc MSI fixes, ARTPEC-6 EP mode support, ARTPEC-7 SoC support Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 01/17] PCI: dwc: Use the DMA-API to get the MSI address Niklas Cassel
2017-11-08 0:56 ` Bjorn Helgaas
2017-11-08 12:45 ` Joao Pinto
2017-11-08 17:27 ` Bjorn Helgaas
2017-11-09 9:20 ` Niklas Cassel
2017-11-21 12:18 ` Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 02/17] PCI: designware-ep: dw_pcie_ep_set_msi() should only set MMC bits Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 03/17] PCI: designware-ep: Read-only registers need DBI_RO_WR_EN to be writable Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 04/17] PCI: designware-ep: Pre-allocate memory for MSI in dw_pcie_ep_init Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 05/17] PCI: designware-ep: Remove static keyword from dw_pcie_ep_reset_bar() Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 06/17] PCI: designware-ep: Add generic function for raising MSI irq Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 07/17] PCI: dwc: dra7xx: Refactor Kconfig and Makefile handling for host/ep mode Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 08/17] PCI: dwc: dra7xx: Assign pp->ops in dra7xx_add_pcie_port() rather than in probe Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 09/17] PCI: dwc: dra7xx: Help compiler to remove unused code Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 10/17] PCI: dwc: artpec6: Remove unused defines Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 11/17] PCI: dwc: artpec6: Use BIT and GENMASK macros Niklas Cassel
2017-11-03 13:47 ` Niklas Cassel [this message]
2017-11-03 13:47 ` [PATCH v4 13/17] bindings: PCI: artpec: Add support for endpoint mode Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 14/17] PCI: dwc: artpec6: " Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 15/17] PCI: dwc: Make cpu_addr_fixup take struct dw_pcie as argument Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 16/17] bindings: PCI: artpec: Add support for the ARTPEC-7 SoC Niklas Cassel
2017-11-03 13:47 ` [PATCH v4 17/17] PCI: dwc: artpec6: " Niklas Cassel
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